meson: clk: Add support for clock gates
This patch adds support for the meson8b clock gates. Most of them are disabled by Amlogic U-Boot, but need to be enabled for ethernet, USB and many other components. Signed-off-by: Alexander Müller <serveralex@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1472319654-59048-7-git-send-email-serveralex@gmail.comsteinar/wifi_calib_4_9_kernel
Alexander Müller
Michael Turquette
parent
7ba64d82b3
commit
e31a1900c1
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@ -313,6 +313,92 @@ struct clk_gate meson8b_clk81 = {
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},
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};
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/* Everything Else (EE) domain gates */
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static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
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static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1);
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static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5);
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static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6);
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static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7);
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static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8);
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static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9);
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static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10);
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static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11);
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static MESON_GATE(meson8b_rng0, HHI_GCLK_MPEG0, 12);
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static MESON_GATE(meson8b_uart0, HHI_GCLK_MPEG0, 13);
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static MESON_GATE(meson8b_sdhc, HHI_GCLK_MPEG0, 14);
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static MESON_GATE(meson8b_stream, HHI_GCLK_MPEG0, 15);
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static MESON_GATE(meson8b_async_fifo, HHI_GCLK_MPEG0, 16);
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static MESON_GATE(meson8b_sdio, HHI_GCLK_MPEG0, 17);
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static MESON_GATE(meson8b_abuf, HHI_GCLK_MPEG0, 18);
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static MESON_GATE(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19);
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static MESON_GATE(meson8b_assist_misc, HHI_GCLK_MPEG0, 23);
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static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30);
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static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2);
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static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3);
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static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4);
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static MESON_GATE(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6);
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static MESON_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
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static MESON_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
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static MESON_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
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static MESON_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
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static MESON_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
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static MESON_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
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static MESON_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
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static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14);
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static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15);
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static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16);
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static MESON_GATE(meson8b_g2d, HHI_GCLK_MPEG1, 20);
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static MESON_GATE(meson8b_usb0, HHI_GCLK_MPEG1, 21);
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static MESON_GATE(meson8b_usb1, HHI_GCLK_MPEG1, 22);
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static MESON_GATE(meson8b_reset, HHI_GCLK_MPEG1, 23);
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static MESON_GATE(meson8b_nand, HHI_GCLK_MPEG1, 24);
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static MESON_GATE(meson8b_dos_parser, HHI_GCLK_MPEG1, 25);
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static MESON_GATE(meson8b_usb, HHI_GCLK_MPEG1, 26);
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static MESON_GATE(meson8b_vdin1, HHI_GCLK_MPEG1, 28);
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static MESON_GATE(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29);
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static MESON_GATE(meson8b_efuse, HHI_GCLK_MPEG1, 30);
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static MESON_GATE(meson8b_boot_rom, HHI_GCLK_MPEG1, 31);
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static MESON_GATE(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1);
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static MESON_GATE(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
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static MESON_GATE(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
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static MESON_GATE(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4);
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static MESON_GATE(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
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static MESON_GATE(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
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static MESON_GATE(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11);
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static MESON_GATE(meson8b_dvin, HHI_GCLK_MPEG2, 12);
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static MESON_GATE(meson8b_uart2, HHI_GCLK_MPEG2, 15);
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static MESON_GATE(meson8b_sana, HHI_GCLK_MPEG2, 22);
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static MESON_GATE(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25);
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static MESON_GATE(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
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static MESON_GATE(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29);
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static MESON_GATE(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1);
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static MESON_GATE(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2);
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static MESON_GATE(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3);
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static MESON_GATE(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4);
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static MESON_GATE(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8);
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static MESON_GATE(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9);
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static MESON_GATE(meson8b_dac_clk, HHI_GCLK_OTHER, 10);
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static MESON_GATE(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14);
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static MESON_GATE(meson8b_iec958_gate, HHI_GCLK_OTHER, 16);
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static MESON_GATE(meson8b_enc480p, HHI_GCLK_OTHER, 20);
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static MESON_GATE(meson8b_rng1, HHI_GCLK_OTHER, 21);
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static MESON_GATE(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22);
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static MESON_GATE(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
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static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25);
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static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26);
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static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31);
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/* Always On (AO) domain gates */
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static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0);
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static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
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static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
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static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
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static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
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.hws = {
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[CLKID_XTAL] = &meson8b_xtal.hw,
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@ -328,6 +414,83 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
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[CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
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[CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
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[CLKID_CLK81] = &meson8b_clk81.hw,
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[CLKID_DDR] = &meson8b_ddr.hw,
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[CLKID_DOS] = &meson8b_dos.hw,
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[CLKID_ISA] = &meson8b_isa.hw,
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[CLKID_PL301] = &meson8b_pl301.hw,
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[CLKID_PERIPHS] = &meson8b_periphs.hw,
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[CLKID_SPICC] = &meson8b_spicc.hw,
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[CLKID_I2C] = &meson8b_i2c.hw,
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[CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
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[CLKID_SMART_CARD] = &meson8b_smart_card.hw,
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[CLKID_RNG0] = &meson8b_rng0.hw,
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[CLKID_UART0] = &meson8b_uart0.hw,
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[CLKID_SDHC] = &meson8b_sdhc.hw,
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[CLKID_STREAM] = &meson8b_stream.hw,
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[CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
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[CLKID_SDIO] = &meson8b_sdio.hw,
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[CLKID_ABUF] = &meson8b_abuf.hw,
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[CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
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[CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
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[CLKID_SPI] = &meson8b_spi.hw,
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[CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
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[CLKID_ETH] = &meson8b_eth.hw,
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[CLKID_DEMUX] = &meson8b_demux.hw,
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[CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
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[CLKID_IEC958] = &meson8b_iec958.hw,
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[CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
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[CLKID_AMCLK] = &meson8b_amclk.hw,
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[CLKID_AIFIFO2] = &meson8b_aififo2.hw,
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[CLKID_MIXER] = &meson8b_mixer.hw,
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[CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
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[CLKID_ADC] = &meson8b_adc.hw,
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[CLKID_BLKMV] = &meson8b_blkmv.hw,
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[CLKID_AIU] = &meson8b_aiu.hw,
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[CLKID_UART1] = &meson8b_uart1.hw,
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[CLKID_G2D] = &meson8b_g2d.hw,
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[CLKID_USB0] = &meson8b_usb0.hw,
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[CLKID_USB1] = &meson8b_usb1.hw,
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[CLKID_RESET] = &meson8b_reset.hw,
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[CLKID_NAND] = &meson8b_nand.hw,
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[CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
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[CLKID_USB] = &meson8b_usb.hw,
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[CLKID_VDIN1] = &meson8b_vdin1.hw,
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[CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
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[CLKID_EFUSE] = &meson8b_efuse.hw,
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[CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
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[CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
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[CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
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[CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
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[CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
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[CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
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[CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
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[CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
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[CLKID_DVIN] = &meson8b_dvin.hw,
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[CLKID_UART2] = &meson8b_uart2.hw,
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[CLKID_SANA] = &meson8b_sana.hw,
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[CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
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[CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
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[CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
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[CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
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[CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
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[CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
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[CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
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[CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
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[CLKID_GCLK_VENCI_INT] = &meson8b_gclk_vencp_int.hw,
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[CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
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[CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
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[CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
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[CLKID_ENC480P] = &meson8b_enc480p.hw,
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[CLKID_RNG1] = &meson8b_rng1.hw,
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[CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
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[CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
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[CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
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[CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
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[CLKID_EDP] = &meson8b_edp.hw,
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[CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
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[CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
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[CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
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[CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
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},
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.num = CLK_NR_CLKS,
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};
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@ -338,6 +501,87 @@ static struct meson_clk_pll *const meson8b_clk_plls[] = {
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&meson8b_sys_pll,
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};
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static struct clk_gate *meson8b_clk_gates[] = {
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&meson8b_clk81,
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&meson8b_ddr,
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&meson8b_dos,
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&meson8b_isa,
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&meson8b_pl301,
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&meson8b_periphs,
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&meson8b_spicc,
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&meson8b_i2c,
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&meson8b_sar_adc,
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&meson8b_smart_card,
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&meson8b_rng0,
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&meson8b_uart0,
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&meson8b_sdhc,
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&meson8b_stream,
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&meson8b_async_fifo,
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&meson8b_sdio,
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&meson8b_abuf,
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&meson8b_hiu_iface,
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&meson8b_assist_misc,
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&meson8b_spi,
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&meson8b_i2s_spdif,
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&meson8b_eth,
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&meson8b_demux,
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&meson8b_aiu_glue,
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&meson8b_iec958,
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&meson8b_i2s_out,
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&meson8b_amclk,
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&meson8b_aififo2,
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&meson8b_mixer,
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&meson8b_mixer_iface,
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&meson8b_adc,
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&meson8b_blkmv,
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&meson8b_aiu,
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&meson8b_uart1,
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&meson8b_g2d,
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&meson8b_usb0,
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&meson8b_usb1,
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&meson8b_reset,
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&meson8b_nand,
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&meson8b_dos_parser,
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&meson8b_usb,
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&meson8b_vdin1,
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&meson8b_ahb_arb0,
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&meson8b_efuse,
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&meson8b_boot_rom,
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&meson8b_ahb_data_bus,
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&meson8b_ahb_ctrl_bus,
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&meson8b_hdmi_intr_sync,
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&meson8b_hdmi_pclk,
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&meson8b_usb1_ddr_bridge,
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&meson8b_usb0_ddr_bridge,
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&meson8b_mmc_pclk,
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&meson8b_dvin,
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&meson8b_uart2,
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&meson8b_sana,
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&meson8b_vpu_intr,
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&meson8b_sec_ahb_ahb3_bridge,
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&meson8b_clk81_a9,
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&meson8b_vclk2_venci0,
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&meson8b_vclk2_venci1,
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&meson8b_vclk2_vencp0,
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&meson8b_vclk2_vencp1,
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&meson8b_gclk_venci_int,
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&meson8b_gclk_vencp_int,
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&meson8b_dac_clk,
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&meson8b_aoclk_gate,
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&meson8b_iec958_gate,
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&meson8b_enc480p,
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&meson8b_rng1,
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&meson8b_gclk_vencl_int,
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&meson8b_vclk2_venclmcc,
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&meson8b_vclk2_vencl,
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&meson8b_vclk2_other,
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&meson8b_edp,
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&meson8b_ao_media_cpu,
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&meson8b_ao_ahb_sram,
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&meson8b_ao_ahb_bus,
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&meson8b_ao_iface,
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};
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static int meson8b_clkc_probe(struct platform_device *pdev)
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{
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void __iomem *clk_base;
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@ -365,6 +609,11 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
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meson8b_mpeg_clk_div.reg = clk_base + (u32)meson8b_mpeg_clk_div.reg;
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meson8b_clk81.reg = clk_base + (u32)meson8b_clk81.reg;
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/* Populate base address for gates */
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for (i = 0; i < ARRAY_SIZE(meson8b_clk_gates); i++)
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meson8b_clk_gates[i]->reg = clk_base +
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(u32)meson8b_clk_gates[i]->reg;
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/*
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* register all clks
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* CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
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@ -30,6 +30,11 @@
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*
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* [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
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*/
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#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
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#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */
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#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
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#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */
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#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */
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#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */
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#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */
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#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
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Loading…
Reference in New Issue