fbdev: remove blackfin drivers
The blackfin architecture is getting removed, this removes the associated fbdev drivers as well. Acked-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Acked-by: Aaron Wu <aaron.wu@analog.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
parent
8cbfbae850
commit
e3ed8b436b
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@ -580,109 +580,6 @@ config FB_VGA16
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To compile this driver as a module, choose M here: the
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module will be called vga16fb.
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config FB_BF54X_LQ043
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tristate "SHARP LQ043 TFT LCD (BF548 EZKIT)"
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depends on FB && (BF54x) && !BF542
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select FB_CFB_FILLRECT
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select FB_CFB_COPYAREA
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select FB_CFB_IMAGEBLIT
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help
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This is the framebuffer device driver for a SHARP LQ043T1DG01 TFT LCD
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config FB_BFIN_T350MCQB
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tristate "Varitronix COG-T350MCQB TFT LCD display (BF527 EZKIT)"
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depends on FB && BLACKFIN
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select BFIN_GPTIMERS
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select FB_CFB_FILLRECT
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select FB_CFB_COPYAREA
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select FB_CFB_IMAGEBLIT
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help
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This is the framebuffer device driver for a Varitronix VL-PS-COG-T350MCQB-01 display TFT LCD
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This display is a QVGA 320x240 24-bit RGB display interfaced by an 8-bit wide PPI
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It uses PPI[0..7] PPI_FS1, PPI_FS2 and PPI_CLK.
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config FB_BFIN_LQ035Q1
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tristate "SHARP LQ035Q1DH02 TFT LCD"
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depends on FB && BLACKFIN && SPI
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select FB_CFB_FILLRECT
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select FB_CFB_COPYAREA
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select FB_CFB_IMAGEBLIT
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select BFIN_GPTIMERS
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help
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This is the framebuffer device driver for a SHARP LQ035Q1DH02 TFT display found on
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the Blackfin Landscape LCD EZ-Extender Card.
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This display is a QVGA 320x240 18-bit RGB display interfaced by an 16-bit wide PPI
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It uses PPI[0..15] PPI_FS1, PPI_FS2 and PPI_CLK.
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To compile this driver as a module, choose M here: the
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module will be called bfin-lq035q1-fb.
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config FB_BF537_LQ035
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tristate "SHARP LQ035 TFT LCD (BF537 STAMP)"
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depends on FB && (BF534 || BF536 || BF537) && I2C_BLACKFIN_TWI
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select FB_CFB_FILLRECT
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select FB_CFB_COPYAREA
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select FB_CFB_IMAGEBLIT
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select BFIN_GPTIMERS
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help
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This is the framebuffer device for a SHARP LQ035Q7DB03 TFT LCD
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attached to a BF537.
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To compile this driver as a module, choose M here: the
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module will be called bf537-lq035.
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config FB_BFIN_7393
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tristate "Blackfin ADV7393 Video encoder"
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depends on FB && BLACKFIN
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select I2C
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select FB_CFB_FILLRECT
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select FB_CFB_COPYAREA
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select FB_CFB_IMAGEBLIT
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help
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This is the framebuffer device for a ADV7393 video encoder
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attached to a Blackfin on the PPI port.
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If your Blackfin board has a ADV7393 select Y.
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To compile this driver as a module, choose M here: the
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module will be called bfin_adv7393fb.
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choice
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prompt "Video mode support"
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depends on FB_BFIN_7393
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default NTSC
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config NTSC
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bool 'NTSC 720x480'
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config PAL
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bool 'PAL 720x576'
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config NTSC_640x480
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bool 'NTSC 640x480 (Experimental)'
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config PAL_640x480
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bool 'PAL 640x480 (Experimental)'
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config NTSC_YCBCR
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bool 'NTSC 720x480 YCbCR input'
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config PAL_YCBCR
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bool 'PAL 720x576 YCbCR input'
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endchoice
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choice
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prompt "Size of ADV7393 frame buffer memory Single/Double Size"
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depends on (FB_BFIN_7393)
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default ADV7393_1XMEM
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config ADV7393_1XMEM
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bool 'Single'
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config ADV7393_2XMEM
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bool 'Double'
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endchoice
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config FB_STI
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tristate "HP STI frame buffer device support"
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depends on FB && PARISC
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@ -136,11 +136,6 @@ obj-$(CONFIG_FB_VESA) += vesafb.o
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obj-$(CONFIG_FB_EFI) += efifb.o
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obj-$(CONFIG_FB_VGA16) += vga16fb.o
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obj-$(CONFIG_FB_OF) += offb.o
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obj-$(CONFIG_FB_BF537_LQ035) += bf537-lq035.o
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obj-$(CONFIG_FB_BF54X_LQ043) += bf54x-lq043fb.o
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obj-$(CONFIG_FB_BFIN_LQ035Q1) += bfin-lq035q1-fb.o
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obj-$(CONFIG_FB_BFIN_T350MCQB) += bfin-t350mcqb-fb.o
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obj-$(CONFIG_FB_BFIN_7393) += bfin_adv7393fb.o
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obj-$(CONFIG_FB_MX3) += mx3fb.o
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obj-$(CONFIG_FB_DA8XX) += da8xx-fb.o
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obj-$(CONFIG_FB_MXS) += mxsfb.o
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@ -1,891 +0,0 @@
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/*
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* Analog Devices Blackfin(BF537 STAMP) + SHARP TFT LCD.
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* http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:tft-lcd
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*
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* Copyright 2006-2010 Analog Devices Inc.
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* Licensed under the GPL-2.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/mm.h>
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#include <linux/delay.h>
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#include <linux/fb.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/gpio.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#include <linux/timer.h>
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#include <linux/device.h>
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#include <linux/backlight.h>
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#include <linux/lcd.h>
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#include <linux/i2c.h>
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#include <linux/spinlock.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <asm/blackfin.h>
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#include <asm/irq.h>
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#include <asm/dpmc.h>
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#include <asm/dma.h>
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#include <asm/portmux.h>
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#define NO_BL 1
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#define MAX_BRIGHENESS 95
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#define MIN_BRIGHENESS 5
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#define NBR_PALETTE 256
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static const unsigned short ppi_pins[] = {
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P_PPI0_CLK, P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
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P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
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P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
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P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, 0
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};
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static unsigned char *fb_buffer; /* RGB Buffer */
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static unsigned long *dma_desc_table;
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static int t_conf_done, lq035_open_cnt;
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static DEFINE_SPINLOCK(bfin_lq035_lock);
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static int landscape;
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module_param(landscape, int, 0);
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MODULE_PARM_DESC(landscape,
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"LANDSCAPE use 320x240 instead of Native 240x320 Resolution");
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static int bgr;
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module_param(bgr, int, 0);
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MODULE_PARM_DESC(bgr,
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"BGR use 16-bit BGR-565 instead of RGB-565");
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static int nocursor = 1;
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module_param(nocursor, int, 0644);
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MODULE_PARM_DESC(nocursor, "cursor enable/disable");
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static unsigned long current_brightness; /* backlight */
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/* AD5280 vcomm */
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static unsigned char vcomm_value = 150;
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static struct i2c_client *ad5280_client;
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static void set_vcomm(void)
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{
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int nr;
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if (!ad5280_client)
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return;
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nr = i2c_smbus_write_byte_data(ad5280_client, 0x00, vcomm_value);
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if (nr)
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pr_err("i2c_smbus_write_byte_data fail: %d\n", nr);
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}
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static int ad5280_probe(struct i2c_client *client,
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const struct i2c_device_id *id)
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{
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int ret;
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if (!i2c_check_functionality(client->adapter,
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I2C_FUNC_SMBUS_BYTE_DATA)) {
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dev_err(&client->dev, "SMBUS Byte Data not Supported\n");
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return -EIO;
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}
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ret = i2c_smbus_write_byte_data(client, 0x00, vcomm_value);
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if (ret) {
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dev_err(&client->dev, "write fail: %d\n", ret);
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return ret;
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}
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ad5280_client = client;
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return 0;
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}
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static int ad5280_remove(struct i2c_client *client)
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{
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ad5280_client = NULL;
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return 0;
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}
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static const struct i2c_device_id ad5280_id[] = {
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{"bf537-lq035-ad5280", 0},
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{}
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};
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MODULE_DEVICE_TABLE(i2c, ad5280_id);
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static struct i2c_driver ad5280_driver = {
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.driver = {
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.name = "bf537-lq035-ad5280",
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},
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.probe = ad5280_probe,
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.remove = ad5280_remove,
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.id_table = ad5280_id,
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};
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#ifdef CONFIG_PNAV10
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#define MOD GPIO_PH13
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#define bfin_write_TIMER_LP_CONFIG bfin_write_TIMER0_CONFIG
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#define bfin_write_TIMER_LP_WIDTH bfin_write_TIMER0_WIDTH
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#define bfin_write_TIMER_LP_PERIOD bfin_write_TIMER0_PERIOD
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#define bfin_read_TIMER_LP_COUNTER bfin_read_TIMER0_COUNTER
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#define TIMDIS_LP TIMDIS0
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#define TIMEN_LP TIMEN0
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#define bfin_write_TIMER_SPS_CONFIG bfin_write_TIMER1_CONFIG
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#define bfin_write_TIMER_SPS_WIDTH bfin_write_TIMER1_WIDTH
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#define bfin_write_TIMER_SPS_PERIOD bfin_write_TIMER1_PERIOD
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#define TIMDIS_SPS TIMDIS1
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#define TIMEN_SPS TIMEN1
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#define bfin_write_TIMER_SP_CONFIG bfin_write_TIMER5_CONFIG
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#define bfin_write_TIMER_SP_WIDTH bfin_write_TIMER5_WIDTH
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#define bfin_write_TIMER_SP_PERIOD bfin_write_TIMER5_PERIOD
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#define TIMDIS_SP TIMDIS5
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#define TIMEN_SP TIMEN5
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#define bfin_write_TIMER_PS_CLS_CONFIG bfin_write_TIMER2_CONFIG
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#define bfin_write_TIMER_PS_CLS_WIDTH bfin_write_TIMER2_WIDTH
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#define bfin_write_TIMER_PS_CLS_PERIOD bfin_write_TIMER2_PERIOD
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#define TIMDIS_PS_CLS TIMDIS2
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#define TIMEN_PS_CLS TIMEN2
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#define bfin_write_TIMER_REV_CONFIG bfin_write_TIMER3_CONFIG
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#define bfin_write_TIMER_REV_WIDTH bfin_write_TIMER3_WIDTH
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#define bfin_write_TIMER_REV_PERIOD bfin_write_TIMER3_PERIOD
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#define TIMDIS_REV TIMDIS3
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#define TIMEN_REV TIMEN3
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#define bfin_read_TIMER_REV_COUNTER bfin_read_TIMER3_COUNTER
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#define FREQ_PPI_CLK (5*1024*1024) /* PPI_CLK 5MHz */
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#define TIMERS {P_TMR0, P_TMR1, P_TMR2, P_TMR3, P_TMR5, 0}
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#else
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#define UD GPIO_PF13 /* Up / Down */
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#define MOD GPIO_PF10
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#define LBR GPIO_PF14 /* Left Right */
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#define bfin_write_TIMER_LP_CONFIG bfin_write_TIMER6_CONFIG
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#define bfin_write_TIMER_LP_WIDTH bfin_write_TIMER6_WIDTH
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#define bfin_write_TIMER_LP_PERIOD bfin_write_TIMER6_PERIOD
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#define bfin_read_TIMER_LP_COUNTER bfin_read_TIMER6_COUNTER
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#define TIMDIS_LP TIMDIS6
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#define TIMEN_LP TIMEN6
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#define bfin_write_TIMER_SPS_CONFIG bfin_write_TIMER1_CONFIG
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#define bfin_write_TIMER_SPS_WIDTH bfin_write_TIMER1_WIDTH
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#define bfin_write_TIMER_SPS_PERIOD bfin_write_TIMER1_PERIOD
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#define TIMDIS_SPS TIMDIS1
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#define TIMEN_SPS TIMEN1
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#define bfin_write_TIMER_SP_CONFIG bfin_write_TIMER0_CONFIG
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#define bfin_write_TIMER_SP_WIDTH bfin_write_TIMER0_WIDTH
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#define bfin_write_TIMER_SP_PERIOD bfin_write_TIMER0_PERIOD
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#define TIMDIS_SP TIMDIS0
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#define TIMEN_SP TIMEN0
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#define bfin_write_TIMER_PS_CLS_CONFIG bfin_write_TIMER7_CONFIG
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#define bfin_write_TIMER_PS_CLS_WIDTH bfin_write_TIMER7_WIDTH
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#define bfin_write_TIMER_PS_CLS_PERIOD bfin_write_TIMER7_PERIOD
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#define TIMDIS_PS_CLS TIMDIS7
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#define TIMEN_PS_CLS TIMEN7
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#define bfin_write_TIMER_REV_CONFIG bfin_write_TIMER5_CONFIG
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#define bfin_write_TIMER_REV_WIDTH bfin_write_TIMER5_WIDTH
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#define bfin_write_TIMER_REV_PERIOD bfin_write_TIMER5_PERIOD
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#define TIMDIS_REV TIMDIS5
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#define TIMEN_REV TIMEN5
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#define bfin_read_TIMER_REV_COUNTER bfin_read_TIMER5_COUNTER
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#define FREQ_PPI_CLK (6*1000*1000) /* PPI_CLK 6MHz */
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#define TIMERS {P_TMR0, P_TMR1, P_TMR5, P_TMR6, P_TMR7, 0}
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#endif
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#define LCD_X_RES 240 /* Horizontal Resolution */
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#define LCD_Y_RES 320 /* Vertical Resolution */
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#define LCD_BBP 16 /* Bit Per Pixel */
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/* the LCD and the DMA start counting differently;
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* since one starts at 0 and the other starts at 1,
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* we have a difference of 1 between START_LINES
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* and U_LINES.
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*/
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#define START_LINES 8 /* lines for field flyback or field blanking signal */
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#define U_LINES 9 /* number of undisplayed blanking lines */
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#define FRAMES_PER_SEC (60)
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#define DCLKS_PER_FRAME (FREQ_PPI_CLK/FRAMES_PER_SEC)
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#define DCLKS_PER_LINE (DCLKS_PER_FRAME/(LCD_Y_RES+U_LINES))
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#define PPI_CONFIG_VALUE (PORT_DIR|XFR_TYPE|DLEN_16|POLS)
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#define PPI_DELAY_VALUE (0)
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#define TIMER_CONFIG (PWM_OUT|PERIOD_CNT|TIN_SEL|CLK_SEL)
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#define ACTIVE_VIDEO_MEM_OFFSET (LCD_X_RES*START_LINES*(LCD_BBP/8))
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#define ACTIVE_VIDEO_MEM_SIZE (LCD_Y_RES*LCD_X_RES*(LCD_BBP/8))
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#define TOTAL_VIDEO_MEM_SIZE ((LCD_Y_RES+U_LINES)*LCD_X_RES*(LCD_BBP/8))
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#define TOTAL_DMA_DESC_SIZE (2 * sizeof(u32) * (LCD_Y_RES + U_LINES))
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static void start_timers(void) /* CHECK with HW */
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{
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unsigned long flags;
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local_irq_save(flags);
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bfin_write_TIMER_ENABLE(TIMEN_REV);
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SSYNC();
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while (bfin_read_TIMER_REV_COUNTER() <= 11)
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continue;
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bfin_write_TIMER_ENABLE(TIMEN_LP);
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SSYNC();
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while (bfin_read_TIMER_LP_COUNTER() < 3)
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continue;
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bfin_write_TIMER_ENABLE(TIMEN_SP|TIMEN_SPS|TIMEN_PS_CLS);
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SSYNC();
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t_conf_done = 1;
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local_irq_restore(flags);
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}
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static void config_timers(void)
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{
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/* Stop timers */
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bfin_write_TIMER_DISABLE(TIMDIS_SP|TIMDIS_SPS|TIMDIS_REV|
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TIMDIS_LP|TIMDIS_PS_CLS);
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SSYNC();
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/* LP, timer 6 */
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bfin_write_TIMER_LP_CONFIG(TIMER_CONFIG|PULSE_HI);
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bfin_write_TIMER_LP_WIDTH(1);
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bfin_write_TIMER_LP_PERIOD(DCLKS_PER_LINE);
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SSYNC();
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/* SPS, timer 1 */
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bfin_write_TIMER_SPS_CONFIG(TIMER_CONFIG|PULSE_HI);
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bfin_write_TIMER_SPS_WIDTH(DCLKS_PER_LINE*2);
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bfin_write_TIMER_SPS_PERIOD((DCLKS_PER_LINE * (LCD_Y_RES+U_LINES)));
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SSYNC();
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/* SP, timer 0 */
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bfin_write_TIMER_SP_CONFIG(TIMER_CONFIG|PULSE_HI);
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bfin_write_TIMER_SP_WIDTH(1);
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bfin_write_TIMER_SP_PERIOD(DCLKS_PER_LINE);
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SSYNC();
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/* PS & CLS, timer 7 */
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bfin_write_TIMER_PS_CLS_CONFIG(TIMER_CONFIG);
|
||||
bfin_write_TIMER_PS_CLS_WIDTH(LCD_X_RES + START_LINES);
|
||||
bfin_write_TIMER_PS_CLS_PERIOD(DCLKS_PER_LINE);
|
||||
|
||||
SSYNC();
|
||||
|
||||
#ifdef NO_BL
|
||||
/* REV, timer 5 */
|
||||
bfin_write_TIMER_REV_CONFIG(TIMER_CONFIG|PULSE_HI);
|
||||
|
||||
bfin_write_TIMER_REV_WIDTH(DCLKS_PER_LINE);
|
||||
bfin_write_TIMER_REV_PERIOD(DCLKS_PER_LINE*2);
|
||||
|
||||
SSYNC();
|
||||
#endif
|
||||
}
|
||||
|
||||
static void config_ppi(void)
|
||||
{
|
||||
bfin_write_PPI_DELAY(PPI_DELAY_VALUE);
|
||||
bfin_write_PPI_COUNT(LCD_X_RES-1);
|
||||
/* 0x10 -> PORT_CFG -> 2 or 3 frame syncs */
|
||||
bfin_write_PPI_CONTROL((PPI_CONFIG_VALUE|0x10) & (~POLS));
|
||||
}
|
||||
|
||||
static int config_dma(void)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
if (landscape) {
|
||||
|
||||
for (i = 0; i < U_LINES; ++i) {
|
||||
/* blanking lines point to first line of fb_buffer */
|
||||
dma_desc_table[2*i] = (unsigned long)&dma_desc_table[2*i+2];
|
||||
dma_desc_table[2*i+1] = (unsigned long)fb_buffer;
|
||||
}
|
||||
|
||||
for (i = U_LINES; i < U_LINES + LCD_Y_RES; ++i) {
|
||||
/* visible lines */
|
||||
dma_desc_table[2*i] = (unsigned long)&dma_desc_table[2*i+2];
|
||||
dma_desc_table[2*i+1] = (unsigned long)fb_buffer +
|
||||
(LCD_Y_RES+U_LINES-1-i)*2;
|
||||
}
|
||||
|
||||
/* last descriptor points to first */
|
||||
dma_desc_table[2*(LCD_Y_RES+U_LINES-1)] = (unsigned long)&dma_desc_table[0];
|
||||
|
||||
set_dma_x_count(CH_PPI, LCD_X_RES);
|
||||
set_dma_x_modify(CH_PPI, LCD_Y_RES * (LCD_BBP / 8));
|
||||
set_dma_y_count(CH_PPI, 0);
|
||||
set_dma_y_modify(CH_PPI, 0);
|
||||
set_dma_next_desc_addr(CH_PPI, (void *)dma_desc_table[0]);
|
||||
set_dma_config(CH_PPI, DMAFLOW_LARGE | NDSIZE_4 | WDSIZE_16);
|
||||
|
||||
} else {
|
||||
|
||||
set_dma_config(CH_PPI, set_bfin_dma_config(DIR_READ,
|
||||
DMA_FLOW_AUTO,
|
||||
INTR_DISABLE,
|
||||
DIMENSION_2D,
|
||||
DATA_SIZE_16,
|
||||
DMA_NOSYNC_KEEP_DMA_BUF));
|
||||
set_dma_x_count(CH_PPI, LCD_X_RES);
|
||||
set_dma_x_modify(CH_PPI, LCD_BBP / 8);
|
||||
set_dma_y_count(CH_PPI, LCD_Y_RES+U_LINES);
|
||||
set_dma_y_modify(CH_PPI, LCD_BBP / 8);
|
||||
set_dma_start_addr(CH_PPI, (unsigned long) fb_buffer);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int request_ports(void)
|
||||
{
|
||||
u16 tmr_req[] = TIMERS;
|
||||
|
||||
/*
|
||||
UD: PF13
|
||||
MOD: PF10
|
||||
LBR: PF14
|
||||
PPI_CLK: PF15
|
||||
*/
|
||||
|
||||
if (peripheral_request_list(ppi_pins, KBUILD_MODNAME)) {
|
||||
pr_err("requesting PPI peripheral failed\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
if (peripheral_request_list(tmr_req, KBUILD_MODNAME)) {
|
||||
peripheral_free_list(ppi_pins);
|
||||
pr_err("requesting timer peripheral failed\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
#if (defined(UD) && defined(LBR))
|
||||
if (gpio_request_one(UD, GPIOF_OUT_INIT_LOW, KBUILD_MODNAME)) {
|
||||
pr_err("requesting GPIO %d failed\n", UD);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
if (gpio_request_one(LBR, GPIOF_OUT_INIT_HIGH, KBUILD_MODNAME)) {
|
||||
pr_err("requesting GPIO %d failed\n", LBR);
|
||||
gpio_free(UD);
|
||||
return -EBUSY;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (gpio_request_one(MOD, GPIOF_OUT_INIT_HIGH, KBUILD_MODNAME)) {
|
||||
pr_err("requesting GPIO %d failed\n", MOD);
|
||||
#if (defined(UD) && defined(LBR))
|
||||
gpio_free(LBR);
|
||||
gpio_free(UD);
|
||||
#endif
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
SSYNC();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void free_ports(void)
|
||||
{
|
||||
u16 tmr_req[] = TIMERS;
|
||||
|
||||
peripheral_free_list(ppi_pins);
|
||||
peripheral_free_list(tmr_req);
|
||||
|
||||
#if defined(UD) && defined(LBR)
|
||||
gpio_free(LBR);
|
||||
gpio_free(UD);
|
||||
#endif
|
||||
gpio_free(MOD);
|
||||
}
|
||||
|
||||
static struct fb_info bfin_lq035_fb;
|
||||
|
||||
static struct fb_var_screeninfo bfin_lq035_fb_defined = {
|
||||
.bits_per_pixel = LCD_BBP,
|
||||
.activate = FB_ACTIVATE_TEST,
|
||||
.xres = LCD_X_RES, /*default portrait mode RGB*/
|
||||
.yres = LCD_Y_RES,
|
||||
.xres_virtual = LCD_X_RES,
|
||||
.yres_virtual = LCD_Y_RES,
|
||||
.height = -1,
|
||||
.width = -1,
|
||||
.left_margin = 0,
|
||||
.right_margin = 0,
|
||||
.upper_margin = 0,
|
||||
.lower_margin = 0,
|
||||
.red = {11, 5, 0},
|
||||
.green = {5, 6, 0},
|
||||
.blue = {0, 5, 0},
|
||||
.transp = {0, 0, 0},
|
||||
};
|
||||
|
||||
static struct fb_fix_screeninfo bfin_lq035_fb_fix = {
|
||||
.id = KBUILD_MODNAME,
|
||||
.smem_len = ACTIVE_VIDEO_MEM_SIZE,
|
||||
.type = FB_TYPE_PACKED_PIXELS,
|
||||
.visual = FB_VISUAL_TRUECOLOR,
|
||||
.xpanstep = 0,
|
||||
.ypanstep = 0,
|
||||
.line_length = LCD_X_RES*(LCD_BBP/8),
|
||||
.accel = FB_ACCEL_NONE,
|
||||
};
|
||||
|
||||
|
||||
static int bfin_lq035_fb_open(struct fb_info *info, int user)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&bfin_lq035_lock, flags);
|
||||
lq035_open_cnt++;
|
||||
spin_unlock_irqrestore(&bfin_lq035_lock, flags);
|
||||
|
||||
if (lq035_open_cnt <= 1) {
|
||||
bfin_write_PPI_CONTROL(0);
|
||||
SSYNC();
|
||||
|
||||
set_vcomm();
|
||||
config_dma();
|
||||
config_ppi();
|
||||
|
||||
/* start dma */
|
||||
enable_dma(CH_PPI);
|
||||
SSYNC();
|
||||
bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
|
||||
SSYNC();
|
||||
|
||||
if (!t_conf_done) {
|
||||
config_timers();
|
||||
start_timers();
|
||||
}
|
||||
/* gpio_set_value(MOD,1); */
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_lq035_fb_release(struct fb_info *info, int user)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&bfin_lq035_lock, flags);
|
||||
lq035_open_cnt--;
|
||||
spin_unlock_irqrestore(&bfin_lq035_lock, flags);
|
||||
|
||||
|
||||
if (lq035_open_cnt <= 0) {
|
||||
|
||||
bfin_write_PPI_CONTROL(0);
|
||||
SSYNC();
|
||||
|
||||
disable_dma(CH_PPI);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int bfin_lq035_fb_check_var(struct fb_var_screeninfo *var,
|
||||
struct fb_info *info)
|
||||
{
|
||||
switch (var->bits_per_pixel) {
|
||||
case 16:/* DIRECTCOLOUR, 64k */
|
||||
var->red.offset = info->var.red.offset;
|
||||
var->green.offset = info->var.green.offset;
|
||||
var->blue.offset = info->var.blue.offset;
|
||||
var->red.length = info->var.red.length;
|
||||
var->green.length = info->var.green.length;
|
||||
var->blue.length = info->var.blue.length;
|
||||
var->transp.offset = 0;
|
||||
var->transp.length = 0;
|
||||
var->transp.msb_right = 0;
|
||||
var->red.msb_right = 0;
|
||||
var->green.msb_right = 0;
|
||||
var->blue.msb_right = 0;
|
||||
break;
|
||||
default:
|
||||
pr_debug("%s: depth not supported: %u BPP\n", __func__,
|
||||
var->bits_per_pixel);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (info->var.xres != var->xres ||
|
||||
info->var.yres != var->yres ||
|
||||
info->var.xres_virtual != var->xres_virtual ||
|
||||
info->var.yres_virtual != var->yres_virtual) {
|
||||
pr_debug("%s: Resolution not supported: X%u x Y%u\n",
|
||||
__func__, var->xres, var->yres);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Memory limit
|
||||
*/
|
||||
|
||||
if ((info->fix.line_length * var->yres_virtual) > info->fix.smem_len) {
|
||||
pr_debug("%s: Memory Limit requested yres_virtual = %u\n",
|
||||
__func__, var->yres_virtual);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_lq035_fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
|
||||
{
|
||||
if (nocursor)
|
||||
return 0;
|
||||
else
|
||||
return -EINVAL; /* just to force soft_cursor() call */
|
||||
}
|
||||
|
||||
static int bfin_lq035_fb_setcolreg(u_int regno, u_int red, u_int green,
|
||||
u_int blue, u_int transp,
|
||||
struct fb_info *info)
|
||||
{
|
||||
if (regno >= NBR_PALETTE)
|
||||
return -EINVAL;
|
||||
|
||||
if (info->var.grayscale)
|
||||
/* grayscale = 0.30*R + 0.59*G + 0.11*B */
|
||||
red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
|
||||
|
||||
if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
|
||||
|
||||
u32 value;
|
||||
/* Place color in the pseudopalette */
|
||||
if (regno > 16)
|
||||
return -EINVAL;
|
||||
|
||||
red >>= (16 - info->var.red.length);
|
||||
green >>= (16 - info->var.green.length);
|
||||
blue >>= (16 - info->var.blue.length);
|
||||
|
||||
value = (red << info->var.red.offset) |
|
||||
(green << info->var.green.offset)|
|
||||
(blue << info->var.blue.offset);
|
||||
value &= 0xFFFF;
|
||||
|
||||
((u32 *) (info->pseudo_palette))[regno] = value;
|
||||
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct fb_ops bfin_lq035_fb_ops = {
|
||||
.owner = THIS_MODULE,
|
||||
.fb_open = bfin_lq035_fb_open,
|
||||
.fb_release = bfin_lq035_fb_release,
|
||||
.fb_check_var = bfin_lq035_fb_check_var,
|
||||
.fb_fillrect = cfb_fillrect,
|
||||
.fb_copyarea = cfb_copyarea,
|
||||
.fb_imageblit = cfb_imageblit,
|
||||
.fb_cursor = bfin_lq035_fb_cursor,
|
||||
.fb_setcolreg = bfin_lq035_fb_setcolreg,
|
||||
};
|
||||
|
||||
static int bl_get_brightness(struct backlight_device *bd)
|
||||
{
|
||||
return current_brightness;
|
||||
}
|
||||
|
||||
static const struct backlight_ops bfin_lq035fb_bl_ops = {
|
||||
.get_brightness = bl_get_brightness,
|
||||
};
|
||||
|
||||
static struct backlight_device *bl_dev;
|
||||
|
||||
static int bfin_lcd_get_power(struct lcd_device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_lcd_set_power(struct lcd_device *dev, int power)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_lcd_get_contrast(struct lcd_device *dev)
|
||||
{
|
||||
return (int)vcomm_value;
|
||||
}
|
||||
|
||||
static int bfin_lcd_set_contrast(struct lcd_device *dev, int contrast)
|
||||
{
|
||||
if (contrast > 255)
|
||||
contrast = 255;
|
||||
if (contrast < 0)
|
||||
contrast = 0;
|
||||
|
||||
vcomm_value = (unsigned char)contrast;
|
||||
set_vcomm();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_lcd_check_fb(struct lcd_device *lcd, struct fb_info *fi)
|
||||
{
|
||||
if (!fi || (fi == &bfin_lq035_fb))
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct lcd_ops bfin_lcd_ops = {
|
||||
.get_power = bfin_lcd_get_power,
|
||||
.set_power = bfin_lcd_set_power,
|
||||
.get_contrast = bfin_lcd_get_contrast,
|
||||
.set_contrast = bfin_lcd_set_contrast,
|
||||
.check_fb = bfin_lcd_check_fb,
|
||||
};
|
||||
|
||||
static struct lcd_device *lcd_dev;
|
||||
|
||||
static int bfin_lq035_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct backlight_properties props;
|
||||
dma_addr_t dma_handle;
|
||||
int ret;
|
||||
|
||||
if (request_dma(CH_PPI, KBUILD_MODNAME)) {
|
||||
pr_err("couldn't request PPI DMA\n");
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
if (request_ports()) {
|
||||
pr_err("couldn't request gpio port\n");
|
||||
ret = -EFAULT;
|
||||
goto out_ports;
|
||||
}
|
||||
|
||||
fb_buffer = dma_alloc_coherent(NULL, TOTAL_VIDEO_MEM_SIZE,
|
||||
&dma_handle, GFP_KERNEL);
|
||||
if (fb_buffer == NULL) {
|
||||
pr_err("couldn't allocate dma buffer\n");
|
||||
ret = -ENOMEM;
|
||||
goto out_dma_coherent;
|
||||
}
|
||||
|
||||
if (L1_DATA_A_LENGTH)
|
||||
dma_desc_table = l1_data_sram_zalloc(TOTAL_DMA_DESC_SIZE);
|
||||
else
|
||||
dma_desc_table = dma_alloc_coherent(NULL, TOTAL_DMA_DESC_SIZE,
|
||||
&dma_handle, 0);
|
||||
|
||||
if (dma_desc_table == NULL) {
|
||||
pr_err("couldn't allocate dma descriptor\n");
|
||||
ret = -ENOMEM;
|
||||
goto out_table;
|
||||
}
|
||||
|
||||
bfin_lq035_fb.screen_base = (void *)fb_buffer;
|
||||
bfin_lq035_fb_fix.smem_start = (int)fb_buffer;
|
||||
if (landscape) {
|
||||
bfin_lq035_fb_defined.xres = LCD_Y_RES;
|
||||
bfin_lq035_fb_defined.yres = LCD_X_RES;
|
||||
bfin_lq035_fb_defined.xres_virtual = LCD_Y_RES;
|
||||
bfin_lq035_fb_defined.yres_virtual = LCD_X_RES;
|
||||
|
||||
bfin_lq035_fb_fix.line_length = LCD_Y_RES*(LCD_BBP/8);
|
||||
} else {
|
||||
bfin_lq035_fb.screen_base += ACTIVE_VIDEO_MEM_OFFSET;
|
||||
bfin_lq035_fb_fix.smem_start += ACTIVE_VIDEO_MEM_OFFSET;
|
||||
}
|
||||
|
||||
bfin_lq035_fb_defined.green.msb_right = 0;
|
||||
bfin_lq035_fb_defined.red.msb_right = 0;
|
||||
bfin_lq035_fb_defined.blue.msb_right = 0;
|
||||
bfin_lq035_fb_defined.green.offset = 5;
|
||||
bfin_lq035_fb_defined.green.length = 6;
|
||||
bfin_lq035_fb_defined.red.length = 5;
|
||||
bfin_lq035_fb_defined.blue.length = 5;
|
||||
|
||||
if (bgr) {
|
||||
bfin_lq035_fb_defined.red.offset = 0;
|
||||
bfin_lq035_fb_defined.blue.offset = 11;
|
||||
} else {
|
||||
bfin_lq035_fb_defined.red.offset = 11;
|
||||
bfin_lq035_fb_defined.blue.offset = 0;
|
||||
}
|
||||
|
||||
bfin_lq035_fb.fbops = &bfin_lq035_fb_ops;
|
||||
bfin_lq035_fb.var = bfin_lq035_fb_defined;
|
||||
|
||||
bfin_lq035_fb.fix = bfin_lq035_fb_fix;
|
||||
bfin_lq035_fb.flags = FBINFO_DEFAULT;
|
||||
|
||||
|
||||
bfin_lq035_fb.pseudo_palette = devm_kzalloc(&pdev->dev,
|
||||
sizeof(u32) * 16,
|
||||
GFP_KERNEL);
|
||||
if (bfin_lq035_fb.pseudo_palette == NULL) {
|
||||
pr_err("failed to allocate pseudo_palette\n");
|
||||
ret = -ENOMEM;
|
||||
goto out_table;
|
||||
}
|
||||
|
||||
if (fb_alloc_cmap(&bfin_lq035_fb.cmap, NBR_PALETTE, 0) < 0) {
|
||||
pr_err("failed to allocate colormap (%d entries)\n",
|
||||
NBR_PALETTE);
|
||||
ret = -EFAULT;
|
||||
goto out_table;
|
||||
}
|
||||
|
||||
if (register_framebuffer(&bfin_lq035_fb) < 0) {
|
||||
pr_err("unable to register framebuffer\n");
|
||||
ret = -EINVAL;
|
||||
goto out_reg;
|
||||
}
|
||||
|
||||
i2c_add_driver(&ad5280_driver);
|
||||
|
||||
memset(&props, 0, sizeof(props));
|
||||
props.type = BACKLIGHT_RAW;
|
||||
props.max_brightness = MAX_BRIGHENESS;
|
||||
bl_dev = backlight_device_register("bf537-bl", NULL, NULL,
|
||||
&bfin_lq035fb_bl_ops, &props);
|
||||
|
||||
lcd_dev = lcd_device_register(KBUILD_MODNAME, &pdev->dev, NULL,
|
||||
&bfin_lcd_ops);
|
||||
if (IS_ERR(lcd_dev)) {
|
||||
pr_err("unable to register lcd\n");
|
||||
ret = PTR_ERR(lcd_dev);
|
||||
goto out_lcd;
|
||||
}
|
||||
lcd_dev->props.max_contrast = 255,
|
||||
|
||||
pr_info("initialized");
|
||||
|
||||
return 0;
|
||||
out_lcd:
|
||||
unregister_framebuffer(&bfin_lq035_fb);
|
||||
out_reg:
|
||||
fb_dealloc_cmap(&bfin_lq035_fb.cmap);
|
||||
out_table:
|
||||
dma_free_coherent(NULL, TOTAL_VIDEO_MEM_SIZE, fb_buffer, 0);
|
||||
fb_buffer = NULL;
|
||||
out_dma_coherent:
|
||||
free_ports();
|
||||
out_ports:
|
||||
free_dma(CH_PPI);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int bfin_lq035_remove(struct platform_device *pdev)
|
||||
{
|
||||
if (fb_buffer != NULL)
|
||||
dma_free_coherent(NULL, TOTAL_VIDEO_MEM_SIZE, fb_buffer, 0);
|
||||
|
||||
if (L1_DATA_A_LENGTH)
|
||||
l1_data_sram_free(dma_desc_table);
|
||||
else
|
||||
dma_free_coherent(NULL, TOTAL_DMA_DESC_SIZE, NULL, 0);
|
||||
|
||||
bfin_write_TIMER_DISABLE(TIMEN_SP|TIMEN_SPS|TIMEN_PS_CLS|
|
||||
TIMEN_LP|TIMEN_REV);
|
||||
t_conf_done = 0;
|
||||
|
||||
free_dma(CH_PPI);
|
||||
|
||||
|
||||
fb_dealloc_cmap(&bfin_lq035_fb.cmap);
|
||||
|
||||
|
||||
lcd_device_unregister(lcd_dev);
|
||||
backlight_device_unregister(bl_dev);
|
||||
|
||||
unregister_framebuffer(&bfin_lq035_fb);
|
||||
i2c_del_driver(&ad5280_driver);
|
||||
|
||||
free_ports();
|
||||
|
||||
pr_info("unregistered LCD driver\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int bfin_lq035_suspend(struct platform_device *pdev, pm_message_t state)
|
||||
{
|
||||
if (lq035_open_cnt > 0) {
|
||||
bfin_write_PPI_CONTROL(0);
|
||||
SSYNC();
|
||||
disable_dma(CH_PPI);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_lq035_resume(struct platform_device *pdev)
|
||||
{
|
||||
if (lq035_open_cnt > 0) {
|
||||
bfin_write_PPI_CONTROL(0);
|
||||
SSYNC();
|
||||
|
||||
config_dma();
|
||||
config_ppi();
|
||||
|
||||
enable_dma(CH_PPI);
|
||||
bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
|
||||
SSYNC();
|
||||
|
||||
config_timers();
|
||||
start_timers();
|
||||
} else {
|
||||
t_conf_done = 0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
# define bfin_lq035_suspend NULL
|
||||
# define bfin_lq035_resume NULL
|
||||
#endif
|
||||
|
||||
static struct platform_driver bfin_lq035_driver = {
|
||||
.probe = bfin_lq035_probe,
|
||||
.remove = bfin_lq035_remove,
|
||||
.suspend = bfin_lq035_suspend,
|
||||
.resume = bfin_lq035_resume,
|
||||
.driver = {
|
||||
.name = KBUILD_MODNAME,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init bfin_lq035_driver_init(void)
|
||||
{
|
||||
request_module("i2c-bfin-twi");
|
||||
return platform_driver_register(&bfin_lq035_driver);
|
||||
}
|
||||
module_init(bfin_lq035_driver_init);
|
||||
|
||||
static void __exit bfin_lq035_driver_cleanup(void)
|
||||
{
|
||||
platform_driver_unregister(&bfin_lq035_driver);
|
||||
}
|
||||
module_exit(bfin_lq035_driver_cleanup);
|
||||
|
||||
MODULE_DESCRIPTION("SHARP LQ035Q7DB03 TFT LCD Driver");
|
||||
MODULE_LICENSE("GPL");
|
|
@ -1,764 +0,0 @@
|
|||
/*
|
||||
* File: drivers/video/bf54x-lq043.c
|
||||
* Based on:
|
||||
* Author: Michael Hennerich <hennerich@blackfin.uclinux.org>
|
||||
*
|
||||
* Created:
|
||||
* Description: ADSP-BF54x Framebuffer driver
|
||||
*
|
||||
*
|
||||
* Modified:
|
||||
* Copyright 2007-2008 Analog Devices Inc.
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see the file COPYING, or write
|
||||
* to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/tty.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/fb.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/backlight.h>
|
||||
#include <linux/lcd.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
#include <asm/blackfin.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/dpmc.h>
|
||||
#include <asm/dma-mapping.h>
|
||||
#include <asm/dma.h>
|
||||
#include <asm/portmux.h>
|
||||
|
||||
#include <mach/bf54x-lq043.h>
|
||||
|
||||
#define NO_BL_SUPPORT
|
||||
|
||||
#define DRIVER_NAME "bf54x-lq043"
|
||||
static char driver_name[] = DRIVER_NAME;
|
||||
|
||||
#define BFIN_LCD_NBR_PALETTE_ENTRIES 256
|
||||
|
||||
#define EPPI0_18 {P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, \
|
||||
P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, \
|
||||
P_PPI0_D11, P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, P_PPI0_D16, P_PPI0_D17, 0}
|
||||
|
||||
#define EPPI0_24 {P_PPI0_D18, P_PPI0_D19, P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23, 0}
|
||||
|
||||
struct bfin_bf54xfb_info {
|
||||
struct fb_info *fb;
|
||||
struct device *dev;
|
||||
|
||||
struct bfin_bf54xfb_mach_info *mach_info;
|
||||
|
||||
unsigned char *fb_buffer; /* RGB Buffer */
|
||||
|
||||
dma_addr_t dma_handle;
|
||||
int lq043_open_cnt;
|
||||
int irq;
|
||||
spinlock_t lock; /* lock */
|
||||
};
|
||||
|
||||
static int nocursor;
|
||||
module_param(nocursor, int, 0644);
|
||||
MODULE_PARM_DESC(nocursor, "cursor enable/disable");
|
||||
|
||||
static int outp_rgb666;
|
||||
module_param(outp_rgb666, int, 0);
|
||||
MODULE_PARM_DESC(outp_rgb666, "Output 18-bit RGB666");
|
||||
|
||||
#define LCD_X_RES 480 /*Horizontal Resolution */
|
||||
#define LCD_Y_RES 272 /* Vertical Resolution */
|
||||
|
||||
#define LCD_BPP 24 /* Bit Per Pixel */
|
||||
#define DMA_BUS_SIZE 32
|
||||
|
||||
/* -- Horizontal synchronizing --
|
||||
*
|
||||
* Timing characteristics taken from the SHARP LQ043T1DG01 datasheet
|
||||
* (LCY-W-06602A Page 9 of 22)
|
||||
*
|
||||
* Clock Frequency 1/Tc Min 7.83 Typ 9.00 Max 9.26 MHz
|
||||
*
|
||||
* Period TH - 525 - Clock
|
||||
* Pulse width THp - 41 - Clock
|
||||
* Horizontal period THd - 480 - Clock
|
||||
* Back porch THb - 2 - Clock
|
||||
* Front porch THf - 2 - Clock
|
||||
*
|
||||
* -- Vertical synchronizing --
|
||||
* Period TV - 286 - Line
|
||||
* Pulse width TVp - 10 - Line
|
||||
* Vertical period TVd - 272 - Line
|
||||
* Back porch TVb - 2 - Line
|
||||
* Front porch TVf - 2 - Line
|
||||
*/
|
||||
|
||||
#define LCD_CLK (8*1000*1000) /* 8MHz */
|
||||
|
||||
/* # active data to transfer after Horizontal Delay clock */
|
||||
#define EPPI_HCOUNT LCD_X_RES
|
||||
|
||||
/* # active lines to transfer after Vertical Delay clock */
|
||||
#define EPPI_VCOUNT LCD_Y_RES
|
||||
|
||||
/* Samples per Line = 480 (active data) + 45 (padding) */
|
||||
#define EPPI_LINE 525
|
||||
|
||||
/* Lines per Frame = 272 (active data) + 14 (padding) */
|
||||
#define EPPI_FRAME 286
|
||||
|
||||
/* FS1 (Hsync) Width (Typical)*/
|
||||
#define EPPI_FS1W_HBL 41
|
||||
|
||||
/* FS1 (Hsync) Period (Typical) */
|
||||
#define EPPI_FS1P_AVPL EPPI_LINE
|
||||
|
||||
/* Horizontal Delay clock after assertion of Hsync (Typical) */
|
||||
#define EPPI_HDELAY 43
|
||||
|
||||
/* FS2 (Vsync) Width = FS1 (Hsync) Period * 10 */
|
||||
#define EPPI_FS2W_LVB (EPPI_LINE * 10)
|
||||
|
||||
/* FS2 (Vsync) Period = FS1 (Hsync) Period * Lines per Frame */
|
||||
#define EPPI_FS2P_LAVF (EPPI_LINE * EPPI_FRAME)
|
||||
|
||||
/* Vertical Delay after assertion of Vsync (2 Lines) */
|
||||
#define EPPI_VDELAY 12
|
||||
|
||||
#define EPPI_CLIP 0xFF00FF00
|
||||
|
||||
/* EPPI Control register configuration value for RGB out
|
||||
* - EPPI as Output
|
||||
* GP 2 frame sync mode,
|
||||
* Internal Clock generation disabled, Internal FS generation enabled,
|
||||
* Receives samples on EPPI_CLK raising edge, Transmits samples on EPPI_CLK falling edge,
|
||||
* FS1 & FS2 are active high,
|
||||
* DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
|
||||
* DMA Unpacking disabled when RGB Formating is enabled, otherwise DMA unpacking enabled
|
||||
* Swapping Enabled,
|
||||
* One (DMA) Channel Mode,
|
||||
* RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
|
||||
* Regular watermark - when FIFO is 100% full,
|
||||
* Urgent watermark - when FIFO is 75% full
|
||||
*/
|
||||
|
||||
#define EPPI_CONTROL (0x20136E2E | SWAPEN)
|
||||
|
||||
static inline u16 get_eppi_clkdiv(u32 target_ppi_clk)
|
||||
{
|
||||
u32 sclk = get_sclk();
|
||||
|
||||
/* EPPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV[15:0] + 1)) */
|
||||
|
||||
return (((sclk / target_ppi_clk) / 2) - 1);
|
||||
}
|
||||
|
||||
static void config_ppi(struct bfin_bf54xfb_info *fbi)
|
||||
{
|
||||
|
||||
u16 eppi_clkdiv = get_eppi_clkdiv(LCD_CLK);
|
||||
|
||||
bfin_write_EPPI0_FS1W_HBL(EPPI_FS1W_HBL);
|
||||
bfin_write_EPPI0_FS1P_AVPL(EPPI_FS1P_AVPL);
|
||||
bfin_write_EPPI0_FS2W_LVB(EPPI_FS2W_LVB);
|
||||
bfin_write_EPPI0_FS2P_LAVF(EPPI_FS2P_LAVF);
|
||||
bfin_write_EPPI0_CLIP(EPPI_CLIP);
|
||||
|
||||
bfin_write_EPPI0_FRAME(EPPI_FRAME);
|
||||
bfin_write_EPPI0_LINE(EPPI_LINE);
|
||||
|
||||
bfin_write_EPPI0_HCOUNT(EPPI_HCOUNT);
|
||||
bfin_write_EPPI0_HDELAY(EPPI_HDELAY);
|
||||
bfin_write_EPPI0_VCOUNT(EPPI_VCOUNT);
|
||||
bfin_write_EPPI0_VDELAY(EPPI_VDELAY);
|
||||
|
||||
bfin_write_EPPI0_CLKDIV(eppi_clkdiv);
|
||||
|
||||
/*
|
||||
* DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
|
||||
* RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
|
||||
*/
|
||||
if (outp_rgb666)
|
||||
bfin_write_EPPI0_CONTROL((EPPI_CONTROL & ~DLENGTH) | DLEN_18 |
|
||||
RGB_FMT_EN);
|
||||
else
|
||||
bfin_write_EPPI0_CONTROL(((EPPI_CONTROL & ~DLENGTH) | DLEN_24) &
|
||||
~RGB_FMT_EN);
|
||||
|
||||
|
||||
}
|
||||
|
||||
static int config_dma(struct bfin_bf54xfb_info *fbi)
|
||||
{
|
||||
|
||||
set_dma_config(CH_EPPI0,
|
||||
set_bfin_dma_config(DIR_READ, DMA_FLOW_AUTO,
|
||||
INTR_DISABLE, DIMENSION_2D,
|
||||
DATA_SIZE_32,
|
||||
DMA_NOSYNC_KEEP_DMA_BUF));
|
||||
set_dma_x_count(CH_EPPI0, (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE);
|
||||
set_dma_x_modify(CH_EPPI0, DMA_BUS_SIZE / 8);
|
||||
set_dma_y_count(CH_EPPI0, LCD_Y_RES);
|
||||
set_dma_y_modify(CH_EPPI0, DMA_BUS_SIZE / 8);
|
||||
set_dma_start_addr(CH_EPPI0, (unsigned long)fbi->fb_buffer);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int request_ports(struct bfin_bf54xfb_info *fbi)
|
||||
{
|
||||
|
||||
u16 eppi_req_18[] = EPPI0_18;
|
||||
u16 disp = fbi->mach_info->disp;
|
||||
|
||||
if (gpio_request_one(disp, GPIOF_OUT_INIT_HIGH, DRIVER_NAME)) {
|
||||
printk(KERN_ERR "Requesting GPIO %d failed\n", disp);
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
if (peripheral_request_list(eppi_req_18, DRIVER_NAME)) {
|
||||
printk(KERN_ERR "Requesting Peripherals failed\n");
|
||||
gpio_free(disp);
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
if (!outp_rgb666) {
|
||||
|
||||
u16 eppi_req_24[] = EPPI0_24;
|
||||
|
||||
if (peripheral_request_list(eppi_req_24, DRIVER_NAME)) {
|
||||
printk(KERN_ERR "Requesting Peripherals failed\n");
|
||||
peripheral_free_list(eppi_req_18);
|
||||
gpio_free(disp);
|
||||
return -EFAULT;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void free_ports(struct bfin_bf54xfb_info *fbi)
|
||||
{
|
||||
|
||||
u16 eppi_req_18[] = EPPI0_18;
|
||||
|
||||
gpio_free(fbi->mach_info->disp);
|
||||
|
||||
peripheral_free_list(eppi_req_18);
|
||||
|
||||
if (!outp_rgb666) {
|
||||
u16 eppi_req_24[] = EPPI0_24;
|
||||
peripheral_free_list(eppi_req_24);
|
||||
}
|
||||
}
|
||||
|
||||
static int bfin_bf54x_fb_open(struct fb_info *info, int user)
|
||||
{
|
||||
struct bfin_bf54xfb_info *fbi = info->par;
|
||||
|
||||
spin_lock(&fbi->lock);
|
||||
fbi->lq043_open_cnt++;
|
||||
|
||||
if (fbi->lq043_open_cnt <= 1) {
|
||||
|
||||
bfin_write_EPPI0_CONTROL(0);
|
||||
SSYNC();
|
||||
|
||||
config_dma(fbi);
|
||||
config_ppi(fbi);
|
||||
|
||||
/* start dma */
|
||||
enable_dma(CH_EPPI0);
|
||||
bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN);
|
||||
}
|
||||
|
||||
spin_unlock(&fbi->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_bf54x_fb_release(struct fb_info *info, int user)
|
||||
{
|
||||
struct bfin_bf54xfb_info *fbi = info->par;
|
||||
|
||||
spin_lock(&fbi->lock);
|
||||
|
||||
fbi->lq043_open_cnt--;
|
||||
|
||||
if (fbi->lq043_open_cnt <= 0) {
|
||||
|
||||
bfin_write_EPPI0_CONTROL(0);
|
||||
SSYNC();
|
||||
disable_dma(CH_EPPI0);
|
||||
}
|
||||
|
||||
spin_unlock(&fbi->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_bf54x_fb_check_var(struct fb_var_screeninfo *var,
|
||||
struct fb_info *info)
|
||||
{
|
||||
|
||||
switch (var->bits_per_pixel) {
|
||||
case 24:/* TRUECOLOUR, 16m */
|
||||
var->red.offset = 16;
|
||||
var->green.offset = 8;
|
||||
var->blue.offset = 0;
|
||||
var->red.length = var->green.length = var->blue.length = 8;
|
||||
var->transp.offset = 0;
|
||||
var->transp.length = 0;
|
||||
var->transp.msb_right = 0;
|
||||
var->red.msb_right = 0;
|
||||
var->green.msb_right = 0;
|
||||
var->blue.msb_right = 0;
|
||||
break;
|
||||
default:
|
||||
pr_debug("%s: depth not supported: %u BPP\n", __func__,
|
||||
var->bits_per_pixel);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (info->var.xres != var->xres || info->var.yres != var->yres ||
|
||||
info->var.xres_virtual != var->xres_virtual ||
|
||||
info->var.yres_virtual != var->yres_virtual) {
|
||||
pr_debug("%s: Resolution not supported: X%u x Y%u \n",
|
||||
__func__, var->xres, var->yres);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Memory limit
|
||||
*/
|
||||
|
||||
if ((info->fix.line_length * var->yres_virtual) > info->fix.smem_len) {
|
||||
pr_debug("%s: Memory Limit requested yres_virtual = %u\n",
|
||||
__func__, var->yres_virtual);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int bfin_bf54x_fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
|
||||
{
|
||||
if (nocursor)
|
||||
return 0;
|
||||
else
|
||||
return -EINVAL; /* just to force soft_cursor() call */
|
||||
}
|
||||
|
||||
static int bfin_bf54x_fb_setcolreg(u_int regno, u_int red, u_int green,
|
||||
u_int blue, u_int transp,
|
||||
struct fb_info *info)
|
||||
{
|
||||
if (regno >= BFIN_LCD_NBR_PALETTE_ENTRIES)
|
||||
return -EINVAL;
|
||||
|
||||
if (info->var.grayscale) {
|
||||
/* grayscale = 0.30*R + 0.59*G + 0.11*B */
|
||||
red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
|
||||
}
|
||||
|
||||
if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
|
||||
|
||||
u32 value;
|
||||
/* Place color in the pseudopalette */
|
||||
if (regno > 16)
|
||||
return -EINVAL;
|
||||
|
||||
red >>= (16 - info->var.red.length);
|
||||
green >>= (16 - info->var.green.length);
|
||||
blue >>= (16 - info->var.blue.length);
|
||||
|
||||
value = (red << info->var.red.offset) |
|
||||
(green << info->var.green.offset) |
|
||||
(blue << info->var.blue.offset);
|
||||
value &= 0xFFFFFF;
|
||||
|
||||
((u32 *) (info->pseudo_palette))[regno] = value;
|
||||
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct fb_ops bfin_bf54x_fb_ops = {
|
||||
.owner = THIS_MODULE,
|
||||
.fb_open = bfin_bf54x_fb_open,
|
||||
.fb_release = bfin_bf54x_fb_release,
|
||||
.fb_check_var = bfin_bf54x_fb_check_var,
|
||||
.fb_fillrect = cfb_fillrect,
|
||||
.fb_copyarea = cfb_copyarea,
|
||||
.fb_imageblit = cfb_imageblit,
|
||||
.fb_cursor = bfin_bf54x_fb_cursor,
|
||||
.fb_setcolreg = bfin_bf54x_fb_setcolreg,
|
||||
};
|
||||
|
||||
#ifndef NO_BL_SUPPORT
|
||||
static int bl_get_brightness(struct backlight_device *bd)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct backlight_ops bfin_lq043fb_bl_ops = {
|
||||
.get_brightness = bl_get_brightness,
|
||||
};
|
||||
|
||||
static struct backlight_device *bl_dev;
|
||||
|
||||
static int bfin_lcd_get_power(struct lcd_device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_lcd_set_power(struct lcd_device *dev, int power)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_lcd_get_contrast(struct lcd_device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_lcd_set_contrast(struct lcd_device *dev, int contrast)
|
||||
{
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_lcd_check_fb(struct lcd_device *dev, struct fb_info *fi)
|
||||
{
|
||||
if (!fi || (fi == &bfin_bf54x_fb))
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct lcd_ops bfin_lcd_ops = {
|
||||
.get_power = bfin_lcd_get_power,
|
||||
.set_power = bfin_lcd_set_power,
|
||||
.get_contrast = bfin_lcd_get_contrast,
|
||||
.set_contrast = bfin_lcd_set_contrast,
|
||||
.check_fb = bfin_lcd_check_fb,
|
||||
};
|
||||
|
||||
static struct lcd_device *lcd_dev;
|
||||
#endif
|
||||
|
||||
static irqreturn_t bfin_bf54x_irq_error(int irq, void *dev_id)
|
||||
{
|
||||
/*struct bfin_bf54xfb_info *info = dev_id;*/
|
||||
|
||||
u16 status = bfin_read_EPPI0_STATUS();
|
||||
|
||||
bfin_write_EPPI0_STATUS(0xFFFF);
|
||||
|
||||
if (status) {
|
||||
bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN);
|
||||
disable_dma(CH_EPPI0);
|
||||
|
||||
/* start dma */
|
||||
enable_dma(CH_EPPI0);
|
||||
bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN);
|
||||
bfin_write_EPPI0_STATUS(0xFFFF);
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int bfin_bf54x_probe(struct platform_device *pdev)
|
||||
{
|
||||
#ifndef NO_BL_SUPPORT
|
||||
struct backlight_properties props;
|
||||
#endif
|
||||
struct bfin_bf54xfb_info *info;
|
||||
struct fb_info *fbinfo;
|
||||
int ret;
|
||||
|
||||
printk(KERN_INFO DRIVER_NAME ": FrameBuffer initializing...\n");
|
||||
|
||||
if (request_dma(CH_EPPI0, "CH_EPPI0") < 0) {
|
||||
printk(KERN_ERR DRIVER_NAME
|
||||
": couldn't request CH_EPPI0 DMA\n");
|
||||
ret = -EFAULT;
|
||||
goto out1;
|
||||
}
|
||||
|
||||
fbinfo =
|
||||
framebuffer_alloc(sizeof(struct bfin_bf54xfb_info), &pdev->dev);
|
||||
if (!fbinfo) {
|
||||
ret = -ENOMEM;
|
||||
goto out2;
|
||||
}
|
||||
|
||||
info = fbinfo->par;
|
||||
info->fb = fbinfo;
|
||||
info->dev = &pdev->dev;
|
||||
spin_lock_init(&info->lock);
|
||||
|
||||
platform_set_drvdata(pdev, fbinfo);
|
||||
|
||||
strcpy(fbinfo->fix.id, driver_name);
|
||||
|
||||
info->mach_info = pdev->dev.platform_data;
|
||||
|
||||
if (info->mach_info == NULL) {
|
||||
dev_err(&pdev->dev,
|
||||
"no platform data for lcd, cannot attach\n");
|
||||
ret = -EINVAL;
|
||||
goto out3;
|
||||
}
|
||||
|
||||
fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
|
||||
fbinfo->fix.type_aux = 0;
|
||||
fbinfo->fix.xpanstep = 0;
|
||||
fbinfo->fix.ypanstep = 0;
|
||||
fbinfo->fix.ywrapstep = 0;
|
||||
fbinfo->fix.accel = FB_ACCEL_NONE;
|
||||
fbinfo->fix.visual = FB_VISUAL_TRUECOLOR;
|
||||
|
||||
fbinfo->var.nonstd = 0;
|
||||
fbinfo->var.activate = FB_ACTIVATE_NOW;
|
||||
fbinfo->var.height = info->mach_info->height;
|
||||
fbinfo->var.width = info->mach_info->width;
|
||||
fbinfo->var.accel_flags = 0;
|
||||
fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
|
||||
|
||||
fbinfo->fbops = &bfin_bf54x_fb_ops;
|
||||
fbinfo->flags = FBINFO_FLAG_DEFAULT;
|
||||
|
||||
fbinfo->var.xres = info->mach_info->xres.defval;
|
||||
fbinfo->var.xres_virtual = info->mach_info->xres.defval;
|
||||
fbinfo->var.yres = info->mach_info->yres.defval;
|
||||
fbinfo->var.yres_virtual = info->mach_info->yres.defval;
|
||||
fbinfo->var.bits_per_pixel = info->mach_info->bpp.defval;
|
||||
|
||||
fbinfo->var.upper_margin = 0;
|
||||
fbinfo->var.lower_margin = 0;
|
||||
fbinfo->var.vsync_len = 0;
|
||||
|
||||
fbinfo->var.left_margin = 0;
|
||||
fbinfo->var.right_margin = 0;
|
||||
fbinfo->var.hsync_len = 0;
|
||||
|
||||
fbinfo->var.red.offset = 16;
|
||||
fbinfo->var.green.offset = 8;
|
||||
fbinfo->var.blue.offset = 0;
|
||||
fbinfo->var.transp.offset = 0;
|
||||
fbinfo->var.red.length = 8;
|
||||
fbinfo->var.green.length = 8;
|
||||
fbinfo->var.blue.length = 8;
|
||||
fbinfo->var.transp.length = 0;
|
||||
fbinfo->fix.smem_len = info->mach_info->xres.max *
|
||||
info->mach_info->yres.max * info->mach_info->bpp.max / 8;
|
||||
|
||||
fbinfo->fix.line_length = fbinfo->var.xres_virtual *
|
||||
fbinfo->var.bits_per_pixel / 8;
|
||||
|
||||
info->fb_buffer =
|
||||
dma_alloc_coherent(NULL, fbinfo->fix.smem_len, &info->dma_handle,
|
||||
GFP_KERNEL);
|
||||
|
||||
if (NULL == info->fb_buffer) {
|
||||
printk(KERN_ERR DRIVER_NAME
|
||||
": couldn't allocate dma buffer.\n");
|
||||
ret = -ENOMEM;
|
||||
goto out3;
|
||||
}
|
||||
|
||||
fbinfo->screen_base = (void *)info->fb_buffer;
|
||||
fbinfo->fix.smem_start = (int)info->fb_buffer;
|
||||
|
||||
fbinfo->fbops = &bfin_bf54x_fb_ops;
|
||||
|
||||
fbinfo->pseudo_palette = devm_kzalloc(&pdev->dev, sizeof(u32) * 16,
|
||||
GFP_KERNEL);
|
||||
if (!fbinfo->pseudo_palette) {
|
||||
printk(KERN_ERR DRIVER_NAME
|
||||
"Fail to allocate pseudo_palette\n");
|
||||
|
||||
ret = -ENOMEM;
|
||||
goto out4;
|
||||
}
|
||||
|
||||
if (fb_alloc_cmap(&fbinfo->cmap, BFIN_LCD_NBR_PALETTE_ENTRIES, 0)
|
||||
< 0) {
|
||||
printk(KERN_ERR DRIVER_NAME
|
||||
"Fail to allocate colormap (%d entries)\n",
|
||||
BFIN_LCD_NBR_PALETTE_ENTRIES);
|
||||
ret = -EFAULT;
|
||||
goto out4;
|
||||
}
|
||||
|
||||
if (request_ports(info)) {
|
||||
printk(KERN_ERR DRIVER_NAME ": couldn't request gpio port.\n");
|
||||
ret = -EFAULT;
|
||||
goto out6;
|
||||
}
|
||||
|
||||
info->irq = platform_get_irq(pdev, 0);
|
||||
if (info->irq < 0) {
|
||||
ret = -EINVAL;
|
||||
goto out7;
|
||||
}
|
||||
|
||||
if (request_irq(info->irq, bfin_bf54x_irq_error, 0,
|
||||
"PPI ERROR", info) < 0) {
|
||||
printk(KERN_ERR DRIVER_NAME
|
||||
": unable to request PPI ERROR IRQ\n");
|
||||
ret = -EFAULT;
|
||||
goto out7;
|
||||
}
|
||||
|
||||
if (register_framebuffer(fbinfo) < 0) {
|
||||
printk(KERN_ERR DRIVER_NAME
|
||||
": unable to register framebuffer.\n");
|
||||
ret = -EINVAL;
|
||||
goto out8;
|
||||
}
|
||||
#ifndef NO_BL_SUPPORT
|
||||
memset(&props, 0, sizeof(struct backlight_properties));
|
||||
props.type = BACKLIGHT_RAW;
|
||||
props.max_brightness = 255;
|
||||
bl_dev = backlight_device_register("bf54x-bl", NULL, NULL,
|
||||
&bfin_lq043fb_bl_ops, &props);
|
||||
if (IS_ERR(bl_dev)) {
|
||||
printk(KERN_ERR DRIVER_NAME
|
||||
": unable to register backlight.\n");
|
||||
ret = -EINVAL;
|
||||
unregister_framebuffer(fbinfo);
|
||||
goto out8;
|
||||
}
|
||||
|
||||
lcd_dev = lcd_device_register(DRIVER_NAME, &pdev->dev, NULL, &bfin_lcd_ops);
|
||||
lcd_dev->props.max_contrast = 255, printk(KERN_INFO "Done.\n");
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
|
||||
out8:
|
||||
free_irq(info->irq, info);
|
||||
out7:
|
||||
free_ports(info);
|
||||
out6:
|
||||
fb_dealloc_cmap(&fbinfo->cmap);
|
||||
out4:
|
||||
dma_free_coherent(NULL, fbinfo->fix.smem_len, info->fb_buffer,
|
||||
info->dma_handle);
|
||||
out3:
|
||||
framebuffer_release(fbinfo);
|
||||
out2:
|
||||
free_dma(CH_EPPI0);
|
||||
out1:
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int bfin_bf54x_remove(struct platform_device *pdev)
|
||||
{
|
||||
|
||||
struct fb_info *fbinfo = platform_get_drvdata(pdev);
|
||||
struct bfin_bf54xfb_info *info = fbinfo->par;
|
||||
|
||||
free_dma(CH_EPPI0);
|
||||
free_irq(info->irq, info);
|
||||
|
||||
if (info->fb_buffer != NULL)
|
||||
dma_free_coherent(NULL, fbinfo->fix.smem_len, info->fb_buffer,
|
||||
info->dma_handle);
|
||||
|
||||
fb_dealloc_cmap(&fbinfo->cmap);
|
||||
|
||||
#ifndef NO_BL_SUPPORT
|
||||
lcd_device_unregister(lcd_dev);
|
||||
backlight_device_unregister(bl_dev);
|
||||
#endif
|
||||
|
||||
unregister_framebuffer(fbinfo);
|
||||
|
||||
free_ports(info);
|
||||
|
||||
printk(KERN_INFO DRIVER_NAME ": Unregister LCD driver.\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int bfin_bf54x_suspend(struct platform_device *pdev, pm_message_t state)
|
||||
{
|
||||
bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN);
|
||||
disable_dma(CH_EPPI0);
|
||||
bfin_write_EPPI0_STATUS(0xFFFF);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_bf54x_resume(struct platform_device *pdev)
|
||||
{
|
||||
struct fb_info *fbinfo = platform_get_drvdata(pdev);
|
||||
struct bfin_bf54xfb_info *info = fbinfo->par;
|
||||
|
||||
if (info->lq043_open_cnt) {
|
||||
|
||||
bfin_write_EPPI0_CONTROL(0);
|
||||
SSYNC();
|
||||
|
||||
config_dma(info);
|
||||
config_ppi(info);
|
||||
|
||||
/* start dma */
|
||||
enable_dma(CH_EPPI0);
|
||||
bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
#define bfin_bf54x_suspend NULL
|
||||
#define bfin_bf54x_resume NULL
|
||||
#endif
|
||||
|
||||
static struct platform_driver bfin_bf54x_driver = {
|
||||
.probe = bfin_bf54x_probe,
|
||||
.remove = bfin_bf54x_remove,
|
||||
.suspend = bfin_bf54x_suspend,
|
||||
.resume = bfin_bf54x_resume,
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
},
|
||||
};
|
||||
module_platform_driver(bfin_bf54x_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Blackfin BF54x TFT LCD Driver");
|
||||
MODULE_LICENSE("GPL");
|
|
@ -1,864 +0,0 @@
|
|||
/*
|
||||
* Blackfin LCD Framebuffer driver SHARP LQ035Q1DH02
|
||||
*
|
||||
* Copyright 2008-2009 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#define DRIVER_NAME "bfin-lq035q1"
|
||||
#define pr_fmt(fmt) DRIVER_NAME ": " fmt
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/fb.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/backlight.h>
|
||||
#include <linux/lcd.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/spi/spi.h>
|
||||
|
||||
#include <asm/blackfin.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/dma.h>
|
||||
#include <asm/portmux.h>
|
||||
#include <asm/gptimers.h>
|
||||
|
||||
#include <asm/bfin-lq035q1.h>
|
||||
|
||||
#if defined(BF533_FAMILY) || defined(BF538_FAMILY)
|
||||
#define TIMER_HSYNC_id TIMER1_id
|
||||
#define TIMER_HSYNCbit TIMER1bit
|
||||
#define TIMER_HSYNC_STATUS_TRUN TIMER_STATUS_TRUN1
|
||||
#define TIMER_HSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL1
|
||||
#define TIMER_HSYNC_STATUS_TOVF TIMER_STATUS_TOVF1
|
||||
|
||||
#define TIMER_VSYNC_id TIMER2_id
|
||||
#define TIMER_VSYNCbit TIMER2bit
|
||||
#define TIMER_VSYNC_STATUS_TRUN TIMER_STATUS_TRUN2
|
||||
#define TIMER_VSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL2
|
||||
#define TIMER_VSYNC_STATUS_TOVF TIMER_STATUS_TOVF2
|
||||
#else
|
||||
#define TIMER_HSYNC_id TIMER0_id
|
||||
#define TIMER_HSYNCbit TIMER0bit
|
||||
#define TIMER_HSYNC_STATUS_TRUN TIMER_STATUS_TRUN0
|
||||
#define TIMER_HSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL0
|
||||
#define TIMER_HSYNC_STATUS_TOVF TIMER_STATUS_TOVF0
|
||||
|
||||
#define TIMER_VSYNC_id TIMER1_id
|
||||
#define TIMER_VSYNCbit TIMER1bit
|
||||
#define TIMER_VSYNC_STATUS_TRUN TIMER_STATUS_TRUN1
|
||||
#define TIMER_VSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL1
|
||||
#define TIMER_VSYNC_STATUS_TOVF TIMER_STATUS_TOVF1
|
||||
#endif
|
||||
|
||||
#define LCD_X_RES 320 /* Horizontal Resolution */
|
||||
#define LCD_Y_RES 240 /* Vertical Resolution */
|
||||
#define DMA_BUS_SIZE 16
|
||||
#define U_LINE 4 /* Blanking Lines */
|
||||
|
||||
|
||||
/* Interface 16/18-bit TFT over an 8-bit wide PPI using a small Programmable Logic Device (CPLD)
|
||||
* http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165
|
||||
*/
|
||||
|
||||
|
||||
#define BFIN_LCD_NBR_PALETTE_ENTRIES 256
|
||||
|
||||
#define PPI_TX_MODE 0x2
|
||||
#define PPI_XFER_TYPE_11 0xC
|
||||
#define PPI_PORT_CFG_01 0x10
|
||||
#define PPI_POLS_1 0x8000
|
||||
|
||||
#define LQ035_INDEX 0x74
|
||||
#define LQ035_DATA 0x76
|
||||
|
||||
#define LQ035_DRIVER_OUTPUT_CTL 0x1
|
||||
#define LQ035_SHUT_CTL 0x11
|
||||
|
||||
#define LQ035_DRIVER_OUTPUT_MASK (LQ035_LR | LQ035_TB | LQ035_BGR | LQ035_REV)
|
||||
#define LQ035_DRIVER_OUTPUT_DEFAULT (0x2AEF & ~LQ035_DRIVER_OUTPUT_MASK)
|
||||
|
||||
#define LQ035_SHUT (1 << 0) /* Shutdown */
|
||||
#define LQ035_ON (0 << 0) /* Shutdown */
|
||||
|
||||
struct bfin_lq035q1fb_info {
|
||||
struct fb_info *fb;
|
||||
struct device *dev;
|
||||
struct spi_driver spidrv;
|
||||
struct bfin_lq035q1fb_disp_info *disp_info;
|
||||
unsigned char *fb_buffer; /* RGB Buffer */
|
||||
dma_addr_t dma_handle;
|
||||
int lq035_open_cnt;
|
||||
int irq;
|
||||
spinlock_t lock; /* lock */
|
||||
u32 pseudo_pal[16];
|
||||
|
||||
u32 lcd_bpp;
|
||||
u32 h_actpix;
|
||||
u32 h_period;
|
||||
u32 h_pulse;
|
||||
u32 h_start;
|
||||
u32 v_lines;
|
||||
u32 v_pulse;
|
||||
u32 v_period;
|
||||
};
|
||||
|
||||
static int nocursor;
|
||||
module_param(nocursor, int, 0644);
|
||||
MODULE_PARM_DESC(nocursor, "cursor enable/disable");
|
||||
|
||||
struct spi_control {
|
||||
unsigned short mode;
|
||||
};
|
||||
|
||||
static int lq035q1_control(struct spi_device *spi, unsigned char reg, unsigned short value)
|
||||
{
|
||||
int ret;
|
||||
u8 regs[3] = { LQ035_INDEX, 0, 0 };
|
||||
u8 dat[3] = { LQ035_DATA, 0, 0 };
|
||||
|
||||
if (!spi)
|
||||
return -ENODEV;
|
||||
|
||||
regs[2] = reg;
|
||||
dat[1] = value >> 8;
|
||||
dat[2] = value & 0xFF;
|
||||
|
||||
ret = spi_write(spi, regs, ARRAY_SIZE(regs));
|
||||
ret |= spi_write(spi, dat, ARRAY_SIZE(dat));
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int lq035q1_spidev_probe(struct spi_device *spi)
|
||||
{
|
||||
int ret;
|
||||
struct spi_control *ctl;
|
||||
struct bfin_lq035q1fb_info *info = container_of(spi->dev.driver,
|
||||
struct bfin_lq035q1fb_info,
|
||||
spidrv.driver);
|
||||
|
||||
ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
|
||||
|
||||
if (!ctl)
|
||||
return -ENOMEM;
|
||||
|
||||
ctl->mode = (info->disp_info->mode &
|
||||
LQ035_DRIVER_OUTPUT_MASK) | LQ035_DRIVER_OUTPUT_DEFAULT;
|
||||
|
||||
ret = lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_ON);
|
||||
ret |= lq035q1_control(spi, LQ035_DRIVER_OUTPUT_CTL, ctl->mode);
|
||||
if (ret) {
|
||||
kfree(ctl);
|
||||
return ret;
|
||||
}
|
||||
|
||||
spi_set_drvdata(spi, ctl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lq035q1_spidev_remove(struct spi_device *spi)
|
||||
{
|
||||
return lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_SHUT);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int lq035q1_spidev_suspend(struct device *dev)
|
||||
{
|
||||
struct spi_device *spi = to_spi_device(dev);
|
||||
|
||||
return lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_SHUT);
|
||||
}
|
||||
|
||||
static int lq035q1_spidev_resume(struct device *dev)
|
||||
{
|
||||
struct spi_device *spi = to_spi_device(dev);
|
||||
struct spi_control *ctl = spi_get_drvdata(spi);
|
||||
int ret;
|
||||
|
||||
ret = lq035q1_control(spi, LQ035_DRIVER_OUTPUT_CTL, ctl->mode);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_ON);
|
||||
}
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(lq035q1_spidev_pm_ops, lq035q1_spidev_suspend,
|
||||
lq035q1_spidev_resume);
|
||||
#define LQ035Q1_SPIDEV_PM_OPS (&lq035q1_spidev_pm_ops)
|
||||
|
||||
#else
|
||||
#define LQ035Q1_SPIDEV_PM_OPS NULL
|
||||
#endif
|
||||
|
||||
/* Power down all displays on reboot, poweroff or halt */
|
||||
static void lq035q1_spidev_shutdown(struct spi_device *spi)
|
||||
{
|
||||
lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_SHUT);
|
||||
}
|
||||
|
||||
static int lq035q1_backlight(struct bfin_lq035q1fb_info *info, unsigned arg)
|
||||
{
|
||||
if (info->disp_info->use_bl)
|
||||
gpio_set_value(info->disp_info->gpio_bl, arg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_lq035q1_calc_timing(struct bfin_lq035q1fb_info *fbi)
|
||||
{
|
||||
unsigned long clocks_per_pix, cpld_pipeline_delay_cor;
|
||||
|
||||
/*
|
||||
* Interface 16/18-bit TFT over an 8-bit wide PPI using a small
|
||||
* Programmable Logic Device (CPLD)
|
||||
* http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165
|
||||
*/
|
||||
|
||||
switch (fbi->disp_info->ppi_mode) {
|
||||
case USE_RGB565_16_BIT_PPI:
|
||||
fbi->lcd_bpp = 16;
|
||||
clocks_per_pix = 1;
|
||||
cpld_pipeline_delay_cor = 0;
|
||||
break;
|
||||
case USE_RGB565_8_BIT_PPI:
|
||||
fbi->lcd_bpp = 16;
|
||||
clocks_per_pix = 2;
|
||||
cpld_pipeline_delay_cor = 3;
|
||||
break;
|
||||
case USE_RGB888_8_BIT_PPI:
|
||||
fbi->lcd_bpp = 24;
|
||||
clocks_per_pix = 3;
|
||||
cpld_pipeline_delay_cor = 5;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* HS and VS timing parameters (all in number of PPI clk ticks)
|
||||
*/
|
||||
|
||||
fbi->h_actpix = (LCD_X_RES * clocks_per_pix); /* active horizontal pixel */
|
||||
fbi->h_period = (336 * clocks_per_pix); /* HS period */
|
||||
fbi->h_pulse = (2 * clocks_per_pix); /* HS pulse width */
|
||||
fbi->h_start = (7 * clocks_per_pix + cpld_pipeline_delay_cor); /* first valid pixel */
|
||||
|
||||
fbi->v_lines = (LCD_Y_RES + U_LINE); /* total vertical lines */
|
||||
fbi->v_pulse = (2 * clocks_per_pix); /* VS pulse width (1-5 H_PERIODs) */
|
||||
fbi->v_period = (fbi->h_period * fbi->v_lines); /* VS period */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void bfin_lq035q1_config_ppi(struct bfin_lq035q1fb_info *fbi)
|
||||
{
|
||||
unsigned ppi_pmode;
|
||||
|
||||
if (fbi->disp_info->ppi_mode == USE_RGB565_16_BIT_PPI)
|
||||
ppi_pmode = DLEN_16;
|
||||
else
|
||||
ppi_pmode = (DLEN_8 | PACK_EN);
|
||||
|
||||
bfin_write_PPI_DELAY(fbi->h_start);
|
||||
bfin_write_PPI_COUNT(fbi->h_actpix - 1);
|
||||
bfin_write_PPI_FRAME(fbi->v_lines);
|
||||
|
||||
bfin_write_PPI_CONTROL(PPI_TX_MODE | /* output mode , PORT_DIR */
|
||||
PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */
|
||||
PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */
|
||||
ppi_pmode | /* 8/16 bit data length / PACK_EN? */
|
||||
PPI_POLS_1); /* faling edge syncs POLS */
|
||||
}
|
||||
|
||||
static inline void bfin_lq035q1_disable_ppi(void)
|
||||
{
|
||||
bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN);
|
||||
}
|
||||
|
||||
static inline void bfin_lq035q1_enable_ppi(void)
|
||||
{
|
||||
bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
|
||||
}
|
||||
|
||||
static void bfin_lq035q1_start_timers(void)
|
||||
{
|
||||
enable_gptimers(TIMER_VSYNCbit | TIMER_HSYNCbit);
|
||||
}
|
||||
|
||||
static void bfin_lq035q1_stop_timers(void)
|
||||
{
|
||||
disable_gptimers(TIMER_HSYNCbit | TIMER_VSYNCbit);
|
||||
|
||||
set_gptimer_status(0, TIMER_HSYNC_STATUS_TRUN | TIMER_VSYNC_STATUS_TRUN |
|
||||
TIMER_HSYNC_STATUS_TIMIL | TIMER_VSYNC_STATUS_TIMIL |
|
||||
TIMER_HSYNC_STATUS_TOVF | TIMER_VSYNC_STATUS_TOVF);
|
||||
|
||||
}
|
||||
|
||||
static void bfin_lq035q1_init_timers(struct bfin_lq035q1fb_info *fbi)
|
||||
{
|
||||
|
||||
bfin_lq035q1_stop_timers();
|
||||
|
||||
set_gptimer_period(TIMER_HSYNC_id, fbi->h_period);
|
||||
set_gptimer_pwidth(TIMER_HSYNC_id, fbi->h_pulse);
|
||||
set_gptimer_config(TIMER_HSYNC_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT |
|
||||
TIMER_TIN_SEL | TIMER_CLK_SEL|
|
||||
TIMER_EMU_RUN);
|
||||
|
||||
set_gptimer_period(TIMER_VSYNC_id, fbi->v_period);
|
||||
set_gptimer_pwidth(TIMER_VSYNC_id, fbi->v_pulse);
|
||||
set_gptimer_config(TIMER_VSYNC_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT |
|
||||
TIMER_TIN_SEL | TIMER_CLK_SEL |
|
||||
TIMER_EMU_RUN);
|
||||
|
||||
}
|
||||
|
||||
static void bfin_lq035q1_config_dma(struct bfin_lq035q1fb_info *fbi)
|
||||
{
|
||||
|
||||
|
||||
set_dma_config(CH_PPI,
|
||||
set_bfin_dma_config(DIR_READ, DMA_FLOW_AUTO,
|
||||
INTR_DISABLE, DIMENSION_2D,
|
||||
DATA_SIZE_16,
|
||||
DMA_NOSYNC_KEEP_DMA_BUF));
|
||||
set_dma_x_count(CH_PPI, (LCD_X_RES * fbi->lcd_bpp) / DMA_BUS_SIZE);
|
||||
set_dma_x_modify(CH_PPI, DMA_BUS_SIZE / 8);
|
||||
set_dma_y_count(CH_PPI, fbi->v_lines);
|
||||
|
||||
set_dma_y_modify(CH_PPI, DMA_BUS_SIZE / 8);
|
||||
set_dma_start_addr(CH_PPI, (unsigned long)fbi->fb_buffer);
|
||||
|
||||
}
|
||||
|
||||
static const u16 ppi0_req_16[] = {P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
|
||||
P_PPI0_D0, P_PPI0_D1, P_PPI0_D2,
|
||||
P_PPI0_D3, P_PPI0_D4, P_PPI0_D5,
|
||||
P_PPI0_D6, P_PPI0_D7, P_PPI0_D8,
|
||||
P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
|
||||
P_PPI0_D12, P_PPI0_D13, P_PPI0_D14,
|
||||
P_PPI0_D15, 0};
|
||||
|
||||
static const u16 ppi0_req_8[] = {P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
|
||||
P_PPI0_D0, P_PPI0_D1, P_PPI0_D2,
|
||||
P_PPI0_D3, P_PPI0_D4, P_PPI0_D5,
|
||||
P_PPI0_D6, P_PPI0_D7, 0};
|
||||
|
||||
static inline void bfin_lq035q1_free_ports(unsigned ppi16)
|
||||
{
|
||||
if (ppi16)
|
||||
peripheral_free_list(ppi0_req_16);
|
||||
else
|
||||
peripheral_free_list(ppi0_req_8);
|
||||
|
||||
if (ANOMALY_05000400)
|
||||
gpio_free(P_IDENT(P_PPI0_FS3));
|
||||
}
|
||||
|
||||
static int bfin_lq035q1_request_ports(struct platform_device *pdev,
|
||||
unsigned ppi16)
|
||||
{
|
||||
int ret;
|
||||
/* ANOMALY_05000400 - PPI Does Not Start Properly In Specific Mode:
|
||||
* Drive PPI_FS3 Low
|
||||
*/
|
||||
if (ANOMALY_05000400) {
|
||||
int ret = gpio_request_one(P_IDENT(P_PPI0_FS3),
|
||||
GPIOF_OUT_INIT_LOW, "PPI_FS3");
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (ppi16)
|
||||
ret = peripheral_request_list(ppi0_req_16, DRIVER_NAME);
|
||||
else
|
||||
ret = peripheral_request_list(ppi0_req_8, DRIVER_NAME);
|
||||
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "requesting peripherals failed\n");
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_lq035q1_fb_open(struct fb_info *info, int user)
|
||||
{
|
||||
struct bfin_lq035q1fb_info *fbi = info->par;
|
||||
|
||||
spin_lock(&fbi->lock);
|
||||
fbi->lq035_open_cnt++;
|
||||
|
||||
if (fbi->lq035_open_cnt <= 1) {
|
||||
|
||||
bfin_lq035q1_disable_ppi();
|
||||
SSYNC();
|
||||
|
||||
bfin_lq035q1_config_dma(fbi);
|
||||
bfin_lq035q1_config_ppi(fbi);
|
||||
bfin_lq035q1_init_timers(fbi);
|
||||
|
||||
/* start dma */
|
||||
enable_dma(CH_PPI);
|
||||
bfin_lq035q1_enable_ppi();
|
||||
bfin_lq035q1_start_timers();
|
||||
lq035q1_backlight(fbi, 1);
|
||||
}
|
||||
|
||||
spin_unlock(&fbi->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_lq035q1_fb_release(struct fb_info *info, int user)
|
||||
{
|
||||
struct bfin_lq035q1fb_info *fbi = info->par;
|
||||
|
||||
spin_lock(&fbi->lock);
|
||||
|
||||
fbi->lq035_open_cnt--;
|
||||
|
||||
if (fbi->lq035_open_cnt <= 0) {
|
||||
lq035q1_backlight(fbi, 0);
|
||||
bfin_lq035q1_disable_ppi();
|
||||
SSYNC();
|
||||
disable_dma(CH_PPI);
|
||||
bfin_lq035q1_stop_timers();
|
||||
}
|
||||
|
||||
spin_unlock(&fbi->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_lq035q1_fb_check_var(struct fb_var_screeninfo *var,
|
||||
struct fb_info *info)
|
||||
{
|
||||
struct bfin_lq035q1fb_info *fbi = info->par;
|
||||
|
||||
if (var->bits_per_pixel == fbi->lcd_bpp) {
|
||||
var->red.offset = info->var.red.offset;
|
||||
var->green.offset = info->var.green.offset;
|
||||
var->blue.offset = info->var.blue.offset;
|
||||
var->red.length = info->var.red.length;
|
||||
var->green.length = info->var.green.length;
|
||||
var->blue.length = info->var.blue.length;
|
||||
var->transp.offset = 0;
|
||||
var->transp.length = 0;
|
||||
var->transp.msb_right = 0;
|
||||
var->red.msb_right = 0;
|
||||
var->green.msb_right = 0;
|
||||
var->blue.msb_right = 0;
|
||||
} else {
|
||||
pr_debug("%s: depth not supported: %u BPP\n", __func__,
|
||||
var->bits_per_pixel);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (info->var.xres != var->xres || info->var.yres != var->yres ||
|
||||
info->var.xres_virtual != var->xres_virtual ||
|
||||
info->var.yres_virtual != var->yres_virtual) {
|
||||
pr_debug("%s: Resolution not supported: X%u x Y%u \n",
|
||||
__func__, var->xres, var->yres);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Memory limit
|
||||
*/
|
||||
|
||||
if ((info->fix.line_length * var->yres_virtual) > info->fix.smem_len) {
|
||||
pr_debug("%s: Memory Limit requested yres_virtual = %u\n",
|
||||
__func__, var->yres_virtual);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int bfin_lq035q1_fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
|
||||
{
|
||||
if (nocursor)
|
||||
return 0;
|
||||
else
|
||||
return -EINVAL; /* just to force soft_cursor() call */
|
||||
}
|
||||
|
||||
static int bfin_lq035q1_fb_setcolreg(u_int regno, u_int red, u_int green,
|
||||
u_int blue, u_int transp,
|
||||
struct fb_info *info)
|
||||
{
|
||||
if (regno >= BFIN_LCD_NBR_PALETTE_ENTRIES)
|
||||
return -EINVAL;
|
||||
|
||||
if (info->var.grayscale) {
|
||||
/* grayscale = 0.30*R + 0.59*G + 0.11*B */
|
||||
red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
|
||||
}
|
||||
|
||||
if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
|
||||
|
||||
u32 value;
|
||||
/* Place color in the pseudopalette */
|
||||
if (regno > 16)
|
||||
return -EINVAL;
|
||||
|
||||
red >>= (16 - info->var.red.length);
|
||||
green >>= (16 - info->var.green.length);
|
||||
blue >>= (16 - info->var.blue.length);
|
||||
|
||||
value = (red << info->var.red.offset) |
|
||||
(green << info->var.green.offset) |
|
||||
(blue << info->var.blue.offset);
|
||||
value &= 0xFFFFFF;
|
||||
|
||||
((u32 *) (info->pseudo_palette))[regno] = value;
|
||||
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct fb_ops bfin_lq035q1_fb_ops = {
|
||||
.owner = THIS_MODULE,
|
||||
.fb_open = bfin_lq035q1_fb_open,
|
||||
.fb_release = bfin_lq035q1_fb_release,
|
||||
.fb_check_var = bfin_lq035q1_fb_check_var,
|
||||
.fb_fillrect = cfb_fillrect,
|
||||
.fb_copyarea = cfb_copyarea,
|
||||
.fb_imageblit = cfb_imageblit,
|
||||
.fb_cursor = bfin_lq035q1_fb_cursor,
|
||||
.fb_setcolreg = bfin_lq035q1_fb_setcolreg,
|
||||
};
|
||||
|
||||
static irqreturn_t bfin_lq035q1_irq_error(int irq, void *dev_id)
|
||||
{
|
||||
/*struct bfin_lq035q1fb_info *info = (struct bfin_lq035q1fb_info *)dev_id;*/
|
||||
|
||||
u16 status = bfin_read_PPI_STATUS();
|
||||
bfin_write_PPI_STATUS(-1);
|
||||
|
||||
if (status) {
|
||||
bfin_lq035q1_disable_ppi();
|
||||
disable_dma(CH_PPI);
|
||||
|
||||
/* start dma */
|
||||
enable_dma(CH_PPI);
|
||||
bfin_lq035q1_enable_ppi();
|
||||
bfin_write_PPI_STATUS(-1);
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int bfin_lq035q1_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct bfin_lq035q1fb_info *info;
|
||||
struct fb_info *fbinfo;
|
||||
u32 active_video_mem_offset;
|
||||
int ret;
|
||||
|
||||
ret = request_dma(CH_PPI, DRIVER_NAME"_CH_PPI");
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "PPI DMA unavailable\n");
|
||||
goto out1;
|
||||
}
|
||||
|
||||
fbinfo = framebuffer_alloc(sizeof(*info), &pdev->dev);
|
||||
if (!fbinfo) {
|
||||
ret = -ENOMEM;
|
||||
goto out2;
|
||||
}
|
||||
|
||||
info = fbinfo->par;
|
||||
info->fb = fbinfo;
|
||||
info->dev = &pdev->dev;
|
||||
spin_lock_init(&info->lock);
|
||||
|
||||
info->disp_info = pdev->dev.platform_data;
|
||||
|
||||
platform_set_drvdata(pdev, fbinfo);
|
||||
|
||||
ret = bfin_lq035q1_calc_timing(info);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Failed PPI Mode\n");
|
||||
goto out3;
|
||||
}
|
||||
|
||||
strcpy(fbinfo->fix.id, DRIVER_NAME);
|
||||
|
||||
fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
|
||||
fbinfo->fix.type_aux = 0;
|
||||
fbinfo->fix.xpanstep = 0;
|
||||
fbinfo->fix.ypanstep = 0;
|
||||
fbinfo->fix.ywrapstep = 0;
|
||||
fbinfo->fix.accel = FB_ACCEL_NONE;
|
||||
fbinfo->fix.visual = FB_VISUAL_TRUECOLOR;
|
||||
|
||||
fbinfo->var.nonstd = 0;
|
||||
fbinfo->var.activate = FB_ACTIVATE_NOW;
|
||||
fbinfo->var.height = -1;
|
||||
fbinfo->var.width = -1;
|
||||
fbinfo->var.accel_flags = 0;
|
||||
fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
|
||||
|
||||
fbinfo->var.xres = LCD_X_RES;
|
||||
fbinfo->var.xres_virtual = LCD_X_RES;
|
||||
fbinfo->var.yres = LCD_Y_RES;
|
||||
fbinfo->var.yres_virtual = LCD_Y_RES;
|
||||
fbinfo->var.bits_per_pixel = info->lcd_bpp;
|
||||
|
||||
if (info->disp_info->mode & LQ035_BGR) {
|
||||
if (info->lcd_bpp == 24) {
|
||||
fbinfo->var.red.offset = 0;
|
||||
fbinfo->var.green.offset = 8;
|
||||
fbinfo->var.blue.offset = 16;
|
||||
} else {
|
||||
fbinfo->var.red.offset = 0;
|
||||
fbinfo->var.green.offset = 5;
|
||||
fbinfo->var.blue.offset = 11;
|
||||
}
|
||||
} else {
|
||||
if (info->lcd_bpp == 24) {
|
||||
fbinfo->var.red.offset = 16;
|
||||
fbinfo->var.green.offset = 8;
|
||||
fbinfo->var.blue.offset = 0;
|
||||
} else {
|
||||
fbinfo->var.red.offset = 11;
|
||||
fbinfo->var.green.offset = 5;
|
||||
fbinfo->var.blue.offset = 0;
|
||||
}
|
||||
}
|
||||
|
||||
fbinfo->var.transp.offset = 0;
|
||||
|
||||
if (info->lcd_bpp == 24) {
|
||||
fbinfo->var.red.length = 8;
|
||||
fbinfo->var.green.length = 8;
|
||||
fbinfo->var.blue.length = 8;
|
||||
} else {
|
||||
fbinfo->var.red.length = 5;
|
||||
fbinfo->var.green.length = 6;
|
||||
fbinfo->var.blue.length = 5;
|
||||
}
|
||||
|
||||
fbinfo->var.transp.length = 0;
|
||||
|
||||
active_video_mem_offset = ((U_LINE / 2) * LCD_X_RES * (info->lcd_bpp / 8));
|
||||
|
||||
fbinfo->fix.smem_len = LCD_X_RES * LCD_Y_RES * info->lcd_bpp / 8
|
||||
+ active_video_mem_offset;
|
||||
|
||||
fbinfo->fix.line_length = fbinfo->var.xres_virtual *
|
||||
fbinfo->var.bits_per_pixel / 8;
|
||||
|
||||
|
||||
fbinfo->fbops = &bfin_lq035q1_fb_ops;
|
||||
fbinfo->flags = FBINFO_FLAG_DEFAULT;
|
||||
|
||||
info->fb_buffer =
|
||||
dma_alloc_coherent(NULL, fbinfo->fix.smem_len, &info->dma_handle,
|
||||
GFP_KERNEL);
|
||||
|
||||
if (NULL == info->fb_buffer) {
|
||||
dev_err(&pdev->dev, "couldn't allocate dma buffer\n");
|
||||
ret = -ENOMEM;
|
||||
goto out3;
|
||||
}
|
||||
|
||||
fbinfo->screen_base = (void *)info->fb_buffer + active_video_mem_offset;
|
||||
fbinfo->fix.smem_start = (int)info->fb_buffer + active_video_mem_offset;
|
||||
|
||||
fbinfo->fbops = &bfin_lq035q1_fb_ops;
|
||||
|
||||
fbinfo->pseudo_palette = &info->pseudo_pal;
|
||||
|
||||
ret = fb_alloc_cmap(&fbinfo->cmap, BFIN_LCD_NBR_PALETTE_ENTRIES, 0);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "failed to allocate colormap (%d entries)\n",
|
||||
BFIN_LCD_NBR_PALETTE_ENTRIES);
|
||||
goto out4;
|
||||
}
|
||||
|
||||
ret = bfin_lq035q1_request_ports(pdev,
|
||||
info->disp_info->ppi_mode == USE_RGB565_16_BIT_PPI);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "couldn't request gpio port\n");
|
||||
goto out6;
|
||||
}
|
||||
|
||||
info->irq = platform_get_irq(pdev, 0);
|
||||
if (info->irq < 0) {
|
||||
ret = -EINVAL;
|
||||
goto out7;
|
||||
}
|
||||
|
||||
ret = request_irq(info->irq, bfin_lq035q1_irq_error, 0,
|
||||
DRIVER_NAME" PPI ERROR", info);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "unable to request PPI ERROR IRQ\n");
|
||||
goto out7;
|
||||
}
|
||||
|
||||
info->spidrv.driver.name = DRIVER_NAME"-spi";
|
||||
info->spidrv.probe = lq035q1_spidev_probe;
|
||||
info->spidrv.remove = lq035q1_spidev_remove;
|
||||
info->spidrv.shutdown = lq035q1_spidev_shutdown;
|
||||
info->spidrv.driver.pm = LQ035Q1_SPIDEV_PM_OPS;
|
||||
|
||||
ret = spi_register_driver(&info->spidrv);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "couldn't register SPI Interface\n");
|
||||
goto out8;
|
||||
}
|
||||
|
||||
if (info->disp_info->use_bl) {
|
||||
ret = gpio_request_one(info->disp_info->gpio_bl,
|
||||
GPIOF_OUT_INIT_LOW, "LQ035 Backlight");
|
||||
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to request GPIO %d\n",
|
||||
info->disp_info->gpio_bl);
|
||||
goto out9;
|
||||
}
|
||||
}
|
||||
|
||||
ret = register_framebuffer(fbinfo);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "unable to register framebuffer\n");
|
||||
goto out10;
|
||||
}
|
||||
|
||||
dev_info(&pdev->dev, "%dx%d %d-bit RGB FrameBuffer initialized\n",
|
||||
LCD_X_RES, LCD_Y_RES, info->lcd_bpp);
|
||||
|
||||
return 0;
|
||||
|
||||
out10:
|
||||
if (info->disp_info->use_bl)
|
||||
gpio_free(info->disp_info->gpio_bl);
|
||||
out9:
|
||||
spi_unregister_driver(&info->spidrv);
|
||||
out8:
|
||||
free_irq(info->irq, info);
|
||||
out7:
|
||||
bfin_lq035q1_free_ports(info->disp_info->ppi_mode ==
|
||||
USE_RGB565_16_BIT_PPI);
|
||||
out6:
|
||||
fb_dealloc_cmap(&fbinfo->cmap);
|
||||
out4:
|
||||
dma_free_coherent(NULL, fbinfo->fix.smem_len, info->fb_buffer,
|
||||
info->dma_handle);
|
||||
out3:
|
||||
framebuffer_release(fbinfo);
|
||||
out2:
|
||||
free_dma(CH_PPI);
|
||||
out1:
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int bfin_lq035q1_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct fb_info *fbinfo = platform_get_drvdata(pdev);
|
||||
struct bfin_lq035q1fb_info *info = fbinfo->par;
|
||||
|
||||
if (info->disp_info->use_bl)
|
||||
gpio_free(info->disp_info->gpio_bl);
|
||||
|
||||
spi_unregister_driver(&info->spidrv);
|
||||
|
||||
unregister_framebuffer(fbinfo);
|
||||
|
||||
free_dma(CH_PPI);
|
||||
free_irq(info->irq, info);
|
||||
|
||||
if (info->fb_buffer != NULL)
|
||||
dma_free_coherent(NULL, fbinfo->fix.smem_len, info->fb_buffer,
|
||||
info->dma_handle);
|
||||
|
||||
fb_dealloc_cmap(&fbinfo->cmap);
|
||||
|
||||
bfin_lq035q1_free_ports(info->disp_info->ppi_mode ==
|
||||
USE_RGB565_16_BIT_PPI);
|
||||
|
||||
framebuffer_release(fbinfo);
|
||||
|
||||
dev_info(&pdev->dev, "unregistered LCD driver\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int bfin_lq035q1_suspend(struct device *dev)
|
||||
{
|
||||
struct fb_info *fbinfo = dev_get_drvdata(dev);
|
||||
struct bfin_lq035q1fb_info *info = fbinfo->par;
|
||||
|
||||
if (info->lq035_open_cnt) {
|
||||
lq035q1_backlight(info, 0);
|
||||
bfin_lq035q1_disable_ppi();
|
||||
SSYNC();
|
||||
disable_dma(CH_PPI);
|
||||
bfin_lq035q1_stop_timers();
|
||||
bfin_write_PPI_STATUS(-1);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_lq035q1_resume(struct device *dev)
|
||||
{
|
||||
struct fb_info *fbinfo = dev_get_drvdata(dev);
|
||||
struct bfin_lq035q1fb_info *info = fbinfo->par;
|
||||
|
||||
if (info->lq035_open_cnt) {
|
||||
bfin_lq035q1_disable_ppi();
|
||||
SSYNC();
|
||||
|
||||
bfin_lq035q1_config_dma(info);
|
||||
bfin_lq035q1_config_ppi(info);
|
||||
bfin_lq035q1_init_timers(info);
|
||||
|
||||
/* start dma */
|
||||
enable_dma(CH_PPI);
|
||||
bfin_lq035q1_enable_ppi();
|
||||
bfin_lq035q1_start_timers();
|
||||
lq035q1_backlight(info, 1);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops bfin_lq035q1_dev_pm_ops = {
|
||||
.suspend = bfin_lq035q1_suspend,
|
||||
.resume = bfin_lq035q1_resume,
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct platform_driver bfin_lq035q1_driver = {
|
||||
.probe = bfin_lq035q1_probe,
|
||||
.remove = bfin_lq035q1_remove,
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
#ifdef CONFIG_PM
|
||||
.pm = &bfin_lq035q1_dev_pm_ops,
|
||||
#endif
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(bfin_lq035q1_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Blackfin TFT LCD Driver");
|
||||
MODULE_LICENSE("GPL");
|
|
@ -1,669 +0,0 @@
|
|||
/*
|
||||
* File: drivers/video/bfin-t350mcqb-fb.c
|
||||
* Based on:
|
||||
* Author: Michael Hennerich <hennerich@blackfin.uclinux.org>
|
||||
*
|
||||
* Created:
|
||||
* Description: Blackfin LCD Framebuffer driver
|
||||
*
|
||||
*
|
||||
* Modified:
|
||||
* Copyright 2004-2007 Analog Devices Inc.
|
||||
*
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see the file COPYING, or write
|
||||
* to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/gfp.h>
|
||||
#include <linux/fb.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/backlight.h>
|
||||
#include <linux/lcd.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/blackfin.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/dma-mapping.h>
|
||||
#include <asm/dma.h>
|
||||
#include <asm/portmux.h>
|
||||
#include <asm/gptimers.h>
|
||||
|
||||
#define NO_BL_SUPPORT
|
||||
|
||||
#define LCD_X_RES 320 /* Horizontal Resolution */
|
||||
#define LCD_Y_RES 240 /* Vertical Resolution */
|
||||
#define LCD_BPP 24 /* Bit Per Pixel */
|
||||
|
||||
#define DMA_BUS_SIZE 16
|
||||
#define LCD_CLK (12*1000*1000) /* 12MHz */
|
||||
|
||||
#define CLOCKS_PER_PIX 3
|
||||
|
||||
/*
|
||||
* HS and VS timing parameters (all in number of PPI clk ticks)
|
||||
*/
|
||||
|
||||
#define U_LINE 1 /* Blanking Lines */
|
||||
|
||||
#define H_ACTPIX (LCD_X_RES * CLOCKS_PER_PIX) /* active horizontal pixel */
|
||||
#define H_PERIOD (408 * CLOCKS_PER_PIX) /* HS period */
|
||||
#define H_PULSE 90 /* HS pulse width */
|
||||
#define H_START 204 /* first valid pixel */
|
||||
|
||||
#define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */
|
||||
#define V_PULSE (3 * H_PERIOD) /* VS pulse width (1-5 H_PERIODs) */
|
||||
#define V_PERIOD (H_PERIOD * V_LINES) /* VS period */
|
||||
|
||||
#define ACTIVE_VIDEO_MEM_OFFSET (U_LINE * H_ACTPIX)
|
||||
|
||||
#define BFIN_LCD_NBR_PALETTE_ENTRIES 256
|
||||
|
||||
#define DRIVER_NAME "bfin-t350mcqb"
|
||||
static char driver_name[] = DRIVER_NAME;
|
||||
|
||||
struct bfin_t350mcqbfb_info {
|
||||
struct fb_info *fb;
|
||||
struct device *dev;
|
||||
unsigned char *fb_buffer; /* RGB Buffer */
|
||||
dma_addr_t dma_handle;
|
||||
int lq043_open_cnt;
|
||||
int irq;
|
||||
spinlock_t lock; /* lock */
|
||||
u32 pseudo_pal[16];
|
||||
};
|
||||
|
||||
static int nocursor;
|
||||
module_param(nocursor, int, 0644);
|
||||
MODULE_PARM_DESC(nocursor, "cursor enable/disable");
|
||||
|
||||
#define PPI_TX_MODE 0x2
|
||||
#define PPI_XFER_TYPE_11 0xC
|
||||
#define PPI_PORT_CFG_01 0x10
|
||||
#define PPI_PACK_EN 0x80
|
||||
#define PPI_POLS_1 0x8000
|
||||
|
||||
static void bfin_t350mcqb_config_ppi(struct bfin_t350mcqbfb_info *fbi)
|
||||
{
|
||||
bfin_write_PPI_DELAY(H_START);
|
||||
bfin_write_PPI_COUNT(H_ACTPIX-1);
|
||||
bfin_write_PPI_FRAME(V_LINES);
|
||||
|
||||
bfin_write_PPI_CONTROL(PPI_TX_MODE | /* output mode , PORT_DIR */
|
||||
PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */
|
||||
PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */
|
||||
PPI_PACK_EN | /* packing enabled PACK_EN */
|
||||
PPI_POLS_1); /* faling edge syncs POLS */
|
||||
}
|
||||
|
||||
static inline void bfin_t350mcqb_disable_ppi(void)
|
||||
{
|
||||
bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN);
|
||||
}
|
||||
|
||||
static inline void bfin_t350mcqb_enable_ppi(void)
|
||||
{
|
||||
bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
|
||||
}
|
||||
|
||||
static void bfin_t350mcqb_start_timers(void)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
enable_gptimers(TIMER1bit);
|
||||
enable_gptimers(TIMER0bit);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static void bfin_t350mcqb_stop_timers(void)
|
||||
{
|
||||
disable_gptimers(TIMER0bit | TIMER1bit);
|
||||
|
||||
set_gptimer_status(0, TIMER_STATUS_TRUN0 | TIMER_STATUS_TRUN1 |
|
||||
TIMER_STATUS_TIMIL0 | TIMER_STATUS_TIMIL1 |
|
||||
TIMER_STATUS_TOVF0 | TIMER_STATUS_TOVF1);
|
||||
|
||||
}
|
||||
|
||||
static void bfin_t350mcqb_init_timers(void)
|
||||
{
|
||||
|
||||
bfin_t350mcqb_stop_timers();
|
||||
|
||||
set_gptimer_period(TIMER0_id, H_PERIOD);
|
||||
set_gptimer_pwidth(TIMER0_id, H_PULSE);
|
||||
set_gptimer_config(TIMER0_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT |
|
||||
TIMER_TIN_SEL | TIMER_CLK_SEL|
|
||||
TIMER_EMU_RUN);
|
||||
|
||||
set_gptimer_period(TIMER1_id, V_PERIOD);
|
||||
set_gptimer_pwidth(TIMER1_id, V_PULSE);
|
||||
set_gptimer_config(TIMER1_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT |
|
||||
TIMER_TIN_SEL | TIMER_CLK_SEL |
|
||||
TIMER_EMU_RUN);
|
||||
|
||||
}
|
||||
|
||||
static void bfin_t350mcqb_config_dma(struct bfin_t350mcqbfb_info *fbi)
|
||||
{
|
||||
|
||||
set_dma_config(CH_PPI,
|
||||
set_bfin_dma_config(DIR_READ, DMA_FLOW_AUTO,
|
||||
INTR_DISABLE, DIMENSION_2D,
|
||||
DATA_SIZE_16,
|
||||
DMA_NOSYNC_KEEP_DMA_BUF));
|
||||
set_dma_x_count(CH_PPI, (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE);
|
||||
set_dma_x_modify(CH_PPI, DMA_BUS_SIZE / 8);
|
||||
set_dma_y_count(CH_PPI, V_LINES);
|
||||
|
||||
set_dma_y_modify(CH_PPI, DMA_BUS_SIZE / 8);
|
||||
set_dma_start_addr(CH_PPI, (unsigned long)fbi->fb_buffer);
|
||||
|
||||
}
|
||||
|
||||
static u16 ppi0_req_8[] = {P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
|
||||
P_PPI0_D0, P_PPI0_D1, P_PPI0_D2,
|
||||
P_PPI0_D3, P_PPI0_D4, P_PPI0_D5,
|
||||
P_PPI0_D6, P_PPI0_D7, 0};
|
||||
|
||||
static int bfin_t350mcqb_request_ports(int action)
|
||||
{
|
||||
if (action) {
|
||||
if (peripheral_request_list(ppi0_req_8, DRIVER_NAME)) {
|
||||
printk(KERN_ERR "Requesting Peripherals failed\n");
|
||||
return -EFAULT;
|
||||
}
|
||||
} else
|
||||
peripheral_free_list(ppi0_req_8);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_t350mcqb_fb_open(struct fb_info *info, int user)
|
||||
{
|
||||
struct bfin_t350mcqbfb_info *fbi = info->par;
|
||||
|
||||
spin_lock(&fbi->lock);
|
||||
fbi->lq043_open_cnt++;
|
||||
|
||||
if (fbi->lq043_open_cnt <= 1) {
|
||||
|
||||
bfin_t350mcqb_disable_ppi();
|
||||
SSYNC();
|
||||
|
||||
bfin_t350mcqb_config_dma(fbi);
|
||||
bfin_t350mcqb_config_ppi(fbi);
|
||||
bfin_t350mcqb_init_timers();
|
||||
|
||||
/* start dma */
|
||||
enable_dma(CH_PPI);
|
||||
bfin_t350mcqb_enable_ppi();
|
||||
bfin_t350mcqb_start_timers();
|
||||
}
|
||||
|
||||
spin_unlock(&fbi->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_t350mcqb_fb_release(struct fb_info *info, int user)
|
||||
{
|
||||
struct bfin_t350mcqbfb_info *fbi = info->par;
|
||||
|
||||
spin_lock(&fbi->lock);
|
||||
|
||||
fbi->lq043_open_cnt--;
|
||||
|
||||
if (fbi->lq043_open_cnt <= 0) {
|
||||
bfin_t350mcqb_disable_ppi();
|
||||
SSYNC();
|
||||
disable_dma(CH_PPI);
|
||||
bfin_t350mcqb_stop_timers();
|
||||
}
|
||||
|
||||
spin_unlock(&fbi->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_t350mcqb_fb_check_var(struct fb_var_screeninfo *var,
|
||||
struct fb_info *info)
|
||||
{
|
||||
|
||||
switch (var->bits_per_pixel) {
|
||||
case 24:/* TRUECOLOUR, 16m */
|
||||
var->red.offset = 0;
|
||||
var->green.offset = 8;
|
||||
var->blue.offset = 16;
|
||||
var->red.length = var->green.length = var->blue.length = 8;
|
||||
var->transp.offset = 0;
|
||||
var->transp.length = 0;
|
||||
var->transp.msb_right = 0;
|
||||
var->red.msb_right = 0;
|
||||
var->green.msb_right = 0;
|
||||
var->blue.msb_right = 0;
|
||||
break;
|
||||
default:
|
||||
pr_debug("%s: depth not supported: %u BPP\n", __func__,
|
||||
var->bits_per_pixel);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (info->var.xres != var->xres || info->var.yres != var->yres ||
|
||||
info->var.xres_virtual != var->xres_virtual ||
|
||||
info->var.yres_virtual != var->yres_virtual) {
|
||||
pr_debug("%s: Resolution not supported: X%u x Y%u \n",
|
||||
__func__, var->xres, var->yres);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Memory limit
|
||||
*/
|
||||
|
||||
if ((info->fix.line_length * var->yres_virtual) > info->fix.smem_len) {
|
||||
pr_debug("%s: Memory Limit requested yres_virtual = %u\n",
|
||||
__func__, var->yres_virtual);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int bfin_t350mcqb_fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
|
||||
{
|
||||
if (nocursor)
|
||||
return 0;
|
||||
else
|
||||
return -EINVAL; /* just to force soft_cursor() call */
|
||||
}
|
||||
|
||||
static int bfin_t350mcqb_fb_setcolreg(u_int regno, u_int red, u_int green,
|
||||
u_int blue, u_int transp,
|
||||
struct fb_info *info)
|
||||
{
|
||||
if (regno >= BFIN_LCD_NBR_PALETTE_ENTRIES)
|
||||
return -EINVAL;
|
||||
|
||||
if (info->var.grayscale) {
|
||||
/* grayscale = 0.30*R + 0.59*G + 0.11*B */
|
||||
red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
|
||||
}
|
||||
|
||||
if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
|
||||
|
||||
u32 value;
|
||||
/* Place color in the pseudopalette */
|
||||
if (regno > 16)
|
||||
return -EINVAL;
|
||||
|
||||
red >>= (16 - info->var.red.length);
|
||||
green >>= (16 - info->var.green.length);
|
||||
blue >>= (16 - info->var.blue.length);
|
||||
|
||||
value = (red << info->var.red.offset) |
|
||||
(green << info->var.green.offset) |
|
||||
(blue << info->var.blue.offset);
|
||||
value &= 0xFFFFFF;
|
||||
|
||||
((u32 *) (info->pseudo_palette))[regno] = value;
|
||||
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct fb_ops bfin_t350mcqb_fb_ops = {
|
||||
.owner = THIS_MODULE,
|
||||
.fb_open = bfin_t350mcqb_fb_open,
|
||||
.fb_release = bfin_t350mcqb_fb_release,
|
||||
.fb_check_var = bfin_t350mcqb_fb_check_var,
|
||||
.fb_fillrect = cfb_fillrect,
|
||||
.fb_copyarea = cfb_copyarea,
|
||||
.fb_imageblit = cfb_imageblit,
|
||||
.fb_cursor = bfin_t350mcqb_fb_cursor,
|
||||
.fb_setcolreg = bfin_t350mcqb_fb_setcolreg,
|
||||
};
|
||||
|
||||
#ifndef NO_BL_SUPPORT
|
||||
static int bl_get_brightness(struct backlight_device *bd)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct backlight_ops bfin_lq043fb_bl_ops = {
|
||||
.get_brightness = bl_get_brightness,
|
||||
};
|
||||
|
||||
static struct backlight_device *bl_dev;
|
||||
|
||||
static int bfin_lcd_get_power(struct lcd_device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_lcd_set_power(struct lcd_device *dev, int power)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_lcd_get_contrast(struct lcd_device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_lcd_set_contrast(struct lcd_device *dev, int contrast)
|
||||
{
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_lcd_check_fb(struct lcd_device *dev, struct fb_info *fi)
|
||||
{
|
||||
if (!fi || (fi == &bfin_t350mcqb_fb))
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct lcd_ops bfin_lcd_ops = {
|
||||
.get_power = bfin_lcd_get_power,
|
||||
.set_power = bfin_lcd_set_power,
|
||||
.get_contrast = bfin_lcd_get_contrast,
|
||||
.set_contrast = bfin_lcd_set_contrast,
|
||||
.check_fb = bfin_lcd_check_fb,
|
||||
};
|
||||
|
||||
static struct lcd_device *lcd_dev;
|
||||
#endif
|
||||
|
||||
static irqreturn_t bfin_t350mcqb_irq_error(int irq, void *dev_id)
|
||||
{
|
||||
/*struct bfin_t350mcqbfb_info *info = (struct bfin_t350mcqbfb_info *)dev_id;*/
|
||||
|
||||
u16 status = bfin_read_PPI_STATUS();
|
||||
bfin_write_PPI_STATUS(0xFFFF);
|
||||
|
||||
if (status) {
|
||||
bfin_t350mcqb_disable_ppi();
|
||||
disable_dma(CH_PPI);
|
||||
|
||||
/* start dma */
|
||||
enable_dma(CH_PPI);
|
||||
bfin_t350mcqb_enable_ppi();
|
||||
bfin_write_PPI_STATUS(0xFFFF);
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int bfin_t350mcqb_probe(struct platform_device *pdev)
|
||||
{
|
||||
#ifndef NO_BL_SUPPORT
|
||||
struct backlight_properties props;
|
||||
#endif
|
||||
struct bfin_t350mcqbfb_info *info;
|
||||
struct fb_info *fbinfo;
|
||||
int ret;
|
||||
|
||||
printk(KERN_INFO DRIVER_NAME ": %dx%d %d-bit RGB FrameBuffer initializing...\n",
|
||||
LCD_X_RES, LCD_Y_RES, LCD_BPP);
|
||||
|
||||
if (request_dma(CH_PPI, "CH_PPI") < 0) {
|
||||
printk(KERN_ERR DRIVER_NAME
|
||||
": couldn't request CH_PPI DMA\n");
|
||||
ret = -EFAULT;
|
||||
goto out1;
|
||||
}
|
||||
|
||||
fbinfo =
|
||||
framebuffer_alloc(sizeof(struct bfin_t350mcqbfb_info), &pdev->dev);
|
||||
if (!fbinfo) {
|
||||
ret = -ENOMEM;
|
||||
goto out2;
|
||||
}
|
||||
|
||||
info = fbinfo->par;
|
||||
info->fb = fbinfo;
|
||||
info->dev = &pdev->dev;
|
||||
spin_lock_init(&info->lock);
|
||||
|
||||
platform_set_drvdata(pdev, fbinfo);
|
||||
|
||||
strcpy(fbinfo->fix.id, driver_name);
|
||||
|
||||
fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
|
||||
fbinfo->fix.type_aux = 0;
|
||||
fbinfo->fix.xpanstep = 0;
|
||||
fbinfo->fix.ypanstep = 0;
|
||||
fbinfo->fix.ywrapstep = 0;
|
||||
fbinfo->fix.accel = FB_ACCEL_NONE;
|
||||
fbinfo->fix.visual = FB_VISUAL_TRUECOLOR;
|
||||
|
||||
fbinfo->var.nonstd = 0;
|
||||
fbinfo->var.activate = FB_ACTIVATE_NOW;
|
||||
fbinfo->var.height = 53;
|
||||
fbinfo->var.width = 70;
|
||||
fbinfo->var.accel_flags = 0;
|
||||
fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
|
||||
|
||||
fbinfo->var.xres = LCD_X_RES;
|
||||
fbinfo->var.xres_virtual = LCD_X_RES;
|
||||
fbinfo->var.yres = LCD_Y_RES;
|
||||
fbinfo->var.yres_virtual = LCD_Y_RES;
|
||||
fbinfo->var.bits_per_pixel = LCD_BPP;
|
||||
|
||||
fbinfo->var.red.offset = 0;
|
||||
fbinfo->var.green.offset = 8;
|
||||
fbinfo->var.blue.offset = 16;
|
||||
fbinfo->var.transp.offset = 0;
|
||||
fbinfo->var.red.length = 8;
|
||||
fbinfo->var.green.length = 8;
|
||||
fbinfo->var.blue.length = 8;
|
||||
fbinfo->var.transp.length = 0;
|
||||
fbinfo->fix.smem_len = LCD_X_RES * LCD_Y_RES * LCD_BPP / 8;
|
||||
|
||||
fbinfo->fix.line_length = fbinfo->var.xres_virtual *
|
||||
fbinfo->var.bits_per_pixel / 8;
|
||||
|
||||
|
||||
fbinfo->fbops = &bfin_t350mcqb_fb_ops;
|
||||
fbinfo->flags = FBINFO_FLAG_DEFAULT;
|
||||
|
||||
info->fb_buffer = dma_alloc_coherent(NULL, fbinfo->fix.smem_len +
|
||||
ACTIVE_VIDEO_MEM_OFFSET,
|
||||
&info->dma_handle, GFP_KERNEL);
|
||||
|
||||
if (NULL == info->fb_buffer) {
|
||||
printk(KERN_ERR DRIVER_NAME
|
||||
": couldn't allocate dma buffer.\n");
|
||||
ret = -ENOMEM;
|
||||
goto out3;
|
||||
}
|
||||
|
||||
fbinfo->screen_base = (void *)info->fb_buffer + ACTIVE_VIDEO_MEM_OFFSET;
|
||||
fbinfo->fix.smem_start = (int)info->fb_buffer + ACTIVE_VIDEO_MEM_OFFSET;
|
||||
|
||||
fbinfo->fbops = &bfin_t350mcqb_fb_ops;
|
||||
|
||||
fbinfo->pseudo_palette = &info->pseudo_pal;
|
||||
|
||||
if (fb_alloc_cmap(&fbinfo->cmap, BFIN_LCD_NBR_PALETTE_ENTRIES, 0)
|
||||
< 0) {
|
||||
printk(KERN_ERR DRIVER_NAME
|
||||
"Fail to allocate colormap (%d entries)\n",
|
||||
BFIN_LCD_NBR_PALETTE_ENTRIES);
|
||||
ret = -EFAULT;
|
||||
goto out4;
|
||||
}
|
||||
|
||||
if (bfin_t350mcqb_request_ports(1)) {
|
||||
printk(KERN_ERR DRIVER_NAME ": couldn't request gpio port.\n");
|
||||
ret = -EFAULT;
|
||||
goto out6;
|
||||
}
|
||||
|
||||
info->irq = platform_get_irq(pdev, 0);
|
||||
if (info->irq < 0) {
|
||||
ret = -EINVAL;
|
||||
goto out7;
|
||||
}
|
||||
|
||||
ret = request_irq(info->irq, bfin_t350mcqb_irq_error, 0,
|
||||
"PPI ERROR", info);
|
||||
if (ret < 0) {
|
||||
printk(KERN_ERR DRIVER_NAME
|
||||
": unable to request PPI ERROR IRQ\n");
|
||||
goto out7;
|
||||
}
|
||||
|
||||
if (register_framebuffer(fbinfo) < 0) {
|
||||
printk(KERN_ERR DRIVER_NAME
|
||||
": unable to register framebuffer.\n");
|
||||
ret = -EINVAL;
|
||||
goto out8;
|
||||
}
|
||||
#ifndef NO_BL_SUPPORT
|
||||
memset(&props, 0, sizeof(struct backlight_properties));
|
||||
props.type = BACKLIGHT_RAW;
|
||||
props.max_brightness = 255;
|
||||
bl_dev = backlight_device_register("bf52x-bl", NULL, NULL,
|
||||
&bfin_lq043fb_bl_ops, &props);
|
||||
if (IS_ERR(bl_dev)) {
|
||||
printk(KERN_ERR DRIVER_NAME
|
||||
": unable to register backlight.\n");
|
||||
ret = -EINVAL;
|
||||
unregister_framebuffer(fbinfo);
|
||||
goto out8;
|
||||
}
|
||||
|
||||
lcd_dev = lcd_device_register(DRIVER_NAME, NULL, &bfin_lcd_ops);
|
||||
lcd_dev->props.max_contrast = 255, printk(KERN_INFO "Done.\n");
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
|
||||
out8:
|
||||
free_irq(info->irq, info);
|
||||
out7:
|
||||
bfin_t350mcqb_request_ports(0);
|
||||
out6:
|
||||
fb_dealloc_cmap(&fbinfo->cmap);
|
||||
out4:
|
||||
dma_free_coherent(NULL, fbinfo->fix.smem_len + ACTIVE_VIDEO_MEM_OFFSET,
|
||||
info->fb_buffer, info->dma_handle);
|
||||
out3:
|
||||
framebuffer_release(fbinfo);
|
||||
out2:
|
||||
free_dma(CH_PPI);
|
||||
out1:
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int bfin_t350mcqb_remove(struct platform_device *pdev)
|
||||
{
|
||||
|
||||
struct fb_info *fbinfo = platform_get_drvdata(pdev);
|
||||
struct bfin_t350mcqbfb_info *info = fbinfo->par;
|
||||
|
||||
unregister_framebuffer(fbinfo);
|
||||
|
||||
free_dma(CH_PPI);
|
||||
free_irq(info->irq, info);
|
||||
|
||||
if (info->fb_buffer != NULL)
|
||||
dma_free_coherent(NULL, fbinfo->fix.smem_len +
|
||||
ACTIVE_VIDEO_MEM_OFFSET, info->fb_buffer,
|
||||
info->dma_handle);
|
||||
|
||||
fb_dealloc_cmap(&fbinfo->cmap);
|
||||
|
||||
#ifndef NO_BL_SUPPORT
|
||||
lcd_device_unregister(lcd_dev);
|
||||
backlight_device_unregister(bl_dev);
|
||||
#endif
|
||||
|
||||
bfin_t350mcqb_request_ports(0);
|
||||
|
||||
framebuffer_release(fbinfo);
|
||||
|
||||
printk(KERN_INFO DRIVER_NAME ": Unregister LCD driver.\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int bfin_t350mcqb_suspend(struct platform_device *pdev, pm_message_t state)
|
||||
{
|
||||
struct fb_info *fbinfo = platform_get_drvdata(pdev);
|
||||
struct bfin_t350mcqbfb_info *fbi = fbinfo->par;
|
||||
|
||||
if (fbi->lq043_open_cnt) {
|
||||
bfin_t350mcqb_disable_ppi();
|
||||
disable_dma(CH_PPI);
|
||||
bfin_t350mcqb_stop_timers();
|
||||
bfin_write_PPI_STATUS(-1);
|
||||
}
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_t350mcqb_resume(struct platform_device *pdev)
|
||||
{
|
||||
struct fb_info *fbinfo = platform_get_drvdata(pdev);
|
||||
struct bfin_t350mcqbfb_info *fbi = fbinfo->par;
|
||||
|
||||
if (fbi->lq043_open_cnt) {
|
||||
bfin_t350mcqb_config_dma(fbi);
|
||||
bfin_t350mcqb_config_ppi(fbi);
|
||||
bfin_t350mcqb_init_timers();
|
||||
|
||||
/* start dma */
|
||||
enable_dma(CH_PPI);
|
||||
bfin_t350mcqb_enable_ppi();
|
||||
bfin_t350mcqb_start_timers();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
#define bfin_t350mcqb_suspend NULL
|
||||
#define bfin_t350mcqb_resume NULL
|
||||
#endif
|
||||
|
||||
static struct platform_driver bfin_t350mcqb_driver = {
|
||||
.probe = bfin_t350mcqb_probe,
|
||||
.remove = bfin_t350mcqb_remove,
|
||||
.suspend = bfin_t350mcqb_suspend,
|
||||
.resume = bfin_t350mcqb_resume,
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
},
|
||||
};
|
||||
module_platform_driver(bfin_t350mcqb_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Blackfin TFT LCD Driver");
|
||||
MODULE_LICENSE("GPL");
|
|
@ -1,828 +0,0 @@
|
|||
/*
|
||||
* Frame buffer driver for ADV7393/2 video encoder
|
||||
*
|
||||
* Copyright 2006-2009 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or late.
|
||||
*/
|
||||
|
||||
/*
|
||||
* TODO: Remove Globals
|
||||
* TODO: Code Cleanup
|
||||
*/
|
||||
|
||||
#define DRIVER_NAME "bfin-adv7393"
|
||||
|
||||
#define pr_fmt(fmt) DRIVER_NAME ": " fmt
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/tty.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/fb.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/sched.h>
|
||||
#include <asm/blackfin.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/dma.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <asm/portmux.h>
|
||||
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/proc_fs.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/i2c.h>
|
||||
|
||||
#include "bfin_adv7393fb.h"
|
||||
|
||||
static int mode = VMODE;
|
||||
static int mem = VMEM;
|
||||
static int nocursor = 1;
|
||||
|
||||
static const unsigned short ppi_pins[] = {
|
||||
P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
|
||||
P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
|
||||
P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
|
||||
P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
|
||||
P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
|
||||
0
|
||||
};
|
||||
|
||||
/*
|
||||
* card parameters
|
||||
*/
|
||||
|
||||
static struct bfin_adv7393_fb_par {
|
||||
/* structure holding blackfin / adv7393 parameters when
|
||||
screen is blanked */
|
||||
struct {
|
||||
u8 Mode; /* ntsc/pal/? */
|
||||
} vga_state;
|
||||
atomic_t ref_count;
|
||||
} bfin_par;
|
||||
|
||||
/* --------------------------------------------------------------------- */
|
||||
|
||||
static struct fb_var_screeninfo bfin_adv7393_fb_defined = {
|
||||
.xres = 720,
|
||||
.yres = 480,
|
||||
.xres_virtual = 720,
|
||||
.yres_virtual = 480,
|
||||
.bits_per_pixel = 16,
|
||||
.activate = FB_ACTIVATE_TEST,
|
||||
.height = -1,
|
||||
.width = -1,
|
||||
.left_margin = 0,
|
||||
.right_margin = 0,
|
||||
.upper_margin = 0,
|
||||
.lower_margin = 0,
|
||||
.vmode = FB_VMODE_INTERLACED,
|
||||
.red = {11, 5, 0},
|
||||
.green = {5, 6, 0},
|
||||
.blue = {0, 5, 0},
|
||||
.transp = {0, 0, 0},
|
||||
};
|
||||
|
||||
static struct fb_fix_screeninfo bfin_adv7393_fb_fix = {
|
||||
.id = "BFIN ADV7393",
|
||||
.smem_len = 720 * 480 * 2,
|
||||
.type = FB_TYPE_PACKED_PIXELS,
|
||||
.visual = FB_VISUAL_TRUECOLOR,
|
||||
.xpanstep = 0,
|
||||
.ypanstep = 0,
|
||||
.line_length = 720 * 2,
|
||||
.accel = FB_ACCEL_NONE
|
||||
};
|
||||
|
||||
static struct fb_ops bfin_adv7393_fb_ops = {
|
||||
.owner = THIS_MODULE,
|
||||
.fb_open = bfin_adv7393_fb_open,
|
||||
.fb_release = bfin_adv7393_fb_release,
|
||||
.fb_check_var = bfin_adv7393_fb_check_var,
|
||||
.fb_pan_display = bfin_adv7393_fb_pan_display,
|
||||
.fb_blank = bfin_adv7393_fb_blank,
|
||||
.fb_fillrect = cfb_fillrect,
|
||||
.fb_copyarea = cfb_copyarea,
|
||||
.fb_imageblit = cfb_imageblit,
|
||||
.fb_cursor = bfin_adv7393_fb_cursor,
|
||||
.fb_setcolreg = bfin_adv7393_fb_setcolreg,
|
||||
};
|
||||
|
||||
static int dma_desc_list(struct adv7393fb_device *fbdev, u16 arg)
|
||||
{
|
||||
if (arg == BUILD) { /* Build */
|
||||
fbdev->vb1 = l1_data_sram_zalloc(sizeof(struct dmasg));
|
||||
if (fbdev->vb1 == NULL)
|
||||
goto error;
|
||||
|
||||
fbdev->av1 = l1_data_sram_zalloc(sizeof(struct dmasg));
|
||||
if (fbdev->av1 == NULL)
|
||||
goto error;
|
||||
|
||||
fbdev->vb2 = l1_data_sram_zalloc(sizeof(struct dmasg));
|
||||
if (fbdev->vb2 == NULL)
|
||||
goto error;
|
||||
|
||||
fbdev->av2 = l1_data_sram_zalloc(sizeof(struct dmasg));
|
||||
if (fbdev->av2 == NULL)
|
||||
goto error;
|
||||
|
||||
/* Build linked DMA descriptor list */
|
||||
fbdev->vb1->next_desc_addr = fbdev->av1;
|
||||
fbdev->av1->next_desc_addr = fbdev->vb2;
|
||||
fbdev->vb2->next_desc_addr = fbdev->av2;
|
||||
fbdev->av2->next_desc_addr = fbdev->vb1;
|
||||
|
||||
/* Save list head */
|
||||
fbdev->descriptor_list_head = fbdev->av2;
|
||||
|
||||
/* Vertical Blanking Field 1 */
|
||||
fbdev->vb1->start_addr = VB_DUMMY_MEMORY_SOURCE;
|
||||
fbdev->vb1->cfg = DMA_CFG_VAL;
|
||||
|
||||
fbdev->vb1->x_count =
|
||||
fbdev->modes[mode].xres + fbdev->modes[mode].boeft_blank;
|
||||
|
||||
fbdev->vb1->x_modify = 0;
|
||||
fbdev->vb1->y_count = fbdev->modes[mode].vb1_lines;
|
||||
fbdev->vb1->y_modify = 0;
|
||||
|
||||
/* Active Video Field 1 */
|
||||
|
||||
fbdev->av1->start_addr = (unsigned long)fbdev->fb_mem;
|
||||
fbdev->av1->cfg = DMA_CFG_VAL;
|
||||
fbdev->av1->x_count =
|
||||
fbdev->modes[mode].xres + fbdev->modes[mode].boeft_blank;
|
||||
fbdev->av1->x_modify = fbdev->modes[mode].bpp / 8;
|
||||
fbdev->av1->y_count = fbdev->modes[mode].a_lines;
|
||||
fbdev->av1->y_modify =
|
||||
(fbdev->modes[mode].xres - fbdev->modes[mode].boeft_blank +
|
||||
1) * (fbdev->modes[mode].bpp / 8);
|
||||
|
||||
/* Vertical Blanking Field 2 */
|
||||
|
||||
fbdev->vb2->start_addr = VB_DUMMY_MEMORY_SOURCE;
|
||||
fbdev->vb2->cfg = DMA_CFG_VAL;
|
||||
fbdev->vb2->x_count =
|
||||
fbdev->modes[mode].xres + fbdev->modes[mode].boeft_blank;
|
||||
|
||||
fbdev->vb2->x_modify = 0;
|
||||
fbdev->vb2->y_count = fbdev->modes[mode].vb2_lines;
|
||||
fbdev->vb2->y_modify = 0;
|
||||
|
||||
/* Active Video Field 2 */
|
||||
|
||||
fbdev->av2->start_addr =
|
||||
(unsigned long)fbdev->fb_mem + fbdev->line_len;
|
||||
|
||||
fbdev->av2->cfg = DMA_CFG_VAL;
|
||||
|
||||
fbdev->av2->x_count =
|
||||
fbdev->modes[mode].xres + fbdev->modes[mode].boeft_blank;
|
||||
|
||||
fbdev->av2->x_modify = (fbdev->modes[mode].bpp / 8);
|
||||
fbdev->av2->y_count = fbdev->modes[mode].a_lines;
|
||||
|
||||
fbdev->av2->y_modify =
|
||||
(fbdev->modes[mode].xres - fbdev->modes[mode].boeft_blank +
|
||||
1) * (fbdev->modes[mode].bpp / 8);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
error:
|
||||
l1_data_sram_free(fbdev->vb1);
|
||||
l1_data_sram_free(fbdev->av1);
|
||||
l1_data_sram_free(fbdev->vb2);
|
||||
l1_data_sram_free(fbdev->av2);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_config_dma(struct adv7393fb_device *fbdev)
|
||||
{
|
||||
BUG_ON(!(fbdev->fb_mem));
|
||||
|
||||
set_dma_x_count(CH_PPI, fbdev->descriptor_list_head->x_count);
|
||||
set_dma_x_modify(CH_PPI, fbdev->descriptor_list_head->x_modify);
|
||||
set_dma_y_count(CH_PPI, fbdev->descriptor_list_head->y_count);
|
||||
set_dma_y_modify(CH_PPI, fbdev->descriptor_list_head->y_modify);
|
||||
set_dma_start_addr(CH_PPI, fbdev->descriptor_list_head->start_addr);
|
||||
set_dma_next_desc_addr(CH_PPI,
|
||||
fbdev->descriptor_list_head->next_desc_addr);
|
||||
set_dma_config(CH_PPI, fbdev->descriptor_list_head->cfg);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void bfin_disable_dma(void)
|
||||
{
|
||||
bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() & ~DMAEN);
|
||||
}
|
||||
|
||||
static void bfin_config_ppi(struct adv7393fb_device *fbdev)
|
||||
{
|
||||
if (ANOMALY_05000183) {
|
||||
bfin_write_TIMER2_CONFIG(WDTH_CAP);
|
||||
bfin_write_TIMER_ENABLE(TIMEN2);
|
||||
}
|
||||
|
||||
bfin_write_PPI_CONTROL(0x381E);
|
||||
bfin_write_PPI_FRAME(fbdev->modes[mode].tot_lines);
|
||||
bfin_write_PPI_COUNT(fbdev->modes[mode].xres +
|
||||
fbdev->modes[mode].boeft_blank - 1);
|
||||
bfin_write_PPI_DELAY(fbdev->modes[mode].aoeft_blank - 1);
|
||||
}
|
||||
|
||||
static void bfin_enable_ppi(void)
|
||||
{
|
||||
bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
|
||||
}
|
||||
|
||||
static void bfin_disable_ppi(void)
|
||||
{
|
||||
bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN);
|
||||
}
|
||||
|
||||
static inline int adv7393_write(struct i2c_client *client, u8 reg, u8 value)
|
||||
{
|
||||
return i2c_smbus_write_byte_data(client, reg, value);
|
||||
}
|
||||
|
||||
static inline int adv7393_read(struct i2c_client *client, u8 reg)
|
||||
{
|
||||
return i2c_smbus_read_byte_data(client, reg);
|
||||
}
|
||||
|
||||
static int
|
||||
adv7393_write_block(struct i2c_client *client,
|
||||
const u8 *data, unsigned int len)
|
||||
{
|
||||
int ret = -1;
|
||||
u8 reg;
|
||||
|
||||
while (len >= 2) {
|
||||
reg = *data++;
|
||||
ret = adv7393_write(client, reg, *data++);
|
||||
if (ret < 0)
|
||||
break;
|
||||
len -= 2;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int adv7393_mode(struct i2c_client *client, u16 mode)
|
||||
{
|
||||
switch (mode) {
|
||||
case POWER_ON: /* ADV7393 Sleep mode OFF */
|
||||
adv7393_write(client, 0x00, 0x1E);
|
||||
break;
|
||||
case POWER_DOWN: /* ADV7393 Sleep mode ON */
|
||||
adv7393_write(client, 0x00, 0x1F);
|
||||
break;
|
||||
case BLANK_OFF: /* Pixel Data Valid */
|
||||
adv7393_write(client, 0x82, 0xCB);
|
||||
break;
|
||||
case BLANK_ON: /* Pixel Data Invalid */
|
||||
adv7393_write(client, 0x82, 0x8B);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static irqreturn_t ppi_irq_error(int irq, void *dev_id)
|
||||
{
|
||||
|
||||
struct adv7393fb_device *fbdev = (struct adv7393fb_device *)dev_id;
|
||||
|
||||
u16 status = bfin_read_PPI_STATUS();
|
||||
|
||||
pr_debug("%s: PPI Status = 0x%X\n", __func__, status);
|
||||
|
||||
if (status) {
|
||||
bfin_disable_dma(); /* TODO: Check Sequence */
|
||||
bfin_disable_ppi();
|
||||
bfin_clear_PPI_STATUS();
|
||||
bfin_config_dma(fbdev);
|
||||
bfin_enable_ppi();
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
|
||||
}
|
||||
|
||||
static int proc_output(char *buf)
|
||||
{
|
||||
char *p = buf;
|
||||
|
||||
p += sprintf(p,
|
||||
"Usage:\n"
|
||||
"echo 0x[REG][Value] > adv7393\n"
|
||||
"example: echo 0x1234 >adv7393\n"
|
||||
"writes 0x34 into Register 0x12\n");
|
||||
|
||||
return p - buf;
|
||||
}
|
||||
|
||||
static ssize_t
|
||||
adv7393_read_proc(struct file *file, char __user *buf,
|
||||
size_t size, loff_t *ppos)
|
||||
{
|
||||
static const char message[] = "Usage:\n"
|
||||
"echo 0x[REG][Value] > adv7393\n"
|
||||
"example: echo 0x1234 >adv7393\n"
|
||||
"writes 0x34 into Register 0x12\n";
|
||||
return simple_read_from_buffer(buf, size, ppos, message,
|
||||
sizeof(message));
|
||||
}
|
||||
|
||||
static ssize_t
|
||||
adv7393_write_proc(struct file *file, const char __user * buffer,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct adv7393fb_device *fbdev = PDE_DATA(file_inode(file));
|
||||
unsigned int val;
|
||||
int ret;
|
||||
|
||||
ret = kstrtouint_from_user(buffer, count, 0, &val);
|
||||
if (ret)
|
||||
return -EFAULT;
|
||||
|
||||
adv7393_write(fbdev->client, val >> 8, val & 0xff);
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
static const struct file_operations fops = {
|
||||
.read = adv7393_read_proc,
|
||||
.write = adv7393_write_proc,
|
||||
.llseek = default_llseek,
|
||||
};
|
||||
|
||||
static int bfin_adv7393_fb_probe(struct i2c_client *client,
|
||||
const struct i2c_device_id *id)
|
||||
{
|
||||
int ret = 0;
|
||||
struct proc_dir_entry *entry;
|
||||
|
||||
struct adv7393fb_device *fbdev = NULL;
|
||||
|
||||
if (mem > 2) {
|
||||
dev_err(&client->dev, "mem out of allowed range [1;2]\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (mode >= ARRAY_SIZE(known_modes)) {
|
||||
dev_err(&client->dev, "mode %d: not supported", mode);
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
fbdev = kzalloc(sizeof(*fbdev), GFP_KERNEL);
|
||||
if (!fbdev) {
|
||||
dev_err(&client->dev, "failed to allocate device private record");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
i2c_set_clientdata(client, fbdev);
|
||||
|
||||
fbdev->modes = known_modes;
|
||||
fbdev->client = client;
|
||||
|
||||
fbdev->fb_len =
|
||||
mem * fbdev->modes[mode].xres * fbdev->modes[mode].xres *
|
||||
(fbdev->modes[mode].bpp / 8);
|
||||
|
||||
fbdev->line_len =
|
||||
fbdev->modes[mode].xres * (fbdev->modes[mode].bpp / 8);
|
||||
|
||||
/* Workaround "PPI Does Not Start Properly In Specific Mode" */
|
||||
if (ANOMALY_05000400) {
|
||||
ret = gpio_request_one(P_IDENT(P_PPI0_FS3), GPIOF_OUT_INIT_LOW,
|
||||
"PPI0_FS3");
|
||||
if (ret) {
|
||||
dev_err(&client->dev, "PPI0_FS3 GPIO request failed\n");
|
||||
ret = -EBUSY;
|
||||
goto free_fbdev;
|
||||
}
|
||||
}
|
||||
|
||||
if (peripheral_request_list(ppi_pins, DRIVER_NAME)) {
|
||||
dev_err(&client->dev, "requesting PPI peripheral failed\n");
|
||||
ret = -EFAULT;
|
||||
goto free_gpio;
|
||||
}
|
||||
|
||||
fbdev->fb_mem =
|
||||
dma_alloc_coherent(NULL, fbdev->fb_len, &fbdev->dma_handle,
|
||||
GFP_KERNEL);
|
||||
|
||||
if (NULL == fbdev->fb_mem) {
|
||||
dev_err(&client->dev, "couldn't allocate dma buffer (%d bytes)\n",
|
||||
(u32) fbdev->fb_len);
|
||||
ret = -ENOMEM;
|
||||
goto free_ppi_pins;
|
||||
}
|
||||
|
||||
fbdev->info.screen_base = (void *)fbdev->fb_mem;
|
||||
bfin_adv7393_fb_fix.smem_start = (int)fbdev->fb_mem;
|
||||
|
||||
bfin_adv7393_fb_fix.smem_len = fbdev->fb_len;
|
||||
bfin_adv7393_fb_fix.line_length = fbdev->line_len;
|
||||
|
||||
if (mem > 1)
|
||||
bfin_adv7393_fb_fix.ypanstep = 1;
|
||||
|
||||
bfin_adv7393_fb_defined.red.length = 5;
|
||||
bfin_adv7393_fb_defined.green.length = 6;
|
||||
bfin_adv7393_fb_defined.blue.length = 5;
|
||||
|
||||
bfin_adv7393_fb_defined.xres = fbdev->modes[mode].xres;
|
||||
bfin_adv7393_fb_defined.yres = fbdev->modes[mode].yres;
|
||||
bfin_adv7393_fb_defined.xres_virtual = fbdev->modes[mode].xres;
|
||||
bfin_adv7393_fb_defined.yres_virtual = mem * fbdev->modes[mode].yres;
|
||||
bfin_adv7393_fb_defined.bits_per_pixel = fbdev->modes[mode].bpp;
|
||||
|
||||
fbdev->info.fbops = &bfin_adv7393_fb_ops;
|
||||
fbdev->info.var = bfin_adv7393_fb_defined;
|
||||
fbdev->info.fix = bfin_adv7393_fb_fix;
|
||||
fbdev->info.par = &bfin_par;
|
||||
fbdev->info.flags = FBINFO_DEFAULT;
|
||||
|
||||
fbdev->info.pseudo_palette = kzalloc(sizeof(u32) * 16, GFP_KERNEL);
|
||||
if (!fbdev->info.pseudo_palette) {
|
||||
dev_err(&client->dev, "failed to allocate pseudo_palette\n");
|
||||
ret = -ENOMEM;
|
||||
goto free_fb_mem;
|
||||
}
|
||||
|
||||
if (fb_alloc_cmap(&fbdev->info.cmap, BFIN_LCD_NBR_PALETTE_ENTRIES, 0) < 0) {
|
||||
dev_err(&client->dev, "failed to allocate colormap (%d entries)\n",
|
||||
BFIN_LCD_NBR_PALETTE_ENTRIES);
|
||||
ret = -EFAULT;
|
||||
goto free_palette;
|
||||
}
|
||||
|
||||
if (request_dma(CH_PPI, "BF5xx_PPI_DMA") < 0) {
|
||||
dev_err(&client->dev, "unable to request PPI DMA\n");
|
||||
ret = -EFAULT;
|
||||
goto free_cmap;
|
||||
}
|
||||
|
||||
if (request_irq(IRQ_PPI_ERROR, ppi_irq_error, 0,
|
||||
"PPI ERROR", fbdev) < 0) {
|
||||
dev_err(&client->dev, "unable to request PPI ERROR IRQ\n");
|
||||
ret = -EFAULT;
|
||||
goto free_ch_ppi;
|
||||
}
|
||||
|
||||
fbdev->open = 0;
|
||||
|
||||
ret = adv7393_write_block(client, fbdev->modes[mode].adv7393_i2c_initd,
|
||||
fbdev->modes[mode].adv7393_i2c_initd_len);
|
||||
|
||||
if (ret) {
|
||||
dev_err(&client->dev, "i2c attach: init error\n");
|
||||
goto free_irq_ppi;
|
||||
}
|
||||
|
||||
|
||||
if (register_framebuffer(&fbdev->info) < 0) {
|
||||
dev_err(&client->dev, "unable to register framebuffer\n");
|
||||
ret = -EFAULT;
|
||||
goto free_irq_ppi;
|
||||
}
|
||||
|
||||
dev_info(&client->dev, "fb%d: %s frame buffer device\n",
|
||||
fbdev->info.node, fbdev->info.fix.id);
|
||||
dev_info(&client->dev, "fb memory address : 0x%p\n", fbdev->fb_mem);
|
||||
|
||||
entry = proc_create_data("driver/adv7393", 0, NULL, &fops, fbdev);
|
||||
if (!entry) {
|
||||
dev_err(&client->dev, "unable to create /proc entry\n");
|
||||
ret = -EFAULT;
|
||||
goto free_fb;
|
||||
}
|
||||
return 0;
|
||||
|
||||
free_fb:
|
||||
unregister_framebuffer(&fbdev->info);
|
||||
free_irq_ppi:
|
||||
free_irq(IRQ_PPI_ERROR, fbdev);
|
||||
free_ch_ppi:
|
||||
free_dma(CH_PPI);
|
||||
free_cmap:
|
||||
fb_dealloc_cmap(&fbdev->info.cmap);
|
||||
free_palette:
|
||||
kfree(fbdev->info.pseudo_palette);
|
||||
free_fb_mem:
|
||||
dma_free_coherent(NULL, fbdev->fb_len, fbdev->fb_mem,
|
||||
fbdev->dma_handle);
|
||||
free_ppi_pins:
|
||||
peripheral_free_list(ppi_pins);
|
||||
free_gpio:
|
||||
if (ANOMALY_05000400)
|
||||
gpio_free(P_IDENT(P_PPI0_FS3));
|
||||
free_fbdev:
|
||||
kfree(fbdev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int bfin_adv7393_fb_open(struct fb_info *info, int user)
|
||||
{
|
||||
struct adv7393fb_device *fbdev = to_adv7393fb_device(info);
|
||||
|
||||
fbdev->info.screen_base = (void *)fbdev->fb_mem;
|
||||
if (!fbdev->info.screen_base) {
|
||||
dev_err(&fbdev->client->dev, "unable to map device\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
fbdev->open = 1;
|
||||
dma_desc_list(fbdev, BUILD);
|
||||
adv7393_mode(fbdev->client, BLANK_OFF);
|
||||
bfin_config_ppi(fbdev);
|
||||
bfin_config_dma(fbdev);
|
||||
bfin_enable_ppi();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_adv7393_fb_release(struct fb_info *info, int user)
|
||||
{
|
||||
struct adv7393fb_device *fbdev = to_adv7393fb_device(info);
|
||||
|
||||
adv7393_mode(fbdev->client, BLANK_ON);
|
||||
bfin_disable_dma();
|
||||
bfin_disable_ppi();
|
||||
dma_desc_list(fbdev, DESTRUCT);
|
||||
fbdev->open = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
bfin_adv7393_fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
|
||||
{
|
||||
|
||||
switch (var->bits_per_pixel) {
|
||||
case 16:/* DIRECTCOLOUR, 64k */
|
||||
var->red.offset = info->var.red.offset;
|
||||
var->green.offset = info->var.green.offset;
|
||||
var->blue.offset = info->var.blue.offset;
|
||||
var->red.length = info->var.red.length;
|
||||
var->green.length = info->var.green.length;
|
||||
var->blue.length = info->var.blue.length;
|
||||
var->transp.offset = 0;
|
||||
var->transp.length = 0;
|
||||
var->transp.msb_right = 0;
|
||||
var->red.msb_right = 0;
|
||||
var->green.msb_right = 0;
|
||||
var->blue.msb_right = 0;
|
||||
break;
|
||||
default:
|
||||
pr_debug("%s: depth not supported: %u BPP\n", __func__,
|
||||
var->bits_per_pixel);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (info->var.xres != var->xres ||
|
||||
info->var.yres != var->yres ||
|
||||
info->var.xres_virtual != var->xres_virtual ||
|
||||
info->var.yres_virtual != var->yres_virtual) {
|
||||
pr_debug("%s: Resolution not supported: X%u x Y%u\n",
|
||||
__func__, var->xres, var->yres);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Memory limit
|
||||
*/
|
||||
|
||||
if ((info->fix.line_length * var->yres_virtual) > info->fix.smem_len) {
|
||||
pr_debug("%s: Memory Limit requested yres_virtual = %u\n",
|
||||
__func__, var->yres_virtual);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
bfin_adv7393_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
|
||||
{
|
||||
int dy;
|
||||
u32 dmaaddr;
|
||||
struct adv7393fb_device *fbdev = to_adv7393fb_device(info);
|
||||
|
||||
if (!var || !info)
|
||||
return -EINVAL;
|
||||
|
||||
if (var->xoffset - info->var.xoffset) {
|
||||
/* No support for X panning for now! */
|
||||
return -EINVAL;
|
||||
}
|
||||
dy = var->yoffset - info->var.yoffset;
|
||||
|
||||
if (dy) {
|
||||
pr_debug("%s: Panning screen of %d lines\n", __func__, dy);
|
||||
|
||||
dmaaddr = fbdev->av1->start_addr;
|
||||
dmaaddr += (info->fix.line_length * dy);
|
||||
/* TODO: Wait for current frame to finished */
|
||||
|
||||
fbdev->av1->start_addr = (unsigned long)dmaaddr;
|
||||
fbdev->av2->start_addr = (unsigned long)dmaaddr + fbdev->line_len;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
/* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */
|
||||
static int bfin_adv7393_fb_blank(int blank, struct fb_info *info)
|
||||
{
|
||||
struct adv7393fb_device *fbdev = to_adv7393fb_device(info);
|
||||
|
||||
switch (blank) {
|
||||
|
||||
case VESA_NO_BLANKING:
|
||||
/* Turn on panel */
|
||||
adv7393_mode(fbdev->client, BLANK_OFF);
|
||||
break;
|
||||
|
||||
case VESA_VSYNC_SUSPEND:
|
||||
case VESA_HSYNC_SUSPEND:
|
||||
case VESA_POWERDOWN:
|
||||
/* Turn off panel */
|
||||
adv7393_mode(fbdev->client, BLANK_ON);
|
||||
break;
|
||||
|
||||
default:
|
||||
return -EINVAL;
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int bfin_adv7393_fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
|
||||
{
|
||||
if (nocursor)
|
||||
return 0;
|
||||
else
|
||||
return -EINVAL; /* just to force soft_cursor() call */
|
||||
}
|
||||
|
||||
static int bfin_adv7393_fb_setcolreg(u_int regno, u_int red, u_int green,
|
||||
u_int blue, u_int transp,
|
||||
struct fb_info *info)
|
||||
{
|
||||
if (regno >= BFIN_LCD_NBR_PALETTE_ENTRIES)
|
||||
return -EINVAL;
|
||||
|
||||
if (info->var.grayscale)
|
||||
/* grayscale = 0.30*R + 0.59*G + 0.11*B */
|
||||
red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
|
||||
|
||||
if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
|
||||
u32 value;
|
||||
/* Place color in the pseudopalette */
|
||||
if (regno > 16)
|
||||
return -EINVAL;
|
||||
|
||||
red >>= (16 - info->var.red.length);
|
||||
green >>= (16 - info->var.green.length);
|
||||
blue >>= (16 - info->var.blue.length);
|
||||
|
||||
value = (red << info->var.red.offset) |
|
||||
(green << info->var.green.offset)|
|
||||
(blue << info->var.blue.offset);
|
||||
value &= 0xFFFF;
|
||||
|
||||
((u32 *) (info->pseudo_palette))[regno] = value;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_adv7393_fb_remove(struct i2c_client *client)
|
||||
{
|
||||
struct adv7393fb_device *fbdev = i2c_get_clientdata(client);
|
||||
|
||||
adv7393_mode(client, POWER_DOWN);
|
||||
|
||||
if (fbdev->fb_mem)
|
||||
dma_free_coherent(NULL, fbdev->fb_len, fbdev->fb_mem, fbdev->dma_handle);
|
||||
free_dma(CH_PPI);
|
||||
free_irq(IRQ_PPI_ERROR, fbdev);
|
||||
unregister_framebuffer(&fbdev->info);
|
||||
remove_proc_entry("driver/adv7393", NULL);
|
||||
fb_dealloc_cmap(&fbdev->info.cmap);
|
||||
kfree(fbdev->info.pseudo_palette);
|
||||
|
||||
if (ANOMALY_05000400)
|
||||
gpio_free(P_IDENT(P_PPI0_FS3)); /* FS3 */
|
||||
peripheral_free_list(ppi_pins);
|
||||
kfree(fbdev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int bfin_adv7393_fb_suspend(struct device *dev)
|
||||
{
|
||||
struct adv7393fb_device *fbdev = dev_get_drvdata(dev);
|
||||
|
||||
if (fbdev->open) {
|
||||
bfin_disable_dma();
|
||||
bfin_disable_ppi();
|
||||
dma_desc_list(fbdev, DESTRUCT);
|
||||
}
|
||||
adv7393_mode(fbdev->client, POWER_DOWN);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_adv7393_fb_resume(struct device *dev)
|
||||
{
|
||||
struct adv7393fb_device *fbdev = dev_get_drvdata(dev);
|
||||
|
||||
adv7393_mode(fbdev->client, POWER_ON);
|
||||
|
||||
if (fbdev->open) {
|
||||
dma_desc_list(fbdev, BUILD);
|
||||
bfin_config_ppi(fbdev);
|
||||
bfin_config_dma(fbdev);
|
||||
bfin_enable_ppi();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops bfin_adv7393_dev_pm_ops = {
|
||||
.suspend = bfin_adv7393_fb_suspend,
|
||||
.resume = bfin_adv7393_fb_resume,
|
||||
};
|
||||
#endif
|
||||
|
||||
static const struct i2c_device_id bfin_adv7393_id[] = {
|
||||
{DRIVER_NAME, 0},
|
||||
{}
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(i2c, bfin_adv7393_id);
|
||||
|
||||
static struct i2c_driver bfin_adv7393_fb_driver = {
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
#ifdef CONFIG_PM
|
||||
.pm = &bfin_adv7393_dev_pm_ops,
|
||||
#endif
|
||||
},
|
||||
.probe = bfin_adv7393_fb_probe,
|
||||
.remove = bfin_adv7393_fb_remove,
|
||||
.id_table = bfin_adv7393_id,
|
||||
};
|
||||
|
||||
static int __init bfin_adv7393_fb_driver_init(void)
|
||||
{
|
||||
#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
|
||||
request_module("i2c-bfin-twi");
|
||||
#else
|
||||
request_module("i2c-gpio");
|
||||
#endif
|
||||
|
||||
return i2c_add_driver(&bfin_adv7393_fb_driver);
|
||||
}
|
||||
module_init(bfin_adv7393_fb_driver_init);
|
||||
|
||||
static void __exit bfin_adv7393_fb_driver_cleanup(void)
|
||||
{
|
||||
i2c_del_driver(&bfin_adv7393_fb_driver);
|
||||
}
|
||||
module_exit(bfin_adv7393_fb_driver_cleanup);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
|
||||
MODULE_DESCRIPTION("Frame buffer driver for ADV7393/2 Video Encoder");
|
||||
|
||||
module_param(mode, int, 0);
|
||||
MODULE_PARM_DESC(mode,
|
||||
"Video Mode (0=NTSC,1=PAL,2=NTSC 640x480,3=PAL 640x480,4=NTSC YCbCr input,5=PAL YCbCr input)");
|
||||
|
||||
module_param(mem, int, 0);
|
||||
MODULE_PARM_DESC(mem,
|
||||
"Size of frame buffer memory 1=Single 2=Double Size (allows y-panning / frame stacking)");
|
||||
|
||||
module_param(nocursor, int, 0644);
|
||||
MODULE_PARM_DESC(nocursor, "cursor enable/disable");
|
|
@ -1,319 +0,0 @@
|
|||
/*
|
||||
* Frame buffer driver for ADV7393/2 video encoder
|
||||
*
|
||||
* Copyright 2006-2009 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or late.
|
||||
*/
|
||||
|
||||
#ifndef __BFIN_ADV7393FB_H__
|
||||
#define __BFIN_ADV7393FB_H__
|
||||
|
||||
#define BFIN_LCD_NBR_PALETTE_ENTRIES 256
|
||||
|
||||
#ifdef CONFIG_NTSC
|
||||
# define VMODE 0
|
||||
#endif
|
||||
#ifdef CONFIG_PAL
|
||||
# define VMODE 1
|
||||
#endif
|
||||
#ifdef CONFIG_NTSC_640x480
|
||||
# define VMODE 2
|
||||
#endif
|
||||
#ifdef CONFIG_PAL_640x480
|
||||
# define VMODE 3
|
||||
#endif
|
||||
#ifdef CONFIG_NTSC_YCBCR
|
||||
# define VMODE 4
|
||||
#endif
|
||||
#ifdef CONFIG_PAL_YCBCR
|
||||
# define VMODE 5
|
||||
#endif
|
||||
|
||||
#ifndef VMODE
|
||||
# define VMODE 1
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ADV7393_2XMEM
|
||||
# define VMEM 2
|
||||
#else
|
||||
# define VMEM 1
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BF537) || defined(CONFIG_BF536) || defined(CONFIG_BF534)
|
||||
# define DMA_CFG_VAL 0x7935 /* Set Sync Bit */
|
||||
# define VB_DUMMY_MEMORY_SOURCE L1_DATA_B_START
|
||||
#else
|
||||
# define DMA_CFG_VAL 0x7915
|
||||
# define VB_DUMMY_MEMORY_SOURCE BOOT_ROM_START
|
||||
#endif
|
||||
|
||||
enum {
|
||||
DESTRUCT,
|
||||
BUILD,
|
||||
};
|
||||
|
||||
enum {
|
||||
POWER_ON,
|
||||
POWER_DOWN,
|
||||
BLANK_ON,
|
||||
BLANK_OFF,
|
||||
};
|
||||
|
||||
struct adv7393fb_modes {
|
||||
const s8 name[25]; /* Full name */
|
||||
u16 xres; /* Active Horizonzal Pixels */
|
||||
u16 yres; /* Active Vertical Pixels */
|
||||
u16 bpp;
|
||||
u16 vmode;
|
||||
u16 a_lines; /* Active Lines per Field */
|
||||
u16 vb1_lines; /* Vertical Blanking Field 1 Lines */
|
||||
u16 vb2_lines; /* Vertical Blanking Field 2 Lines */
|
||||
u16 tot_lines; /* Total Lines per Frame */
|
||||
u16 boeft_blank; /* Before Odd/Even Field Transition No. of Blank Pixels */
|
||||
u16 aoeft_blank; /* After Odd/Even Field Transition No. of Blank Pixels */
|
||||
const s8 *adv7393_i2c_initd;
|
||||
u16 adv7393_i2c_initd_len;
|
||||
};
|
||||
|
||||
static const u8 init_NTSC_TESTPATTERN[] = {
|
||||
0x00, 0x1E, /* Power up all DACs and PLL */
|
||||
0x01, 0x00, /* SD-Only Mode */
|
||||
0x80, 0x10, /* SSAF Luma Filter Enabled, NTSC Mode */
|
||||
0x82, 0xCB, /* Step control on, pixel data valid, pedestal on, PrPb SSAF on, CVBS/YC output */
|
||||
0x84, 0x40, /* SD Color Bar Test Pattern Enabled, DAC 2 = Luma, DAC 3 = Chroma */
|
||||
};
|
||||
|
||||
static const u8 init_NTSC[] = {
|
||||
0x00, 0x1E, /* Power up all DACs and PLL */
|
||||
0xC3, 0x26, /* Program RGB->YCrCb Color Space conversion matrix */
|
||||
0xC5, 0x12, /* Program RGB->YCrCb Color Space conversion matrix */
|
||||
0xC2, 0x4A, /* Program RGB->YCrCb Color Space conversion matrix */
|
||||
0xC6, 0x5E, /* Program RGB->YCrCb Color Space conversion matrix */
|
||||
0xBD, 0x19, /* Program RGB->YCrCb Color Space conversion matrix */
|
||||
0xBF, 0x42, /* Program RGB->YCrCb Color Space conversion matrix */
|
||||
0x8C, 0x1F, /* NTSC Subcarrier Frequency */
|
||||
0x8D, 0x7C, /* NTSC Subcarrier Frequency */
|
||||
0x8E, 0xF0, /* NTSC Subcarrier Frequency */
|
||||
0x8F, 0x21, /* NTSC Subcarrier Frequency */
|
||||
0x01, 0x00, /* SD-Only Mode */
|
||||
0x80, 0x30, /* SSAF Luma Filter Enabled, NTSC Mode */
|
||||
0x82, 0x8B, /* Step control on, pixel data invalid, pedestal on, PrPb SSAF on, CVBS/YC output */
|
||||
0x87, 0x80, /* SD Color Bar Test Pattern Enabled, DAC 2 = Luma, DAC 3 = Chroma */
|
||||
0x86, 0x82,
|
||||
0x8B, 0x11,
|
||||
0x88, 0x20,
|
||||
0x8A, 0x0d,
|
||||
};
|
||||
|
||||
static const u8 init_PAL[] = {
|
||||
0x00, 0x1E, /* Power up all DACs and PLL */
|
||||
0xC3, 0x26, /* Program RGB->YCrCb Color Space conversion matrix */
|
||||
0xC5, 0x12, /* Program RGB->YCrCb Color Space conversion matrix */
|
||||
0xC2, 0x4A, /* Program RGB->YCrCb Color Space conversion matrix */
|
||||
0xC6, 0x5E, /* Program RGB->YCrCb Color Space conversion matrix */
|
||||
0xBD, 0x19, /* Program RGB->YCrCb Color Space conversion matrix */
|
||||
0xBF, 0x42, /* Program RGB->YCrCb Color Space conversion matrix */
|
||||
0x8C, 0xCB, /* PAL Subcarrier Frequency */
|
||||
0x8D, 0x8A, /* PAL Subcarrier Frequency */
|
||||
0x8E, 0x09, /* PAL Subcarrier Frequency */
|
||||
0x8F, 0x2A, /* PAL Subcarrier Frequency */
|
||||
0x01, 0x00, /* SD-Only Mode */
|
||||
0x80, 0x11, /* SSAF Luma Filter Enabled, PAL Mode */
|
||||
0x82, 0x8B, /* Step control on, pixel data invalid, pedestal on, PrPb SSAF on, CVBS/YC output */
|
||||
0x87, 0x80, /* SD Color Bar Test Pattern Enabled, DAC 2 = Luma, DAC 3 = Chroma */
|
||||
0x86, 0x82,
|
||||
0x8B, 0x11,
|
||||
0x88, 0x20,
|
||||
0x8A, 0x0d,
|
||||
};
|
||||
|
||||
static const u8 init_NTSC_YCbCr[] = {
|
||||
0x00, 0x1E, /* Power up all DACs and PLL */
|
||||
0x8C, 0x1F, /* NTSC Subcarrier Frequency */
|
||||
0x8D, 0x7C, /* NTSC Subcarrier Frequency */
|
||||
0x8E, 0xF0, /* NTSC Subcarrier Frequency */
|
||||
0x8F, 0x21, /* NTSC Subcarrier Frequency */
|
||||
0x01, 0x00, /* SD-Only Mode */
|
||||
0x80, 0x30, /* SSAF Luma Filter Enabled, NTSC Mode */
|
||||
0x82, 0x8B, /* Step control on, pixel data invalid, pedestal on, PrPb SSAF on, CVBS/YC output */
|
||||
0x87, 0x00, /* DAC 2 = Luma, DAC 3 = Chroma */
|
||||
0x86, 0x82,
|
||||
0x8B, 0x11,
|
||||
0x88, 0x08,
|
||||
0x8A, 0x0d,
|
||||
};
|
||||
|
||||
static const u8 init_PAL_YCbCr[] = {
|
||||
0x00, 0x1E, /* Power up all DACs and PLL */
|
||||
0x8C, 0xCB, /* PAL Subcarrier Frequency */
|
||||
0x8D, 0x8A, /* PAL Subcarrier Frequency */
|
||||
0x8E, 0x09, /* PAL Subcarrier Frequency */
|
||||
0x8F, 0x2A, /* PAL Subcarrier Frequency */
|
||||
0x01, 0x00, /* SD-Only Mode */
|
||||
0x80, 0x11, /* SSAF Luma Filter Enabled, PAL Mode */
|
||||
0x82, 0x8B, /* Step control on, pixel data invalid, pedestal on, PrPb SSAF on, CVBS/YC output */
|
||||
0x87, 0x00, /* DAC 2 = Luma, DAC 3 = Chroma */
|
||||
0x86, 0x82,
|
||||
0x8B, 0x11,
|
||||
0x88, 0x08,
|
||||
0x8A, 0x0d,
|
||||
};
|
||||
|
||||
static struct adv7393fb_modes known_modes[] = {
|
||||
/* NTSC 720x480 CRT */
|
||||
{
|
||||
.name = "NTSC 720x480",
|
||||
.xres = 720,
|
||||
.yres = 480,
|
||||
.bpp = 16,
|
||||
.vmode = FB_VMODE_INTERLACED,
|
||||
.a_lines = 240,
|
||||
.vb1_lines = 22,
|
||||
.vb2_lines = 23,
|
||||
.tot_lines = 525,
|
||||
.boeft_blank = 16,
|
||||
.aoeft_blank = 122,
|
||||
.adv7393_i2c_initd = init_NTSC,
|
||||
.adv7393_i2c_initd_len = sizeof(init_NTSC)
|
||||
},
|
||||
/* PAL 720x480 CRT */
|
||||
{
|
||||
.name = "PAL 720x576",
|
||||
.xres = 720,
|
||||
.yres = 576,
|
||||
.bpp = 16,
|
||||
.vmode = FB_VMODE_INTERLACED,
|
||||
.a_lines = 288,
|
||||
.vb1_lines = 24,
|
||||
.vb2_lines = 25,
|
||||
.tot_lines = 625,
|
||||
.boeft_blank = 12,
|
||||
.aoeft_blank = 132,
|
||||
.adv7393_i2c_initd = init_PAL,
|
||||
.adv7393_i2c_initd_len = sizeof(init_PAL)
|
||||
},
|
||||
/* NTSC 640x480 CRT Experimental */
|
||||
{
|
||||
.name = "NTSC 640x480",
|
||||
.xres = 640,
|
||||
.yres = 480,
|
||||
.bpp = 16,
|
||||
.vmode = FB_VMODE_INTERLACED,
|
||||
.a_lines = 240,
|
||||
.vb1_lines = 22,
|
||||
.vb2_lines = 23,
|
||||
.tot_lines = 525,
|
||||
.boeft_blank = 16 + 40,
|
||||
.aoeft_blank = 122 + 40,
|
||||
.adv7393_i2c_initd = init_NTSC,
|
||||
.adv7393_i2c_initd_len = sizeof(init_NTSC)
|
||||
},
|
||||
/* PAL 640x480 CRT Experimental */
|
||||
{
|
||||
.name = "PAL 640x480",
|
||||
.xres = 640,
|
||||
.yres = 480,
|
||||
.bpp = 16,
|
||||
.vmode = FB_VMODE_INTERLACED,
|
||||
.a_lines = 288 - 20,
|
||||
.vb1_lines = 24 + 20,
|
||||
.vb2_lines = 25 + 20,
|
||||
.tot_lines = 625,
|
||||
.boeft_blank = 12 + 40,
|
||||
.aoeft_blank = 132 + 40,
|
||||
.adv7393_i2c_initd = init_PAL,
|
||||
.adv7393_i2c_initd_len = sizeof(init_PAL)
|
||||
},
|
||||
/* NTSC 720x480 YCbCR */
|
||||
{
|
||||
.name = "NTSC 720x480 YCbCR",
|
||||
.xres = 720,
|
||||
.yres = 480,
|
||||
.bpp = 16,
|
||||
.vmode = FB_VMODE_INTERLACED,
|
||||
.a_lines = 240,
|
||||
.vb1_lines = 22,
|
||||
.vb2_lines = 23,
|
||||
.tot_lines = 525,
|
||||
.boeft_blank = 16,
|
||||
.aoeft_blank = 122,
|
||||
.adv7393_i2c_initd = init_NTSC_YCbCr,
|
||||
.adv7393_i2c_initd_len = sizeof(init_NTSC_YCbCr)
|
||||
},
|
||||
/* PAL 720x480 CRT */
|
||||
{
|
||||
.name = "PAL 720x576 YCbCR",
|
||||
.xres = 720,
|
||||
.yres = 576,
|
||||
.bpp = 16,
|
||||
.vmode = FB_VMODE_INTERLACED,
|
||||
.a_lines = 288,
|
||||
.vb1_lines = 24,
|
||||
.vb2_lines = 25,
|
||||
.tot_lines = 625,
|
||||
.boeft_blank = 12,
|
||||
.aoeft_blank = 132,
|
||||
.adv7393_i2c_initd = init_PAL_YCbCr,
|
||||
.adv7393_i2c_initd_len = sizeof(init_PAL_YCbCr)
|
||||
}
|
||||
};
|
||||
|
||||
struct adv7393fb_regs {
|
||||
|
||||
};
|
||||
|
||||
struct adv7393fb_device {
|
||||
struct fb_info info; /* FB driver info record */
|
||||
|
||||
struct i2c_client *client;
|
||||
|
||||
struct dmasg *descriptor_list_head;
|
||||
struct dmasg *vb1;
|
||||
struct dmasg *av1;
|
||||
struct dmasg *vb2;
|
||||
struct dmasg *av2;
|
||||
|
||||
dma_addr_t dma_handle;
|
||||
|
||||
struct fb_info bfin_adv7393_fb;
|
||||
|
||||
struct adv7393fb_modes *modes;
|
||||
|
||||
struct adv7393fb_regs *regs; /* Registers memory map */
|
||||
size_t regs_len;
|
||||
size_t fb_len;
|
||||
size_t line_len;
|
||||
u16 open;
|
||||
u16 *fb_mem; /* RGB Buffer */
|
||||
|
||||
};
|
||||
|
||||
#define to_adv7393fb_device(_info) \
|
||||
(_info ? container_of(_info, struct adv7393fb_device, info) : NULL);
|
||||
|
||||
static int bfin_adv7393_fb_open(struct fb_info *info, int user);
|
||||
static int bfin_adv7393_fb_release(struct fb_info *info, int user);
|
||||
static int bfin_adv7393_fb_check_var(struct fb_var_screeninfo *var,
|
||||
struct fb_info *info);
|
||||
|
||||
static int bfin_adv7393_fb_pan_display(struct fb_var_screeninfo *var,
|
||||
struct fb_info *info);
|
||||
|
||||
static int bfin_adv7393_fb_blank(int blank, struct fb_info *info);
|
||||
|
||||
static void bfin_config_ppi(struct adv7393fb_device *fbdev);
|
||||
static int bfin_config_dma(struct adv7393fb_device *fbdev);
|
||||
static void bfin_disable_dma(void);
|
||||
static void bfin_enable_ppi(void);
|
||||
static void bfin_disable_ppi(void);
|
||||
|
||||
static inline int adv7393_write(struct i2c_client *client, u8 reg, u8 value);
|
||||
static inline int adv7393_read(struct i2c_client *client, u8 reg);
|
||||
static int adv7393_write_block(struct i2c_client *client, const u8 *data,
|
||||
unsigned int len);
|
||||
|
||||
int bfin_adv7393_fb_cursor(struct fb_info *info, struct fb_cursor *cursor);
|
||||
static int bfin_adv7393_fb_setcolreg(u_int, u_int, u_int, u_int,
|
||||
u_int, struct fb_info *info);
|
||||
|
||||
#endif
|
|
@ -571,8 +571,7 @@ static inline struct apertures_struct *alloc_apertures(unsigned int max_num) {
|
|||
|
||||
#elif defined(__i386__) || defined(__alpha__) || defined(__x86_64__) || \
|
||||
defined(__hppa__) || defined(__sh__) || defined(__powerpc__) || \
|
||||
defined(__avr32__) || defined(__bfin__) || defined(__arm__) || \
|
||||
defined(__aarch64__)
|
||||
defined(__arm__) || defined(__aarch64__)
|
||||
|
||||
#define fb_readb __raw_readb
|
||||
#define fb_readw __raw_readw
|
||||
|
|
Loading…
Reference in a new issue