KVM: nVMX: Do not load EOI-exitmap while running L2
When L1 IOAPIC redirection-table is written, a request of KVM_REQ_SCAN_IOAPIC is set on all vCPUs. This is done such that all vCPUs will now recalc their IOAPIC handled vectors and load it to their EOI-exitmap. However, it could be that one of the vCPUs is currently running L2. In this case, load_eoi_exitmap() will be called which would write to vmcs02->eoi_exit_bitmap, which is wrong because vmcs02->eoi_exit_bitmap should always be equal to vmcs12->eoi_exit_bitmap. Furthermore, at this point KVM_REQ_SCAN_IOAPIC was already consumed and therefore we will never update vmcs01->eoi_exit_bitmap. This could lead to remote_irr of some IOAPIC level-triggered entry to remain set forever. Fix this issue by delaying the load of EOI-exitmap to when vCPU is running L1. One may wonder why not just delay entire KVM_REQ_SCAN_IOAPIC processing to when vCPU is running L1. This is done in order to handle correctly the case where LAPIC & IO-APIC of L1 is pass-throughed into L2. In this case, vmcs12->virtual_interrupt_delivery should be 0. In current nVMX implementation, that results in vmcs02->virtual_interrupt_delivery to also be 0. Thus, vmcs02->eoi_exit_bitmap is not used. Therefore, every L2 EOI cause a #VMExit into L0 (either on MSR_WRITE to x2APIC MSR or APIC_ACCESS/APIC_WRITE/EPT_MISCONFIG to APIC MMIO page). In order for such L2 EOI to be broadcasted, if needed, from LAPIC to IO-APIC, vcpu->arch.ioapic_handled_vectors must be updated while L2 is running. Therefore, patch makes sure to delay only the loading of EOI-exitmap but not the update of vcpu->arch.ioapic_handled_vectors. Reviewed-by: Arbel Moshe <arbel.moshe@oracle.com> Reviewed-by: Krish Sadhukhan <krish.sadhukhan@oracle.com> Signed-off-by: Liran Alon <liran.alon@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -73,6 +73,7 @@
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#define KVM_REQ_HV_RESET KVM_ARCH_REQ(20)
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#define KVM_REQ_HV_EXIT KVM_ARCH_REQ(21)
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#define KVM_REQ_HV_STIMER KVM_ARCH_REQ(22)
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#define KVM_REQ_LOAD_EOI_EXITMAP KVM_ARCH_REQ(23)
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#define CR0_RESERVED_BITS \
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(~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
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@ -498,6 +499,7 @@ struct kvm_vcpu_arch {
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u64 apic_base;
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struct kvm_lapic *apic; /* kernel irqchip context */
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bool apicv_active;
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bool load_eoi_exitmap_pending;
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DECLARE_BITMAP(ioapic_handled_vectors, 256);
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unsigned long apic_attention;
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int32_t apic_arb_prio;
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@ -93,6 +93,11 @@ static inline void enter_guest_mode(struct kvm_vcpu *vcpu)
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static inline void leave_guest_mode(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.hflags &= ~HF_GUEST_MASK;
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if (vcpu->arch.load_eoi_exitmap_pending) {
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vcpu->arch.load_eoi_exitmap_pending = false;
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kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
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}
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}
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static inline bool is_guest_mode(struct kvm_vcpu *vcpu)
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@ -7110,8 +7110,6 @@ void kvm_make_scan_ioapic_request(struct kvm *kvm)
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static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
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{
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u64 eoi_exit_bitmap[4];
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if (!kvm_apic_hw_enabled(vcpu->arch.apic))
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return;
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@ -7124,6 +7122,20 @@ static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
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kvm_x86_ops->sync_pir_to_irr(vcpu);
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kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
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}
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if (is_guest_mode(vcpu))
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vcpu->arch.load_eoi_exitmap_pending = true;
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else
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kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
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}
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static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
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{
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u64 eoi_exit_bitmap[4];
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if (!kvm_apic_hw_enabled(vcpu->arch.apic))
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return;
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bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
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vcpu_to_synic(vcpu)->vec_bitmap, 256);
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kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
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@ -7238,6 +7250,8 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
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}
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if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
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vcpu_scan_ioapic(vcpu);
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if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
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vcpu_load_eoi_exitmap(vcpu);
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if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
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kvm_vcpu_reload_apic_access_page(vcpu);
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if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
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