Merge branches 'pm-tools' and 'powercap'
* pm-tools: tools: cpupower: Fix error when running cpupower monitor tools/power turbostat: fix typo on DRAM column in Joules-mode cpupower: Do not change the frequency of offline cpu tools/power turbostat: fix parameter passing for forked command tools/power turbostat: dump CONFIG_TDP tools/power turbostat: cpu0 is no longer hard-coded, so update output tools/power turbostat: update turbostat(8) * powercap: powercap / RAPL: disable the 2nd power limit properly powercap / RAPL: Add support for Broadwell-H powercap / RAPL: Add support for Skylake H/S
This commit is contained in:
commit
e625ccec1f
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@ -170,6 +170,12 @@
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#define MSR_PP1_ENERGY_STATUS 0x00000641
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#define MSR_PP1_POLICY 0x00000642
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#define MSR_CONFIG_TDP_NOMINAL 0x00000648
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#define MSR_CONFIG_TDP_LEVEL_1 0x00000649
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#define MSR_CONFIG_TDP_LEVEL_2 0x0000064A
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#define MSR_CONFIG_TDP_CONTROL 0x0000064B
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#define MSR_TURBO_ACTIVATION_RATIO 0x0000064C
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#define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
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#define MSR_PKG_ANY_CORE_C0_RES 0x00000659
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#define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
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@ -1096,11 +1096,13 @@ static const struct x86_cpu_id rapl_ids[] __initconst = {
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RAPL_CPU(0x3f, rapl_defaults_hsw_server),/* Haswell servers */
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RAPL_CPU(0x4f, rapl_defaults_hsw_server),/* Broadwell servers */
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RAPL_CPU(0x45, rapl_defaults_core),/* Haswell ULT */
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RAPL_CPU(0x47, rapl_defaults_core),/* Broadwell-H */
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RAPL_CPU(0x4E, rapl_defaults_core),/* Skylake */
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RAPL_CPU(0x4C, rapl_defaults_cht),/* Braswell/Cherryview */
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RAPL_CPU(0x4A, rapl_defaults_tng),/* Tangier */
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RAPL_CPU(0x56, rapl_defaults_core),/* Future Xeon */
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RAPL_CPU(0x5A, rapl_defaults_ann),/* Annidale */
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RAPL_CPU(0x5E, rapl_defaults_core),/* Skylake-H/S */
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RAPL_CPU(0x57, rapl_defaults_hsw_server),/* Knights Landing */
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{}
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};
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@ -1145,9 +1147,11 @@ static int rapl_unregister_powercap(void)
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pr_debug("remove package, undo power limit on %d: %s\n",
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rp->id, rd->name);
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rapl_write_data_raw(rd, PL1_ENABLE, 0);
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rapl_write_data_raw(rd, PL2_ENABLE, 0);
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rapl_write_data_raw(rd, PL1_CLAMP, 0);
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rapl_write_data_raw(rd, PL2_CLAMP, 0);
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if (find_nr_power_limit(rd) > 1) {
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rapl_write_data_raw(rd, PL2_ENABLE, 0);
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rapl_write_data_raw(rd, PL2_CLAMP, 0);
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}
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if (rd->id == RAPL_DOMAIN_PACKAGE) {
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rd_package = rd;
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continue;
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@ -17,6 +17,7 @@
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#include "cpufreq.h"
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#include "helpers/helpers.h"
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#include "helpers/sysfs.h"
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#define NORM_FREQ_LEN 32
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@ -318,6 +319,9 @@ int cmd_freq_set(int argc, char **argv)
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cpufreq_cpu_exists(cpu))
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continue;
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if (sysfs_is_cpu_online(cpu) != 1)
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continue;
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printf(_("Setting cpu: %d\n"), cpu);
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ret = do_one_cpu(cpu, &new_pol, freq, policychange);
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if (ret) {
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@ -73,6 +73,8 @@ int get_cpu_topology(struct cpupower_topology *cpu_top)
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for (cpu = 0; cpu < cpus; cpu++) {
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cpu_top->core_info[cpu].cpu = cpu;
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cpu_top->core_info[cpu].is_online = sysfs_is_cpu_online(cpu);
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if (!cpu_top->core_info[cpu].is_online)
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continue;
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if(sysfs_topology_read_file(
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cpu,
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"physical_package_id",
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@ -251,11 +251,6 @@ Although it is not guaranteed by the architecture, turbostat assumes
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that they count at TSC rate, which is true on all processors tested to date.
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.SH REFERENCES
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"Intel® Turbo Boost Technology
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in Intel® Core™ Microarchitecture (Nehalem) Based Processors"
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http://download.intel.com/design/processor/applnots/320354.pdf
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"Intel® 64 and IA-32 Architectures Software Developer's Manual
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Volume 3B: System Programming Guide"
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http://www.intel.com/products/processor/manuals/
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@ -372,7 +372,7 @@ void print_header(void)
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if (do_rapl & RAPL_GFX)
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outp += sprintf(outp, " GFX_J");
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if (do_rapl & RAPL_DRAM)
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outp += sprintf(outp, " RAM_W");
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outp += sprintf(outp, " RAM_J");
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if (do_rapl & RAPL_PKG_PERF_STATUS)
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outp += sprintf(outp, " PKG_%%");
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if (do_rapl & RAPL_DRAM_PERF_STATUS)
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@ -1157,7 +1157,7 @@ dump_nhm_platform_info(void)
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get_msr(base_cpu, MSR_NHM_PLATFORM_INFO, &msr);
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fprintf(stderr, "cpu0: MSR_NHM_PLATFORM_INFO: 0x%08llx\n", msr);
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fprintf(stderr, "cpu%d: MSR_NHM_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr);
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ratio = (msr >> 40) & 0xFF;
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fprintf(stderr, "%d * %.0f = %.0f MHz max efficiency frequency\n",
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@ -1168,8 +1168,8 @@ dump_nhm_platform_info(void)
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ratio, bclk, ratio * bclk);
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get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr);
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fprintf(stderr, "cpu0: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n",
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msr, msr & 0x2 ? "EN" : "DIS");
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fprintf(stderr, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n",
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base_cpu, msr, msr & 0x2 ? "EN" : "DIS");
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return;
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}
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@ -1182,7 +1182,7 @@ dump_hsw_turbo_ratio_limits(void)
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get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr);
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fprintf(stderr, "cpu0: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", msr);
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fprintf(stderr, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr);
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ratio = (msr >> 8) & 0xFF;
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if (ratio)
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@ -1204,7 +1204,7 @@ dump_ivt_turbo_ratio_limits(void)
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get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr);
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fprintf(stderr, "cpu0: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", msr);
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fprintf(stderr, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr);
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ratio = (msr >> 56) & 0xFF;
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if (ratio)
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@ -1256,7 +1256,7 @@ dump_nhm_turbo_ratio_limits(void)
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get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
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fprintf(stderr, "cpu0: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", msr);
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fprintf(stderr, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr);
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ratio = (msr >> 56) & 0xFF;
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if (ratio)
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@ -1312,8 +1312,8 @@ dump_knl_turbo_ratio_limits(void)
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get_msr(base_cpu, MSR_NHM_TURBO_RATIO_LIMIT, &msr);
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fprintf(stderr, "cpu0: MSR_NHM_TURBO_RATIO_LIMIT: 0x%08llx\n",
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msr);
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fprintf(stderr, "cpu%d: MSR_NHM_TURBO_RATIO_LIMIT: 0x%08llx\n",
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base_cpu, msr);
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/**
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* Turbo encoding in KNL is as follows:
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@ -1371,7 +1371,7 @@ dump_nhm_cst_cfg(void)
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#define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
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#define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
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fprintf(stderr, "cpu0: MSR_NHM_SNB_PKG_CST_CFG_CTL: 0x%08llx", msr);
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fprintf(stderr, "cpu%d: MSR_NHM_SNB_PKG_CST_CFG_CTL: 0x%08llx", base_cpu, msr);
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fprintf(stderr, " (%s%s%s%s%slocked: pkg-cstate-limit=%d: %s)\n",
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(msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "",
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@ -1384,6 +1384,49 @@ dump_nhm_cst_cfg(void)
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return;
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}
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static void
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dump_config_tdp(void)
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{
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unsigned long long msr;
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get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr);
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fprintf(stderr, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr);
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fprintf(stderr, " (base_ratio=%d)\n", (unsigned int)msr & 0xEF);
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get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr);
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fprintf(stderr, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr);
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if (msr) {
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fprintf(stderr, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0xEFFF);
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fprintf(stderr, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0xEFFF);
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fprintf(stderr, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xEF);
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fprintf(stderr, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0xEFFF);
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}
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fprintf(stderr, ")\n");
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get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr);
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fprintf(stderr, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr);
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if (msr) {
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fprintf(stderr, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0xEFFF);
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fprintf(stderr, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0xEFFF);
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fprintf(stderr, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xEF);
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fprintf(stderr, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0xEFFF);
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}
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fprintf(stderr, ")\n");
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get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr);
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fprintf(stderr, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr);
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if ((msr) & 0x3)
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fprintf(stderr, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3);
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fprintf(stderr, " lock=%d", (unsigned int)(msr >> 31) & 1);
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fprintf(stderr, ")\n");
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get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr);
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fprintf(stderr, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr);
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fprintf(stderr, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xEF);
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fprintf(stderr, " lock=%d", (unsigned int)(msr >> 31) & 1);
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fprintf(stderr, ")\n");
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}
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void free_all_buffers(void)
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{
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CPU_FREE(cpu_present_set);
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return 0;
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}
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}
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int has_config_tdp(unsigned int family, unsigned int model)
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{
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if (!genuine_intel)
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return 0;
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if (family != 6)
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return 0;
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switch (model) {
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case 0x3A: /* IVB */
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case 0x3E: /* IVB Xeon */
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case 0x3C: /* HSW */
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case 0x3F: /* HSX */
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case 0x45: /* HSW */
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case 0x46: /* HSW */
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case 0x3D: /* BDW */
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case 0x47: /* BDW */
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case 0x4F: /* BDX */
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case 0x56: /* BDX-DE */
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case 0x4E: /* SKL */
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case 0x5E: /* SKL */
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case 0x57: /* Knights Landing */
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return 1;
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default:
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return 0;
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}
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}
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static void
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dump_cstate_pstate_config_info(family, model)
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{
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if (has_knl_turbo_ratio_limit(family, model))
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dump_knl_turbo_ratio_limits();
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if (has_config_tdp(family, model))
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dump_config_tdp();
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dump_nhm_cst_cfg();
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}
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@ -3014,7 +3090,7 @@ int get_and_dump_counters(void)
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}
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void print_version() {
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fprintf(stderr, "turbostat version 4.7 27-May, 2015"
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fprintf(stderr, "turbostat version 4.7 17-June, 2015"
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" - Len Brown <lenb@kernel.org>\n");
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}
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@ -3042,7 +3118,7 @@ void cmdline(int argc, char **argv)
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progname = argv[0];
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while ((opt = getopt_long_only(argc, argv, "C:c:Ddhi:JM:m:PpST:v",
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while ((opt = getopt_long_only(argc, argv, "+C:c:Ddhi:JM:m:PpST:v",
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long_options, &option_index)) != -1) {
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switch (opt) {
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case 'C':
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