ARM: dts: keystone-k2hk: Add PSC reset controller node
The Power Sleep Controller (PSC) module contains specific memory-mapped registers that can be used to perform reset management using specific bits for the DSPs available on the SoC. The PSC is defined using a syscon node, and the reset functionality is defined using a child syscon reset controller node. Add this syscon reset controller node as well as the reset control data for the resets it supports for the 66AK2H SoCs. Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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@ -8,6 +8,8 @@
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* published by the Free Software Foundation.
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*/
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#include <dt-bindings/reset/ti-syscon.h>
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/ {
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compatible = "ti,k2hk", "ti,keystone";
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model = "Texas Instruments Keystone 2 Kepler/Hawking SoC";
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@ -58,6 +60,24 @@
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};
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};
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psc: power-sleep-controller@02350000 {
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pscrst: reset-controller {
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compatible = "ti,k2hk-pscrst", "ti,syscon-reset";
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#reset-cells = <1>;
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ti,reset-bits = <
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0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */
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0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */
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0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */
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0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */
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0xa4c 8 0xa4c 8 0x84c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 4: dsp4 */
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0xa50 8 0xa50 8 0x850 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 5: dsp5 */
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0xa54 8 0xa54 8 0x854 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 6: dsp6 */
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0xa58 8 0xa58 8 0x858 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 7: dsp7 */
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>;
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};
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};
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dspgpio0: keystone_dsp_gpio@02620240 {
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compatible = "ti,keystone-dsp-gpio";
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gpio-controller;
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