drm/i915: Differentiate between sw write location into ring and last hw read
We need to keep track of the last location we ask the hw to read up to (RING_TAIL) separately from our last write location into the ring, so that in the event of a GPU reset we do not tell the HW to proceed into a partially written request (which can happen if that request is waiting for an external signal before being executed). v2: Refactor intel_ring_reset() (Mika) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100144 Testcase: igt/gem_exec_fence/await-hang Fixes:821ed7df6e
("drm/i915: Update reset path to fix incomplete requests") Fixes:d55ac5bf97
("drm/i915: Defer transfer onto execution timeline to actual hw submission") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170425130049.26147-1-chris@chris-wilson.co.uk Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
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@ -283,10 +283,18 @@ static void advance_ring(struct drm_i915_gem_request *request)
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* Note this requires that we are always called in request
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* completion order.
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*/
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if (list_is_last(&request->ring_link, &request->ring->request_list))
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tail = request->ring->tail;
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else
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if (list_is_last(&request->ring_link, &request->ring->request_list)) {
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/* We may race here with execlists resubmitting this request
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* as we retire it. The resubmission will move the ring->tail
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* forwards (to request->wa_tail). We either read the
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* current value that was written to hw, or the value that
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* is just about to be. Either works, if we miss the last two
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* noops - they are safe to be replayed on a reset.
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*/
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tail = READ_ONCE(request->ring->tail);
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} else {
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tail = request->postfix;
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}
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list_del(&request->ring_link);
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request->ring->head = tail;
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@ -651,7 +659,7 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
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* GPU processing the request, we never over-estimate the
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* position of the head.
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*/
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req->head = req->ring->tail;
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req->head = req->ring->emit;
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/* Check that we didn't interrupt ourselves with a new request */
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GEM_BUG_ON(req->timeline->seqno != req->fence.seqno);
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@ -480,9 +480,7 @@ static void guc_wq_item_append(struct i915_guc_client *client,
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GEM_BUG_ON(freespace < wqi_size);
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/* The GuC firmware wants the tail index in QWords, not bytes */
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tail = rq->tail;
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assert_ring_tail_valid(rq->ring, rq->tail);
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tail >>= 3;
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tail = intel_ring_set_tail(rq->ring, rq->tail) >> 3;
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GEM_BUG_ON(tail > WQ_RING_TAIL_MAX);
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/* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
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@ -326,8 +326,7 @@ static u64 execlists_update_context(struct drm_i915_gem_request *rq)
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rq->ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
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u32 *reg_state = ce->lrc_reg_state;
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assert_ring_tail_valid(rq->ring, rq->tail);
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reg_state[CTX_RING_TAIL+1] = rq->tail;
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reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
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/* True 32b PPGTT with dynamic page allocation: update PDP
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* registers and point the unallocated PDPs to scratch page.
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@ -2057,8 +2056,7 @@ void intel_lr_context_resume(struct drm_i915_private *dev_priv)
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ce->state->obj->mm.dirty = true;
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i915_gem_object_unpin_map(ce->state->obj);
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ce->ring->head = ce->ring->tail = 0;
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intel_ring_update_space(ce->ring);
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intel_ring_reset(ce->ring, 0);
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}
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}
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}
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@ -49,7 +49,7 @@ static int __intel_ring_space(int head, int tail, int size)
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void intel_ring_update_space(struct intel_ring *ring)
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{
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ring->space = __intel_ring_space(ring->head, ring->tail, ring->size);
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ring->space = __intel_ring_space(ring->head, ring->emit, ring->size);
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}
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static int
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@ -774,8 +774,8 @@ static void i9xx_submit_request(struct drm_i915_gem_request *request)
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i915_gem_request_submit(request);
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assert_ring_tail_valid(request->ring, request->tail);
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I915_WRITE_TAIL(request->engine, request->tail);
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I915_WRITE_TAIL(request->engine,
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intel_ring_set_tail(request->ring, request->tail));
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}
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static void i9xx_emit_breadcrumb(struct drm_i915_gem_request *req, u32 *cs)
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@ -1319,11 +1319,23 @@ err:
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return PTR_ERR(addr);
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}
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void intel_ring_reset(struct intel_ring *ring, u32 tail)
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{
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GEM_BUG_ON(!list_empty(&ring->request_list));
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ring->tail = tail;
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ring->head = tail;
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ring->emit = tail;
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intel_ring_update_space(ring);
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}
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void intel_ring_unpin(struct intel_ring *ring)
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{
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GEM_BUG_ON(!ring->vma);
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GEM_BUG_ON(!ring->vaddr);
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/* Discard any unused bytes beyond that submitted to hw. */
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intel_ring_reset(ring, ring->tail);
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if (i915_vma_is_map_and_fenceable(ring->vma))
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i915_vma_unpin_iomap(ring->vma);
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else
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@ -1555,8 +1567,9 @@ void intel_legacy_submission_resume(struct drm_i915_private *dev_priv)
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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/* Restart from the beginning of the rings for convenience */
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for_each_engine(engine, dev_priv, id)
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engine->buffer->head = engine->buffer->tail;
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intel_ring_reset(engine->buffer, 0);
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}
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static int ring_request_alloc(struct drm_i915_gem_request *request)
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@ -1609,7 +1622,7 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
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unsigned space;
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/* Would completion of this request free enough space? */
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space = __intel_ring_space(target->postfix, ring->tail,
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space = __intel_ring_space(target->postfix, ring->emit,
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ring->size);
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if (space >= bytes)
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break;
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@ -1634,8 +1647,8 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
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u32 *intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
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{
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struct intel_ring *ring = req->ring;
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int remain_actual = ring->size - ring->tail;
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int remain_usable = ring->effective_size - ring->tail;
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int remain_actual = ring->size - ring->emit;
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int remain_usable = ring->effective_size - ring->emit;
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int bytes = num_dwords * sizeof(u32);
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int total_bytes, wait_bytes;
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bool need_wrap = false;
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@ -1671,17 +1684,17 @@ u32 *intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
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if (unlikely(need_wrap)) {
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GEM_BUG_ON(remain_actual > ring->space);
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GEM_BUG_ON(ring->tail + remain_actual > ring->size);
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GEM_BUG_ON(ring->emit + remain_actual > ring->size);
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/* Fill the tail with MI_NOOP */
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memset(ring->vaddr + ring->tail, 0, remain_actual);
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ring->tail = 0;
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memset(ring->vaddr + ring->emit, 0, remain_actual);
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ring->emit = 0;
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ring->space -= remain_actual;
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}
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GEM_BUG_ON(ring->tail > ring->size - bytes);
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cs = ring->vaddr + ring->tail;
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ring->tail += bytes;
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GEM_BUG_ON(ring->emit > ring->size - bytes);
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cs = ring->vaddr + ring->emit;
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ring->emit += bytes;
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ring->space -= bytes;
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GEM_BUG_ON(ring->space < 0);
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@ -1692,7 +1705,7 @@ u32 *intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
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int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
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{
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int num_dwords =
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(req->ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
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(req->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
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u32 *cs;
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if (num_dwords == 0)
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@ -143,6 +143,7 @@ struct intel_ring {
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u32 head;
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u32 tail;
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u32 emit;
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int space;
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int size;
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@ -494,6 +495,8 @@ intel_engine_create_ring(struct intel_engine_cs *engine, int size);
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int intel_ring_pin(struct intel_ring *ring,
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struct drm_i915_private *i915,
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unsigned int offset_bias);
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void intel_ring_reset(struct intel_ring *ring, u32 tail);
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void intel_ring_update_space(struct intel_ring *ring);
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void intel_ring_unpin(struct intel_ring *ring);
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void intel_ring_free(struct intel_ring *ring);
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@ -517,7 +520,7 @@ intel_ring_advance(struct drm_i915_gem_request *req, u32 *cs)
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* reserved for the command packet (i.e. the value passed to
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* intel_ring_begin()).
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*/
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GEM_BUG_ON((req->ring->vaddr + req->ring->tail) != cs);
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GEM_BUG_ON((req->ring->vaddr + req->ring->emit) != cs);
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}
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static inline u32
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@ -546,7 +549,19 @@ assert_ring_tail_valid(const struct intel_ring *ring, unsigned int tail)
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GEM_BUG_ON(tail >= ring->size);
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}
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void intel_ring_update_space(struct intel_ring *ring);
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static inline unsigned int
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intel_ring_set_tail(struct intel_ring *ring, unsigned int tail)
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{
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/* Whilst writes to the tail are strictly order, there is no
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* serialisation between readers and the writers. The tail may be
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* read by i915_gem_request_retire() just as it is being updated
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* by execlists, as although the breadcrumb is complete, the context
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* switch hasn't been seen.
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*/
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assert_ring_tail_valid(ring, tail);
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ring->tail = tail;
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return tail;
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}
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void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno);
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