rsi: fix nommu_map_sg overflow kernel panic
[ Upstream commit f700546682 ]
Following overflow kernel panic is observed on some platforms while
loading the driver. It is fixed if dynamically allocated memory is
passed to SDIO instead of static one
[ 927.513963] nommu_map_sg: overflow 17d54064ba7c+20 of device mask ffffffff
[ 927.517712] Modules linked in: rsi_sdio(+) cmac bnep arc4 rsi_91x mac80211 cfg80211
btrsi rfcomm bluetooth ecdh_generic snd_soc_sst_bytcr_rt5660
[ 927.517861] CPU: 0 PID: 1624 Comm: insmod Tainted: G W 4.15.0-1000 #1
[ 927.517870] RIP: 0010:sdhci_send_command+0x5f0/0xa90 [sdhci]
[ 927.517873] RSP: 0000:ffffac3fc064b6d8 EFLAGS: 00010086
[ 927.517895] Call Trace:
[ 927.517908] ? __schedule+0x3cd/0x890
[ 927.517915] ? mod_timer+0x17b/0x3c0
[ 927.517922] sdhci_request+0x7c/0xf0 [sdhci]
[ 927.517928] __mmc_start_request+0x5a/0x170
[ 927.517932] mmc_start_request+0x74/0x90
[ 927.517936] mmc_wait_for_req+0x87/0xe0
[ 927.517940] mmc_io_rw_extended+0x2fd/0x330
[ 927.517946] ? mmc_wait_data_done+0x30/0x30
[ 927.517951] sdio_io_rw_ext_helper+0x160/0x210
[ 927.517956] sdio_writesb+0x1d/0x20
[ 927.517966] rsi_sdio_write_register_multiple+0x68/0x110 [rsi_sdio]
[ 927.517976] rsi_hal_device_init+0x357/0x910 [rsi_91x]
[ 927.517983] ? rsi_hal_device_init+0x357/0x910 [rsi_91x]
[ 927.517990] rsi_probe+0x2c6/0x450 [rsi_sdio]
[ 927.517995] sdio_bus_probe+0xfc/0x110
[ 927.518000] driver_probe_device+0x2b3/0x490
[ 927.518005] __driver_attach+0xdf/0xf0
[ 927.518008] ? driver_probe_device+0x490/0x490
[ 927.518014] bus_for_each_dev+0x6c/0xc0
[ 927.518018] driver_attach+0x1e/0x20
[ 927.518021] bus_add_driver+0x1f4/0x270
[ 927.518028] ? rsi_sdio_ack_intr+0x50/0x50 [rsi_sdio]
[ 927.518031] driver_register+0x60/0xe0
[ 927.518038] ? rsi_sdio_ack_intr+0x50/0x50 [rsi_sdio]
[ 927.518041] sdio_register_driver+0x20/0x30
[ 927.518047] rsi_module_init+0x16/0x40 [rsi_sdio]
Signed-off-by: Siva Rebbagondla <siva.rebbagondla@redpinesignals.com>
Signed-off-by: Amitkumar Karwar <amit.karwar@redpinesignals.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
pull/10/head
Siva Rebbagondla
Greg Kroah-Hartman
parent
0be8aa812c
commit
e7cb8f11f6
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@ -557,28 +557,32 @@ static int bl_write_header(struct rsi_hw *adapter, u8 *flash_content,
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u32 content_size)
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{
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struct rsi_host_intf_ops *hif_ops = adapter->host_intf_ops;
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struct bl_header bl_hdr;
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struct bl_header *bl_hdr;
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u32 write_addr, write_len;
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int status;
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bl_hdr.flags = 0;
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bl_hdr.image_no = cpu_to_le32(adapter->priv->coex_mode);
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bl_hdr.check_sum = cpu_to_le32(
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*(u32 *)&flash_content[CHECK_SUM_OFFSET]);
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bl_hdr.flash_start_address = cpu_to_le32(
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*(u32 *)&flash_content[ADDR_OFFSET]);
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bl_hdr.flash_len = cpu_to_le32(*(u32 *)&flash_content[LEN_OFFSET]);
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bl_hdr = kzalloc(sizeof(*bl_hdr), GFP_KERNEL);
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if (!bl_hdr)
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return -ENOMEM;
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bl_hdr->flags = 0;
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bl_hdr->image_no = cpu_to_le32(adapter->priv->coex_mode);
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bl_hdr->check_sum =
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cpu_to_le32(*(u32 *)&flash_content[CHECK_SUM_OFFSET]);
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bl_hdr->flash_start_address =
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cpu_to_le32(*(u32 *)&flash_content[ADDR_OFFSET]);
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bl_hdr->flash_len = cpu_to_le32(*(u32 *)&flash_content[LEN_OFFSET]);
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write_len = sizeof(struct bl_header);
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if (adapter->rsi_host_intf == RSI_HOST_INTF_USB) {
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write_addr = PING_BUFFER_ADDRESS;
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status = hif_ops->write_reg_multiple(adapter, write_addr,
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(u8 *)&bl_hdr, write_len);
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(u8 *)bl_hdr, write_len);
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if (status < 0) {
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rsi_dbg(ERR_ZONE,
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"%s: Failed to load Version/CRC structure\n",
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__func__);
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return status;
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goto fail;
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}
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} else {
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write_addr = PING_BUFFER_ADDRESS >> 16;
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@ -587,20 +591,23 @@ static int bl_write_header(struct rsi_hw *adapter, u8 *flash_content,
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rsi_dbg(ERR_ZONE,
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"%s: Unable to set ms word to common reg\n",
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__func__);
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return status;
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goto fail;
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}
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write_addr = RSI_SD_REQUEST_MASTER |
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(PING_BUFFER_ADDRESS & 0xFFFF);
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status = hif_ops->write_reg_multiple(adapter, write_addr,
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(u8 *)&bl_hdr, write_len);
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(u8 *)bl_hdr, write_len);
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if (status < 0) {
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rsi_dbg(ERR_ZONE,
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"%s: Failed to load Version/CRC structure\n",
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__func__);
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return status;
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goto fail;
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}
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}
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return 0;
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status = 0;
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fail:
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kfree(bl_hdr);
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return status;
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}
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static u32 read_flash_capacity(struct rsi_hw *adapter)
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@ -968,17 +968,21 @@ static void ulp_read_write(struct rsi_hw *adapter, u16 addr, u32 data,
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/*This function resets and re-initializes the chip.*/
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static void rsi_reset_chip(struct rsi_hw *adapter)
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{
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__le32 data;
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u8 *data;
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u8 sdio_interrupt_status = 0;
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u8 request = 1;
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int ret;
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data = kzalloc(sizeof(u32), GFP_KERNEL);
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if (!data)
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return;
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rsi_dbg(INFO_ZONE, "Writing disable to wakeup register\n");
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ret = rsi_sdio_write_register(adapter, 0, SDIO_WAKEUP_REG, &request);
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if (ret < 0) {
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rsi_dbg(ERR_ZONE,
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"%s: Failed to write SDIO wakeup register\n", __func__);
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return;
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goto err;
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}
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msleep(20);
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ret = rsi_sdio_read_register(adapter, RSI_FN1_INT_REGISTER,
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@ -986,7 +990,7 @@ static void rsi_reset_chip(struct rsi_hw *adapter)
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if (ret < 0) {
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rsi_dbg(ERR_ZONE, "%s: Failed to Read Intr Status Register\n",
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__func__);
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return;
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goto err;
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}
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rsi_dbg(INFO_ZONE, "%s: Intr Status Register value = %d\n",
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__func__, sdio_interrupt_status);
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@ -996,17 +1000,17 @@ static void rsi_reset_chip(struct rsi_hw *adapter)
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rsi_dbg(ERR_ZONE,
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"%s: Unable to set ms word to common reg\n",
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__func__);
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return;
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goto err;
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}
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data = TA_HOLD_THREAD_VALUE;
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put_unaligned_le32(TA_HOLD_THREAD_VALUE, data);
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if (rsi_sdio_write_register_multiple(adapter, TA_HOLD_THREAD_REG |
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RSI_SD_REQUEST_MASTER,
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(u8 *)&data, 4)) {
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data, 4)) {
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rsi_dbg(ERR_ZONE,
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"%s: Unable to hold Thread-Arch processor threads\n",
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__func__);
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return;
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goto err;
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}
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/* This msleep will ensure Thread-Arch processor to go to hold
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@ -1027,6 +1031,9 @@ static void rsi_reset_chip(struct rsi_hw *adapter)
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* read write operations to complete for chip reset.
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*/
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msleep(500);
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err:
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kfree(data);
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return;
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}
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/**
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@ -85,7 +85,7 @@ enum sdio_interrupt_type {
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#define TA_SOFT_RST_CLR 0
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#define TA_SOFT_RST_SET BIT(0)
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#define TA_PC_ZERO 0
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#define TA_HOLD_THREAD_VALUE cpu_to_le32(0xF)
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#define TA_HOLD_THREAD_VALUE 0xF
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#define TA_RELEASE_THREAD_VALUE cpu_to_le32(0xF)
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#define TA_BASE_ADDR 0x2200
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#define MISC_CFG_BASE_ADDR 0x4105
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