dsa: mv88e6xxx: Set the RGMII delay based on phy interface
Some Marvell switches allow the RGMII Rx and Tx clock to be delayed when the port is using RGMII. Have the adjust_link function look at the phy interface type and enable this delay as requested. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -612,6 +612,16 @@ void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
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if (phydev->duplex == DUPLEX_FULL)
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reg |= PORT_PCS_CTRL_DUPLEX_FULL;
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if ((mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds)) &&
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(port >= ps->num_ports - 2)) {
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
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reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
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reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
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reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
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PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
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}
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_mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_PCS_CTRL, reg);
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out:
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@ -46,6 +46,8 @@
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#define PORT_STATUS_TX_PAUSED BIT(5)
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#define PORT_STATUS_FLOW_CTRL BIT(4)
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#define PORT_PCS_CTRL 0x01
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#define PORT_PCS_CTRL_RGMII_DELAY_RXCLK BIT(15)
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#define PORT_PCS_CTRL_RGMII_DELAY_TXCLK BIT(14)
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#define PORT_PCS_CTRL_FC BIT(7)
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#define PORT_PCS_CTRL_FORCE_FC BIT(6)
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#define PORT_PCS_CTRL_LINK_UP BIT(5)
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