ARM: dts: sk-rzg1e: initial device tree
Add the initial device tree for the R8A7745 SoC based SK-RZG1E board. The board has 1 debug serial port (SCIF2); include support for it, so that the serial console can work. Based on the original (and large) patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -678,6 +678,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
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r8a73a4-ape6evm.dtb \
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r8a7740-armadillo800eva.dtb \
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r8a7743-sk-rzg1m.dtb \
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r8a7745-sk-rzg1e.dtb \
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r8a7778-bockw.dtb \
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r8a7779-marzen.dtb \
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r8a7790-lager.dtb \
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39
arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
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39
arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
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@ -0,0 +1,39 @@
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/*
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* Device Tree Source for the SK-RZG1E board
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*
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* Copyright (C) 2016 Cogent Embedded, Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/dts-v1/;
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#include "r8a7745.dtsi"
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/ {
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model = "SK-RZG1E";
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compatible = "renesas,sk-rzg1e", "renesas,r8a7745";
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aliases {
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serial0 = &scif2;
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};
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chosen {
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bootargs = "ignore_loglevel";
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stdout-path = "serial0:115200n8";
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0 0x40000000 0 0x40000000>;
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};
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};
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&extal_clk {
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clock-frequency = <20000000>;
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};
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&scif2 {
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status = "okay";
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};
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