[IA64] multi-core/multi-thread identification
Version 3 - rediffed to apply on top of Ashok's hotplug cpu patch. /proc/cpuinfo output in step with x86. This is an updated MC/MT identification patch based on the previous discussions on list. Add the Multi-core and Multi-threading detection for IPF. - Add new core and threading related fields in /proc/cpuinfo. Physical id Core id Thread id Siblings - setup the cpu_core_map and cpu_sibling_map appropriately - Handles Hot plug CPU Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Gordon Jin <gordon.jin@intel.com> Signed-off-by: Rohit Seth <rohit.seth@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>wifi-calibration
Suresh Siddha
Tony Luck
parent
6118ec847e
commit
e927ecb05e
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@ -4,10 +4,15 @@
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* Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
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* David Mosberger-Tang <davidm@hpl.hp.com>
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* Stephane Eranian <eranian@hpl.hp.com>
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* Copyright (C) 2000, Rohit Seth <rohit.seth@intel.com>
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* Copyright (C) 2000, 2004 Intel Corp
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* Rohit Seth <rohit.seth@intel.com>
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* Suresh Siddha <suresh.b.siddha@intel.com>
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* Gordon Jin <gordon.jin@intel.com>
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* Copyright (C) 1999 VA Linux Systems
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* Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
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*
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* 12/26/04 S.Siddha, G.Jin, R.Seth
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* Add multi-threading and multi-core detection
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* 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
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* 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
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* 03/31/00 R.Seth cpu_initialized and current->processor fixes
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@ -296,6 +301,34 @@ mark_bsp_online (void)
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#endif
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}
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#ifdef CONFIG_SMP
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static void
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check_for_logical_procs (void)
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{
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pal_logical_to_physical_t info;
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s64 status;
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status = ia64_pal_logical_to_phys(0, &info);
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if (status == -1) {
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printk(KERN_INFO "No logical to physical processor mapping "
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"available\n");
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return;
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}
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if (status) {
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printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n",
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status);
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return;
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}
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/*
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* Total number of siblings that BSP has. Though not all of them
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* may have booted successfully. The correct number of siblings
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* booted is in info.overview_num_log.
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*/
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smp_num_siblings = info.overview_tpc;
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smp_num_cpucores = info.overview_cpp;
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}
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#endif
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void __init
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setup_arch (char **cmdline_p)
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{
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@ -356,6 +389,19 @@ setup_arch (char **cmdline_p)
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#ifdef CONFIG_SMP
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cpu_physical_id(0) = hard_smp_processor_id();
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cpu_set(0, cpu_sibling_map[0]);
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cpu_set(0, cpu_core_map[0]);
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check_for_logical_procs();
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if (smp_num_cpucores > 1)
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printk(KERN_INFO
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"cpu package is Multi-Core capable: number of cores=%d\n",
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smp_num_cpucores);
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if (smp_num_siblings > 1)
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printk(KERN_INFO
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"cpu package is Multi-Threading capable: number of siblings=%d\n",
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smp_num_siblings);
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#endif
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cpu_init(); /* initialize the bootstrap CPU */
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@ -459,12 +505,23 @@ show_cpuinfo (struct seq_file *m, void *v)
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"cpu regs : %u\n"
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"cpu MHz : %lu.%06lu\n"
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"itc MHz : %lu.%06lu\n"
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"BogoMIPS : %lu.%02lu\n\n",
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"BogoMIPS : %lu.%02lu\n",
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cpunum, c->vendor, family, c->model, c->revision, c->archrev,
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features, c->ppn, c->number,
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c->proc_freq / 1000000, c->proc_freq % 1000000,
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c->itc_freq / 1000000, c->itc_freq % 1000000,
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lpj*HZ/500000, (lpj*HZ/5000) % 100);
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#ifdef CONFIG_SMP
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if (c->threads_per_core > 1 || c->cores_per_socket > 1)
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seq_printf(m,
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"physical id: %u\n"
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"core id : %u\n"
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"thread id : %u\n",
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c->socket_id, c->core_id, c->thread_id);
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seq_printf(m, "siblings : %u\n", c->num_log);
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#endif
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seq_printf(m,"\n");
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return 0;
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}
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@ -533,6 +590,14 @@ identify_cpu (struct cpuinfo_ia64 *c)
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memcpy(c->vendor, cpuid.field.vendor, 16);
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#ifdef CONFIG_SMP
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c->cpu = smp_processor_id();
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/* below default values will be overwritten by identify_siblings()
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* for Multi-Threading/Multi-Core capable cpu's
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*/
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c->threads_per_core = c->cores_per_socket = c->num_log = 1;
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c->socket_id = -1;
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identify_siblings(c);
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#endif
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c->ppn = cpuid.field.ppn;
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c->number = cpuid.field.number;
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@ -3,6 +3,11 @@
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*
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* Copyright (C) 1998-2003, 2005 Hewlett-Packard Co
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* David Mosberger-Tang <davidm@hpl.hp.com>
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* Copyright (C) 2001, 2004-2005 Intel Corp
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* Rohit Seth <rohit.seth@intel.com>
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* Suresh Siddha <suresh.b.siddha@intel.com>
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* Gordon Jin <gordon.jin@intel.com>
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* Ashok Raj <ashok.raj@intel.com>
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*
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* 01/05/16 Rohit Seth <rohit.seth@intel.com> Moved SMP booting functions from smp.c to here.
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* 01/04/27 David Mosberger <davidm@hpl.hp.com> Added ITC synching code.
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@ -10,6 +15,11 @@
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* smp_boot_cpus()/smp_commence() is replaced by
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* smp_prepare_cpus()/__cpu_up()/smp_cpus_done().
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* 04/06/21 Ashok Raj <ashok.raj@intel.com> Added CPU Hotplug Support
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* 04/12/26 Jin Gordon <gordon.jin@intel.com>
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* 04/12/26 Rohit Seth <rohit.seth@intel.com>
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* Add multi-threading and multi-core detection
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* 05/01/30 Suresh Siddha <suresh.b.siddha@intel.com>
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* Setup cpu_sibling_map and cpu_core_map
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*/
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#include <linux/config.h>
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@ -122,6 +132,11 @@ EXPORT_SYMBOL(cpu_online_map);
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cpumask_t cpu_possible_map;
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EXPORT_SYMBOL(cpu_possible_map);
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cpumask_t cpu_core_map[NR_CPUS] __cacheline_aligned;
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cpumask_t cpu_sibling_map[NR_CPUS] __cacheline_aligned;
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int smp_num_siblings = 1;
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int smp_num_cpucores = 1;
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/* which logical CPU number maps to which CPU (physical APIC ID) */
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volatile int ia64_cpu_to_sapicid[NR_CPUS];
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EXPORT_SYMBOL(ia64_cpu_to_sapicid);
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@ -598,7 +613,68 @@ void __devinit smp_prepare_boot_cpu(void)
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cpu_set(smp_processor_id(), cpu_callin_map);
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}
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/*
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* mt_info[] is a temporary store for all info returned by
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* PAL_LOGICAL_TO_PHYSICAL, to be copied into cpuinfo_ia64 when the
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* specific cpu comes.
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*/
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static struct {
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__u32 socket_id;
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__u16 core_id;
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__u16 thread_id;
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__u16 proc_fixed_addr;
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__u8 valid;
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}mt_info[NR_CPUS] __devinit;
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#ifdef CONFIG_HOTPLUG_CPU
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static inline void
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remove_from_mtinfo(int cpu)
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{
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int i;
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for_each_cpu(i)
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if (mt_info[i].valid && mt_info[i].socket_id ==
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cpu_data(cpu)->socket_id)
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mt_info[i].valid = 0;
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}
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static inline void
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clear_cpu_sibling_map(int cpu)
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{
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int i;
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for_each_cpu_mask(i, cpu_sibling_map[cpu])
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cpu_clear(cpu, cpu_sibling_map[i]);
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for_each_cpu_mask(i, cpu_core_map[cpu])
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cpu_clear(cpu, cpu_core_map[i]);
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cpu_sibling_map[cpu] = cpu_core_map[cpu] = CPU_MASK_NONE;
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}
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static void
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remove_siblinginfo(int cpu)
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{
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int last = 0;
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if (cpu_data(cpu)->threads_per_core == 1 &&
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cpu_data(cpu)->cores_per_socket == 1) {
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cpu_clear(cpu, cpu_core_map[cpu]);
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cpu_clear(cpu, cpu_sibling_map[cpu]);
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return;
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}
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last = (cpus_weight(cpu_core_map[cpu]) == 1 ? 1 : 0);
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/* remove it from all sibling map's */
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clear_cpu_sibling_map(cpu);
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/* if this cpu is the last in the core group, remove all its info
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* from mt_info structure
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*/
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if (last)
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remove_from_mtinfo(cpu);
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}
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extern void fixup_irqs(void);
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/* must be called with cpucontrol mutex held */
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int __cpu_disable(void)
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@ -611,6 +687,7 @@ int __cpu_disable(void)
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if (cpu == 0)
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return -EBUSY;
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remove_siblinginfo(cpu);
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fixup_irqs();
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local_flush_tlb_all();
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cpu_clear(cpu, cpu_callin_map);
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@ -663,6 +740,23 @@ smp_cpus_done (unsigned int dummy)
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(int)num_online_cpus(), bogosum/(500000/HZ), (bogosum/(5000/HZ))%100);
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}
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static inline void __devinit
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set_cpu_sibling_map(int cpu)
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{
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int i;
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for_each_online_cpu(i) {
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if ((cpu_data(cpu)->socket_id == cpu_data(i)->socket_id)) {
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cpu_set(i, cpu_core_map[cpu]);
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cpu_set(cpu, cpu_core_map[i]);
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if (cpu_data(cpu)->core_id == cpu_data(i)->core_id) {
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cpu_set(i, cpu_sibling_map[cpu]);
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cpu_set(cpu, cpu_sibling_map[i]);
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}
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}
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}
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}
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int __devinit
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__cpu_up (unsigned int cpu)
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{
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@ -685,6 +779,15 @@ __cpu_up (unsigned int cpu)
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if (ret < 0)
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return ret;
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if (cpu_data(cpu)->threads_per_core == 1 &&
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cpu_data(cpu)->cores_per_socket == 1) {
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cpu_set(cpu, cpu_sibling_map[cpu]);
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cpu_set(cpu, cpu_core_map[cpu]);
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return 0;
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}
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set_cpu_sibling_map(cpu);
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return 0;
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}
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@ -712,3 +815,106 @@ init_smp_config(void)
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ia64_sal_strerror(sal_ret));
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}
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static inline int __devinit
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check_for_mtinfo_index(void)
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{
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int i;
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for_each_cpu(i)
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if (!mt_info[i].valid)
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return i;
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return -1;
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}
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/*
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* Search the mt_info to find out if this socket's cid/tid information is
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* cached or not. If the socket exists, fill in the core_id and thread_id
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* in cpuinfo
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*/
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static int __devinit
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check_for_new_socket(__u16 logical_address, struct cpuinfo_ia64 *c)
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{
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int i;
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__u32 sid = c->socket_id;
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for_each_cpu(i) {
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if (mt_info[i].valid && mt_info[i].proc_fixed_addr == logical_address
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&& mt_info[i].socket_id == sid) {
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c->core_id = mt_info[i].core_id;
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c->thread_id = mt_info[i].thread_id;
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return 1; /* not a new socket */
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}
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}
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return 0;
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}
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/*
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* identify_siblings(cpu) gets called from identify_cpu. This populates the
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* information related to logical execution units in per_cpu_data structure.
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*/
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void __devinit
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identify_siblings(struct cpuinfo_ia64 *c)
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{
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s64 status;
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u16 pltid;
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u64 proc_fixed_addr;
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int count, i;
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pal_logical_to_physical_t info;
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if (smp_num_cpucores == 1 && smp_num_siblings == 1)
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return;
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if ((status = ia64_pal_logical_to_phys(0, &info)) != PAL_STATUS_SUCCESS) {
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printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n",
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status);
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return;
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}
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if ((status = ia64_sal_physical_id_info(&pltid)) != PAL_STATUS_SUCCESS) {
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printk(KERN_ERR "ia64_sal_pltid failed with %ld\n", status);
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return;
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}
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if ((status = ia64_pal_fixed_addr(&proc_fixed_addr)) != PAL_STATUS_SUCCESS) {
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printk(KERN_ERR "ia64_pal_fixed_addr failed with %ld\n", status);
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return;
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}
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c->socket_id = (pltid << 8) | info.overview_ppid;
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c->cores_per_socket = info.overview_cpp;
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c->threads_per_core = info.overview_tpc;
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count = c->num_log = info.overview_num_log;
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/* If the thread and core id information is already cached, then
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* we will simply update cpu_info and return. Otherwise, we will
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* do the PAL calls and cache core and thread id's of all the siblings.
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*/
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if (check_for_new_socket(proc_fixed_addr, c))
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return;
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for (i = 0; i < count; i++) {
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int index;
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if (i && (status = ia64_pal_logical_to_phys(i, &info))
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!= PAL_STATUS_SUCCESS) {
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printk(KERN_ERR "ia64_pal_logical_to_phys failed"
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" with %ld\n", status);
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return;
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}
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if (info.log2_la == proc_fixed_addr) {
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c->core_id = info.log1_cid;
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c->thread_id = info.log1_tid;
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}
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index = check_for_mtinfo_index();
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/* We will not do the mt_info caching optimization in this case.
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*/
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if (index < 0)
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continue;
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mt_info[index].valid = 1;
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mt_info[index].socket_id = c->socket_id;
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mt_info[index].core_id = info.log1_cid;
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mt_info[index].thread_id = info.log1_tid;
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mt_info[index].proc_fixed_addr = info.log2_la;
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}
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}
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@ -67,6 +67,7 @@
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#define PAL_REGISTER_INFO 39 /* return AR and CR register information*/
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#define PAL_SHUTDOWN 40 /* enter processor shutdown state */
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#define PAL_PREFETCH_VISIBILITY 41 /* Make Processor Prefetches Visible */
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#define PAL_LOGICAL_TO_PHYSICAL 42 /* returns information on logical to physical processor mapping */
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#define PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */
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#define PAL_HALT_INFO 257 /* return the low power capabilities of processor */
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@ -1559,6 +1560,73 @@ ia64_pal_prefetch_visibility (s64 trans_type)
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return iprv.status;
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}
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/* data structure for getting information on logical to physical mappings */
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typedef union pal_log_overview_u {
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struct {
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u64 num_log :16, /* Total number of logical
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* processors on this die
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*/
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tpc :8, /* Threads per core */
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reserved3 :8, /* Reserved */
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cpp :8, /* Cores per processor */
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reserved2 :8, /* Reserved */
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ppid :8, /* Physical processor ID */
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reserved1 :8; /* Reserved */
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} overview_bits;
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u64 overview_data;
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} pal_log_overview_t;
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typedef union pal_proc_n_log_info1_u{
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struct {
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u64 tid :16, /* Thread id */
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reserved2 :16, /* Reserved */
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cid :16, /* Core id */
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reserved1 :16; /* Reserved */
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} ppli1_bits;
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u64 ppli1_data;
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} pal_proc_n_log_info1_t;
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typedef union pal_proc_n_log_info2_u {
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struct {
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u64 la :16, /* Logical address */
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reserved :48; /* Reserved */
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} ppli2_bits;
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u64 ppli2_data;
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} pal_proc_n_log_info2_t;
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typedef struct pal_logical_to_physical_s
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{
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pal_log_overview_t overview;
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pal_proc_n_log_info1_t ppli1;
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pal_proc_n_log_info2_t ppli2;
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} pal_logical_to_physical_t;
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#define overview_num_log overview.overview_bits.num_log
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#define overview_tpc overview.overview_bits.tpc
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#define overview_cpp overview.overview_bits.cpp
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#define overview_ppid overview.overview_bits.ppid
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#define log1_tid ppli1.ppli1_bits.tid
|
||||
#define log1_cid ppli1.ppli1_bits.cid
|
||||
#define log2_la ppli2.ppli2_bits.la
|
||||
|
||||
/* Get information on logical to physical processor mappings. */
|
||||
static inline s64
|
||||
ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
|
||||
{
|
||||
struct ia64_pal_retval iprv;
|
||||
|
||||
PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);
|
||||
|
||||
if (iprv.status == PAL_STATUS_SUCCESS)
|
||||
{
|
||||
if (proc_number == 0)
|
||||
mapping->overview.overview_data = iprv.v0;
|
||||
mapping->ppli1.ppli1_data = iprv.v1;
|
||||
mapping->ppli2.ppli2_data = iprv.v2;
|
||||
}
|
||||
|
||||
return iprv.status;
|
||||
}
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _ASM_IA64_PAL_H */
|
||||
|
|
|
|||
|
|
@ -148,6 +148,13 @@ struct cpuinfo_ia64 {
|
|||
#ifdef CONFIG_SMP
|
||||
__u64 loops_per_jiffy;
|
||||
int cpu;
|
||||
__u32 socket_id; /* physical processor socket id */
|
||||
__u16 core_id; /* core id */
|
||||
__u16 thread_id; /* thread id */
|
||||
__u16 num_log; /* Total number of logical processors on
|
||||
* this socket that were successfully booted */
|
||||
__u8 cores_per_socket; /* Cores per processor socket */
|
||||
__u8 threads_per_core; /* Threads per core */
|
||||
#endif
|
||||
|
||||
/* CPUID-derived information: */
|
||||
|
|
|
|||
|
|
@ -91,6 +91,7 @@ extern spinlock_t sal_lock;
|
|||
#define SAL_PCI_CONFIG_READ 0x01000010
|
||||
#define SAL_PCI_CONFIG_WRITE 0x01000011
|
||||
#define SAL_FREQ_BASE 0x01000012
|
||||
#define SAL_PHYSICAL_ID_INFO 0x01000013
|
||||
|
||||
#define SAL_UPDATE_PAL 0x01000020
|
||||
|
||||
|
|
@ -815,6 +816,17 @@ ia64_sal_update_pal (u64 param_buf, u64 scratch_buf, u64 scratch_buf_size,
|
|||
return isrv.status;
|
||||
}
|
||||
|
||||
/* Get physical processor die mapping in the platform. */
|
||||
static inline s64
|
||||
ia64_sal_physical_id_info(u16 *splid)
|
||||
{
|
||||
struct ia64_sal_retval isrv;
|
||||
SAL_CALL(isrv, SAL_PHYSICAL_ID_INFO, 0, 0, 0, 0, 0, 0, 0);
|
||||
if (splid)
|
||||
*splid = isrv.v0;
|
||||
return isrv.status;
|
||||
}
|
||||
|
||||
extern unsigned long sal_platform_features;
|
||||
|
||||
extern int (*salinfo_platform_oemdata)(const u8 *, u8 **, u64 *);
|
||||
|
|
|
|||
|
|
@ -56,6 +56,10 @@ extern struct smp_boot_data {
|
|||
extern char no_int_routing __devinitdata;
|
||||
|
||||
extern cpumask_t cpu_online_map;
|
||||
extern cpumask_t cpu_core_map[NR_CPUS];
|
||||
extern cpumask_t cpu_sibling_map[NR_CPUS];
|
||||
extern int smp_num_siblings;
|
||||
extern int smp_num_cpucores;
|
||||
extern void __iomem *ipi_base_addr;
|
||||
extern unsigned char smp_int_redirect;
|
||||
|
||||
|
|
@ -124,6 +128,7 @@ extern int smp_call_function_single (int cpuid, void (*func) (void *info), void
|
|||
extern void smp_send_reschedule (int cpu);
|
||||
extern void lock_ipi_calllock(void);
|
||||
extern void unlock_ipi_calllock(void);
|
||||
extern void identify_siblings (struct cpuinfo_ia64 *);
|
||||
|
||||
#else
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue