watchdog: stm32: add dynamic prescaler support
This patch allows to define the max prescaler by compatible. To set a large range of timeout, the prescaler should be set dynamically (from the timeout request) to improve the resolution in order to have a timeout close to the expected value. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
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@ -34,36 +34,44 @@
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#define KR_KEY_EWA 0x5555 /* write access enable */
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#define KR_KEY_DWA 0x0000 /* write access disable */
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/* IWDG_PR register bit values */
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#define PR_4 0x00 /* prescaler set to 4 */
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#define PR_8 0x01 /* prescaler set to 8 */
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#define PR_16 0x02 /* prescaler set to 16 */
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#define PR_32 0x03 /* prescaler set to 32 */
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#define PR_64 0x04 /* prescaler set to 64 */
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#define PR_128 0x05 /* prescaler set to 128 */
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#define PR_256 0x06 /* prescaler set to 256 */
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/* IWDG_PR register */
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#define PR_SHIFT 2
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#define PR_MIN BIT(PR_SHIFT)
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/* IWDG_RLR register values */
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#define RLR_MIN 0x07C /* min value supported by reload register */
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#define RLR_MAX 0xFFF /* max value supported by reload register */
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#define RLR_MIN 0x2 /* min value recommended */
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#define RLR_MAX GENMASK(11, 0) /* max value of reload register */
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/* IWDG_SR register bit mask */
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#define FLAG_PVU BIT(0) /* Watchdog prescaler value update */
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#define FLAG_RVU BIT(1) /* Watchdog counter reload value update */
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#define SR_PVU BIT(0) /* Watchdog prescaler value update */
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#define SR_RVU BIT(1) /* Watchdog counter reload value update */
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/* set timeout to 100000 us */
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#define TIMEOUT_US 100000
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#define SLEEP_US 1000
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#define HAS_PCLK true
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struct stm32_iwdg_data {
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bool has_pclk;
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u32 max_prescaler;
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};
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static const struct stm32_iwdg_data stm32_iwdg_data = {
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.has_pclk = false,
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.max_prescaler = 256,
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};
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static const struct stm32_iwdg_data stm32mp1_iwdg_data = {
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.has_pclk = true,
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.max_prescaler = 1024,
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};
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struct stm32_iwdg {
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struct watchdog_device wdd;
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const struct stm32_iwdg_data *data;
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void __iomem *regs;
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struct clk *clk_lsi;
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struct clk *clk_pclk;
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unsigned int rate;
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bool has_pclk;
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};
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static inline u32 reg_read(void __iomem *base, u32 reg)
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@ -79,31 +87,35 @@ static inline void reg_write(void __iomem *base, u32 reg, u32 val)
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static int stm32_iwdg_start(struct watchdog_device *wdd)
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{
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struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
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u32 val = FLAG_PVU | FLAG_RVU;
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u32 reload;
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u32 tout, presc, iwdg_rlr, iwdg_pr, iwdg_sr;
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int ret;
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dev_dbg(wdd->parent, "%s\n", __func__);
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/* prescaler fixed to 256 */
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reload = clamp_t(unsigned int, ((wdd->timeout * wdt->rate) / 256) - 1,
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RLR_MIN, RLR_MAX);
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tout = clamp_t(unsigned int, wdd->timeout,
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wdd->min_timeout, wdd->max_hw_heartbeat_ms / 1000);
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presc = DIV_ROUND_UP(tout * wdt->rate, RLR_MAX + 1);
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/* The prescaler is align on power of 2 and start at 2 ^ PR_SHIFT. */
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presc = roundup_pow_of_two(presc);
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iwdg_pr = presc <= 1 << PR_SHIFT ? 0 : ilog2(presc) - PR_SHIFT;
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iwdg_rlr = ((tout * wdt->rate) / presc) - 1;
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/* enable write access */
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reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA);
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/* set prescaler & reload registers */
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reg_write(wdt->regs, IWDG_PR, PR_256); /* prescaler fix to 256 */
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reg_write(wdt->regs, IWDG_RLR, reload);
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reg_write(wdt->regs, IWDG_PR, iwdg_pr);
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reg_write(wdt->regs, IWDG_RLR, iwdg_rlr);
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reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE);
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/* wait for the registers to be updated (max 100ms) */
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ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, val,
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!(val & (FLAG_PVU | FLAG_RVU)),
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ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, iwdg_sr,
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!(iwdg_sr & (SR_PVU | SR_RVU)),
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SLEEP_US, TIMEOUT_US);
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if (ret) {
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dev_err(wdd->parent,
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"Fail to set prescaler or reload registers\n");
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dev_err(wdd->parent, "Fail to set prescaler, reload regs\n");
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return ret;
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}
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@ -156,7 +168,7 @@ static int stm32_iwdg_clk_init(struct platform_device *pdev,
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}
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/* optional peripheral clock */
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if (wdt->has_pclk) {
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if (wdt->data->has_pclk) {
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wdt->clk_pclk = devm_clk_get(dev, "pclk");
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if (IS_ERR(wdt->clk_pclk)) {
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dev_err(dev, "Unable to get pclk clock\n");
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@ -205,8 +217,8 @@ static const struct watchdog_ops stm32_iwdg_ops = {
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};
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static const struct of_device_id stm32_iwdg_of_match[] = {
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{ .compatible = "st,stm32-iwdg", .data = (void *)!HAS_PCLK },
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{ .compatible = "st,stm32mp1-iwdg", .data = (void *)HAS_PCLK },
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{ .compatible = "st,stm32-iwdg", .data = &stm32_iwdg_data },
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{ .compatible = "st,stm32mp1-iwdg", .data = &stm32mp1_iwdg_data },
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{ /* end node */ }
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};
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MODULE_DEVICE_TABLE(of, stm32_iwdg_of_match);
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@ -215,19 +227,16 @@ static int stm32_iwdg_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct watchdog_device *wdd;
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const struct of_device_id *match;
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struct stm32_iwdg *wdt;
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int ret;
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match = of_match_device(stm32_iwdg_of_match, dev);
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if (!match)
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return -ENODEV;
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wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
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if (!wdt)
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return -ENOMEM;
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wdt->has_pclk = match->data;
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wdt->data = of_device_get_match_data(&pdev->dev);
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if (!wdt->data)
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return -ENODEV;
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/* This is the timer base. */
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wdt->regs = devm_platform_ioremap_resource(pdev, 0);
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@ -242,11 +251,12 @@ static int stm32_iwdg_probe(struct platform_device *pdev)
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/* Initialize struct watchdog_device. */
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wdd = &wdt->wdd;
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wdd->parent = dev;
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wdd->info = &stm32_iwdg_info;
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wdd->ops = &stm32_iwdg_ops;
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wdd->min_timeout = ((RLR_MIN + 1) * 256) / wdt->rate;
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wdd->max_hw_heartbeat_ms = ((RLR_MAX + 1) * 256 * 1000) / wdt->rate;
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wdd->parent = dev;
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wdd->min_timeout = DIV_ROUND_UP((RLR_MIN + 1) * PR_MIN, wdt->rate);
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wdd->max_hw_heartbeat_ms = ((RLR_MAX + 1) * wdt->data->max_prescaler *
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1000) / wdt->rate;
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watchdog_set_drvdata(wdd, wdt);
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watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
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