ARM: S5PV210: Add Power Management Support
This patch adds suspend-to-ram support for S5PV210. Note. This patch is confirmed on SMDKV210 and SMDKC110 board. Signed-off-by: Jongpill Lee <boyko.lee@samsung.com> Signed-off-by: Sangbeom Kim <sbkim73@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Jongpill Lee
Kukjin Kim
parent
dc425471b6
commit
ea31fd4330
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@ -13,6 +13,7 @@ config CPU_S5PV210
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bool
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select S3C_PL330_DMA
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select S5P_EXT_INT
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select S5PV210_PM if PM
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help
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Enable S5PV210 CPU support
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@ -152,4 +153,9 @@ config MACH_TORBRECK
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endmenu
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config S5PV210_PM
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bool
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help
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Power Management code common to S5PV210
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endif
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@ -14,6 +14,7 @@ obj- :=
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obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o gpiolib.o
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obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o
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obj-$(CONFIG_S5PV210_PM) += pm.o sleep.o
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# machine support
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43
arch/arm/mach-s5pv210/include/mach/pm-core.h
Normal file
43
arch/arm/mach-s5pv210/include/mach/pm-core.h
Normal file
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@ -0,0 +1,43 @@
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/* linux/arch/arm/mach-s5pv210/include/mach/pm-core.h
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S5PV210 - PM core support for arch/arm/plat-s5p/pm.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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static inline void s3c_pm_debug_init_uart(void)
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{
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/* nothing here yet */
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}
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static inline void s3c_pm_arch_prepare_irqs(void)
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{
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__raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
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__raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
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}
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static inline void s3c_pm_arch_stop_clocks(void)
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{
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/* nothing here yet */
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}
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static inline void s3c_pm_arch_show_resume_irqs(void)
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{
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/* nothing here yet */
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}
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static inline void s3c_pm_arch_update_uart(void __iomem *regs,
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struct pm_uart_save *save)
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{
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/* nothing here yet */
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}
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@ -95,7 +95,7 @@
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/* Registers related to power management */
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#define S5P_PWR_CFG S5P_CLKREG(0xC000)
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#define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0xC004)
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#define S5P_WAKEUP_MASK S5P_CLKREG(0xC008)
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#define S5P_WAKEUP_MASK S5P_CLKREG(0xC008)
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#define S5P_PWR_MODE S5P_CLKREG(0xC00C)
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#define S5P_NORMAL_CFG S5P_CLKREG(0xC010)
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#define S5P_IDLE_CFG S5P_CLKREG(0xC020)
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@ -159,8 +159,11 @@
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#define S5P_SLEEP_CFG_USBOSC_EN (1 << 1)
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/* OTHERS Resgister */
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#define S5P_OTHERS_RET_IO (1 << 31)
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#define S5P_OTHERS_RET_CF (1 << 30)
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#define S5P_OTHERS_RET_MMC (1 << 29)
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#define S5P_OTHERS_RET_UART (1 << 28)
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#define S5P_OTHERS_USB_SIG_MASK (1 << 16)
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#define S5P_OTHERS_MIPI_DPHY_EN (1 << 28)
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/* MIPI */
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#define S5P_MIPI_DPHY_EN (3)
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@ -28,6 +28,7 @@
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#include <plat/cpu.h>
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#include <plat/ata.h>
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#include <plat/iic.h>
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#include <plat/pm.h>
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/* Following are default values for UCON, ULCON and UFCON UART registers */
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#define SMDKC110_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
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@ -110,6 +111,8 @@ static void __init smdkc110_map_io(void)
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static void __init smdkc110_machine_init(void)
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{
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s3c_pm_init();
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s3c_i2c0_set_platdata(NULL);
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s3c_i2c1_set_platdata(NULL);
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s3c_i2c2_set_platdata(NULL);
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@ -31,6 +31,7 @@
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#include <plat/ata.h>
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#include <plat/iic.h>
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#include <plat/keypad.h>
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#include <plat/pm.h>
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/* Following are default values for UCON, ULCON and UFCON UART registers */
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#define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
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@ -145,6 +146,8 @@ static void __init smdkv210_map_io(void)
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static void __init smdkv210_machine_init(void)
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{
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s3c_pm_init();
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samsung_keypad_set_platdata(&smdkv210_keypad_data);
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s3c24xx_ts_set_platdata(&s3c_ts_platform);
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166
arch/arm/mach-s5pv210/pm.c
Normal file
166
arch/arm/mach-s5pv210/pm.c
Normal file
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@ -0,0 +1,166 @@
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/* linux/arch/arm/mach-s5pv210/pm.c
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* S5PV210 - Power Management support
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*
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* Based on arch/arm/mach-s3c2410/pm.c
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* Copyright (c) 2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/suspend.h>
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#include <linux/io.h>
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#include <plat/cpu.h>
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#include <plat/pm.h>
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#include <plat/regs-timer.h>
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#include <mach/regs-irq.h>
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#include <mach/regs-clock.h>
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static struct sleep_save s5pv210_core_save[] = {
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/* Clock source */
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SAVE_ITEM(S5P_CLK_SRC0),
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SAVE_ITEM(S5P_CLK_SRC1),
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SAVE_ITEM(S5P_CLK_SRC2),
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SAVE_ITEM(S5P_CLK_SRC3),
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SAVE_ITEM(S5P_CLK_SRC4),
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SAVE_ITEM(S5P_CLK_SRC5),
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SAVE_ITEM(S5P_CLK_SRC6),
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/* Clock source Mask */
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SAVE_ITEM(S5P_CLK_SRC_MASK0),
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SAVE_ITEM(S5P_CLK_SRC_MASK1),
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/* Clock Divider */
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SAVE_ITEM(S5P_CLK_DIV0),
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SAVE_ITEM(S5P_CLK_DIV1),
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SAVE_ITEM(S5P_CLK_DIV2),
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SAVE_ITEM(S5P_CLK_DIV3),
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SAVE_ITEM(S5P_CLK_DIV4),
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SAVE_ITEM(S5P_CLK_DIV5),
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SAVE_ITEM(S5P_CLK_DIV6),
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SAVE_ITEM(S5P_CLK_DIV7),
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/* Clock Main Gate */
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SAVE_ITEM(S5P_CLKGATE_MAIN0),
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SAVE_ITEM(S5P_CLKGATE_MAIN1),
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SAVE_ITEM(S5P_CLKGATE_MAIN2),
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/* Clock source Peri Gate */
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SAVE_ITEM(S5P_CLKGATE_PERI0),
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SAVE_ITEM(S5P_CLKGATE_PERI1),
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/* Clock source SCLK Gate */
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SAVE_ITEM(S5P_CLKGATE_SCLK0),
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SAVE_ITEM(S5P_CLKGATE_SCLK1),
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/* Clock IP Clock gate */
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SAVE_ITEM(S5P_CLKGATE_IP0),
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SAVE_ITEM(S5P_CLKGATE_IP1),
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SAVE_ITEM(S5P_CLKGATE_IP2),
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SAVE_ITEM(S5P_CLKGATE_IP3),
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SAVE_ITEM(S5P_CLKGATE_IP4),
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/* Clock Blcok and Bus gate */
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SAVE_ITEM(S5P_CLKGATE_BLOCK),
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SAVE_ITEM(S5P_CLKGATE_BUS0),
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/* Clock ETC */
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SAVE_ITEM(S5P_CLK_OUT),
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SAVE_ITEM(S5P_MDNIE_SEL),
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/* PWM Register */
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SAVE_ITEM(S3C2410_TCFG0),
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SAVE_ITEM(S3C2410_TCFG1),
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SAVE_ITEM(S3C64XX_TINT_CSTAT),
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SAVE_ITEM(S3C2410_TCON),
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SAVE_ITEM(S3C2410_TCNTB(0)),
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SAVE_ITEM(S3C2410_TCMPB(0)),
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SAVE_ITEM(S3C2410_TCNTO(0)),
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};
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void s5pv210_cpu_suspend(void)
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{
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unsigned long tmp;
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/* issue the standby signal into the pm unit. Note, we
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* issue a write-buffer drain just in case */
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tmp = 0;
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asm("b 1f\n\t"
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".align 5\n\t"
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"1:\n\t"
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"mcr p15, 0, %0, c7, c10, 5\n\t"
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"mcr p15, 0, %0, c7, c10, 4\n\t"
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"wfi" : : "r" (tmp));
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/* we should never get past here */
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panic("sleep resumed to originator?");
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}
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static void s5pv210_pm_prepare(void)
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{
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unsigned int tmp;
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/* ensure at least INFORM0 has the resume address */
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__raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
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tmp = __raw_readl(S5P_SLEEP_CFG);
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tmp &= ~(S5P_SLEEP_CFG_OSC_EN | S5P_SLEEP_CFG_USBOSC_EN);
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__raw_writel(tmp, S5P_SLEEP_CFG);
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/* WFI for SLEEP mode configuration by SYSCON */
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tmp = __raw_readl(S5P_PWR_CFG);
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tmp &= S5P_CFG_WFI_CLEAN;
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tmp |= S5P_CFG_WFI_SLEEP;
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__raw_writel(tmp, S5P_PWR_CFG);
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/* SYSCON interrupt handling disable */
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tmp = __raw_readl(S5P_OTHERS);
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tmp |= S5P_OTHER_SYSC_INTOFF;
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__raw_writel(tmp, S5P_OTHERS);
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s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
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}
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static int s5pv210_pm_add(struct sys_device *sysdev)
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{
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pm_cpu_prep = s5pv210_pm_prepare;
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pm_cpu_sleep = s5pv210_cpu_suspend;
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return 0;
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}
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static int s5pv210_pm_resume(struct sys_device *dev)
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{
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u32 tmp;
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tmp = __raw_readl(S5P_OTHERS);
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tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF |\
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S5P_OTHERS_RET_MMC | S5P_OTHERS_RET_UART);
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__raw_writel(tmp , S5P_OTHERS);
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s3c_pm_do_restore_core(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
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return 0;
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}
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static struct sysdev_driver s5pv210_pm_driver = {
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.add = s5pv210_pm_add,
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.resume = s5pv210_pm_resume,
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};
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static __init int s5pv210_pm_drvinit(void)
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{
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return sysdev_driver_register(&s5pv210_sysclass, &s5pv210_pm_driver);
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}
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arch_initcall(s5pv210_pm_drvinit);
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170
arch/arm/mach-s5pv210/sleep.S
Normal file
170
arch/arm/mach-s5pv210/sleep.S
Normal file
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@ -0,0 +1,170 @@
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/* linux/arch/arm/plat-s5p/sleep.S
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* S5PV210 power Manager (Suspend-To-RAM) support
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* Based on S3C2410 sleep code by:
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* Ben Dooks, (c) 2004 Simtec Electronics
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*
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* Based on PXA/SA1100 sleep code by:
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* Nicolas Pitre, (c) 2002 Monta Vista Software Inc
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* Cliff Brake, (c) 2001
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/memory.h>
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.text
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/* s3c_cpu_save
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*
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* entry:
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* r0 = save address (virtual addr of s3c_sleep_save_phys)
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*/
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ENTRY(s3c_cpu_save)
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stmfd sp!, { r3 - r12, lr }
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mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mrc p15, 0, r5, c3, c0, 0 @ Domain ID
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mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
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mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
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mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control
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mrc p15, 0, r9, c1, c0, 0 @ Control register
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mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
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mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls
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mrc p15, 0, r12, c10, c2, 0 @ Read PRRR
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mrc p15, 0, r3, c10, c2, 1 @ READ NMRR
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stmia r0, { r3 - r13 }
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bl s3c_pm_cb_flushcache
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ldr r0, =pm_cpu_sleep
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ldr r0, [ r0 ]
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mov pc, r0
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resume_with_mmu:
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/*
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* After MMU is turned on, restore the previous MMU table.
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*/
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ldr r9 , =(PAGE_OFFSET - PHYS_OFFSET)
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add r4, r4, r9
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str r12, [r4]
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ldmfd sp!, { r3 - r12, pc }
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.ltorg
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.data
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.global s3c_sleep_save_phys
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s3c_sleep_save_phys:
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.word 0
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/* sleep magic, to allow the bootloader to check for an valid
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* image to resume to. Must be the first word before the
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* s3c_cpu_resume entry.
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*/
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.word 0x2bedf00d
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/* s3c_cpu_resume
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*
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* resume code entry for bootloader to call
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*
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* we must put this code here in the data segment as we have no
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* other way of restoring the stack pointer after sleep, and we
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* must not write to the code segment (code is read-only)
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*/
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ENTRY(s3c_cpu_resume)
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mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
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msr cpsr_c, r0
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mov r1, #0
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mcr p15, 0, r1, c8, c7, 0 @ invalidate TLBs
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mcr p15, 0, r1, c7, c5, 0 @ invalidate I Cache
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ldr r0, s3c_sleep_save_phys @ address of restore block
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ldmia r0, { r3 - r13 }
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mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mcr p15, 0, r5, c3, c0, 0 @ Domain ID
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mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control
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mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
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mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
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mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register
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mov r0, #0
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mcr p15, 0, r0, c8, c7, 0 @ Invalidate I & D TLB
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mov r0, #0 @ restore copro access
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mcr p15, 0, r11, c1, c0, 2 @ Co-processor access
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mcr p15, 0, r0, c7, c5, 4
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|
||||
mcr p15, 0, r12, c10, c2, 0 @ write PRRR
|
||||
mcr p15, 0, r3, c10, c2, 1 @ write NMRR
|
||||
|
||||
/*
|
||||
* In Cortex-A8, when MMU is turned on, the pipeline is flushed.
|
||||
* And there are no valid entries in the MMU table at this point.
|
||||
* So before turning on the MMU, the MMU entry for the DRAM address
|
||||
* range is added. After the MMU is turned on, the other entries
|
||||
* in the MMU table will be restored.
|
||||
*/
|
||||
|
||||
/* r6 = Translation Table BASE0 */
|
||||
mov r4, r6
|
||||
mov r4, r4, LSR #14
|
||||
mov r4, r4, LSL #14
|
||||
|
||||
/* Load address for adding to MMU table list */
|
||||
ldr r11, =0xE010F000 @ INFORM0 reg.
|
||||
ldr r10, [r11, #0]
|
||||
mov r10, r10, LSR #18
|
||||
bic r10, r10, #0x3
|
||||
orr r4, r4, r10
|
||||
|
||||
/* Calculate MMU table entry */
|
||||
mov r10, r10, LSL #18
|
||||
ldr r5, =0x40E
|
||||
orr r10, r10, r5
|
||||
|
||||
/* Back up originally data */
|
||||
ldr r12, [r4]
|
||||
|
||||
/* Add calculated MMU table entry into MMU table list */
|
||||
str r10, [r4]
|
||||
|
||||
ldr r2, =resume_with_mmu
|
||||
mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, etc
|
||||
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop @ second-to-last before mmu
|
||||
|
||||
mov pc, r2 @ go back to virtual address
|
||||
|
||||
.ltorg
|
||||
|
|
@ -19,6 +19,8 @@ obj-y += clock.o
|
|||
obj-y += irq.o
|
||||
obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o
|
||||
obj-$(CONFIG_S5P_GPIO_INT) += irq-gpioint.o
|
||||
obj-$(CONFIG_PM) += pm.o
|
||||
obj-$(CONFIG_PM) += irq-pm.o
|
||||
|
||||
# devices
|
||||
|
||||
|
|
|
|||
93
arch/arm/plat-s5p/irq-pm.c
Normal file
93
arch/arm/plat-s5p/irq-pm.c
Normal file
|
|
@ -0,0 +1,93 @@
|
|||
/* linux/arch/arm/plat-s5p/irq-pm.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Based on arch/arm/plat-s3c24xx/irq-pm.c,
|
||||
* Copyright (c) 2003,2004 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/sysdev.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/irqs.h>
|
||||
#include <plat/pm.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <mach/regs-gpio.h>
|
||||
#include <mach/regs-irq.h>
|
||||
|
||||
/* state for IRQs over sleep */
|
||||
|
||||
/* default is to allow for EINT0..EINT31, and IRQ_RTC_TIC, IRQ_RTC_ALARM,
|
||||
* as wakeup sources
|
||||
*
|
||||
* set bit to 1 in allow bitfield to enable the wakeup settings on it
|
||||
*/
|
||||
|
||||
unsigned long s3c_irqwake_intallow = 0x00000006L;
|
||||
unsigned long s3c_irqwake_eintallow = 0xffffffffL;
|
||||
|
||||
int s3c_irq_wake(unsigned int irqno, unsigned int state)
|
||||
{
|
||||
unsigned long irqbit;
|
||||
|
||||
switch (irqno) {
|
||||
case IRQ_RTC_TIC:
|
||||
case IRQ_RTC_ALARM:
|
||||
irqbit = 1 << (irqno + 1 - IRQ_RTC_ALARM);
|
||||
if (!state)
|
||||
s3c_irqwake_intmask |= irqbit;
|
||||
else
|
||||
s3c_irqwake_intmask &= ~irqbit;
|
||||
break;
|
||||
default:
|
||||
return -ENOENT;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct sleep_save eint_save[] = {
|
||||
SAVE_ITEM(S5P_EINT_CON(0)),
|
||||
SAVE_ITEM(S5P_EINT_CON(1)),
|
||||
SAVE_ITEM(S5P_EINT_CON(2)),
|
||||
SAVE_ITEM(S5P_EINT_CON(3)),
|
||||
|
||||
SAVE_ITEM(S5P_EINT_FLTCON(0)),
|
||||
SAVE_ITEM(S5P_EINT_FLTCON(1)),
|
||||
SAVE_ITEM(S5P_EINT_FLTCON(2)),
|
||||
SAVE_ITEM(S5P_EINT_FLTCON(3)),
|
||||
SAVE_ITEM(S5P_EINT_FLTCON(4)),
|
||||
SAVE_ITEM(S5P_EINT_FLTCON(5)),
|
||||
SAVE_ITEM(S5P_EINT_FLTCON(6)),
|
||||
SAVE_ITEM(S5P_EINT_FLTCON(7)),
|
||||
|
||||
SAVE_ITEM(S5P_EINT_MASK(0)),
|
||||
SAVE_ITEM(S5P_EINT_MASK(1)),
|
||||
SAVE_ITEM(S5P_EINT_MASK(2)),
|
||||
SAVE_ITEM(S5P_EINT_MASK(3)),
|
||||
};
|
||||
|
||||
int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
|
||||
{
|
||||
s3c_pm_do_save(eint_save, ARRAY_SIZE(eint_save));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int s3c24xx_irq_resume(struct sys_device *dev)
|
||||
{
|
||||
s3c_pm_do_restore(eint_save, ARRAY_SIZE(eint_save));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
52
arch/arm/plat-s5p/pm.c
Normal file
52
arch/arm/plat-s5p/pm.c
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/* linux/arch/arm/plat-s5p/pm.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* S5P Power Manager (Suspend-To-RAM) support
|
||||
*
|
||||
* Based on arch/arm/plat-s3c24xx/pm.c
|
||||
* Copyright (c) 2004,2006 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/suspend.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
#define PFX "s5p pm: "
|
||||
|
||||
/* s3c_pm_check_resume_pin
|
||||
*
|
||||
* check to see if the pin is configured correctly for sleep mode, and
|
||||
* make any necessary adjustments if it is not
|
||||
*/
|
||||
|
||||
static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
|
||||
{
|
||||
/* nothing here yet */
|
||||
}
|
||||
|
||||
/* s3c_pm_configure_extint
|
||||
*
|
||||
* configure all external interrupt pins
|
||||
*/
|
||||
|
||||
void s3c_pm_configure_extint(void)
|
||||
{
|
||||
/* nothing here yet */
|
||||
}
|
||||
|
||||
void s3c_pm_restore_core(void)
|
||||
{
|
||||
/* nothing here yet */
|
||||
}
|
||||
|
||||
void s3c_pm_save_core(void)
|
||||
{
|
||||
/* nothing here yet */
|
||||
}
|
||||
|
||||
|
|
@ -192,7 +192,7 @@ struct s3c_gpio_pm s3c_gpio_pm_2bit = {
|
|||
.resume = s3c_gpio_pm_2bit_resume,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ARCH_S3C64XX
|
||||
#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P)
|
||||
static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip)
|
||||
{
|
||||
chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
|
||||
|
|
@ -302,7 +302,7 @@ struct s3c_gpio_pm s3c_gpio_pm_4bit = {
|
|||
.save = s3c_gpio_pm_4bit_save,
|
||||
.resume = s3c_gpio_pm_4bit_resume,
|
||||
};
|
||||
#endif /* CONFIG_ARCH_S3C64XX */
|
||||
#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P */
|
||||
|
||||
/**
|
||||
* s3c_pm_save_gpio() - save gpio chip data for suspend
|
||||
|
|
|
|||
Loading…
Reference in a new issue