MLK-16784-4 sound: asoc: add micfil cpu-dai in iMX8MM
Add micfil cpu-dai for iMX8MM. The MICFIL digital interface provides a 16-bit audio signal from a PDM microphone bitstream in a configurable output sampling rate. Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>pull/10/head
Cosmin-Gabriel Samoila
Jason Liu
parent
adb3169228
commit
ea341b3392
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@ -74,6 +74,15 @@ config SND_SOC_FSL_ESAI
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This option is only useful for out-of-tree drivers since
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in-tree drivers select it automatically.
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config SND_SOC_FSL_MICFIL
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tristate "Pulse Density Modulation Microphone Interface (MICFIL) module support"
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select REGMAP_MMIO
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select SND_SOC_IMX_PCM_DMA if SND_IMX_SOC != n
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select SND_SOC_GENERIC_DMAENGINE_PCM
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help
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Say Y if you want to add Pulse Density Modulation microphone
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interface (MICFIL) support for NXP.
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config SND_SOC_FSL_RPMSG_I2S
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tristate "I2S base on the RPMSG support"
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depends on RPMSG
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@ -27,6 +27,8 @@ snd-soc-fsl-dma-objs := fsl_dma.o
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snd-soc-fsl-rpmsg-i2s-objs := fsl_rpmsg_i2s.o
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snd-soc-fsl-hdmi-objs := fsl_hdmi.o
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snd-soc-fsl-asoc-card-objs := fsl-asoc-card.o
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snd-soc-fsl-micfil-objs := fsl_micfil.o
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obj-$(CONFIG_SND_SOC_FSL_ACM) += snd-soc-fsl-acm.o
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obj-$(CONFIG_SND_SOC_FSL_AMIX) += snd-soc-fsl-amix.o
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obj-$(CONFIG_SND_SOC_FSL_ASRC) += snd-soc-fsl-asrc.o
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@ -40,6 +42,7 @@ obj-$(CONFIG_SND_SOC_FSL_HDMI) += snd-soc-fsl-hdmi.o
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obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
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obj-$(CONFIG_SND_SOC_FSL_RPMSG_I2S) += snd-soc-fsl-rpmsg-i2s.o
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obj-$(CONFIG_SND_SOC_FSL_ASOC_CARD) += snd-soc-fsl-asoc-card.o
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obj-$(CONFIG_SND_SOC_FSL_MICFIL) += snd-soc-fsl-micfil.o
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# MPC5200 Platform Support
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obj-$(CONFIG_SND_MPC52xx_DMA) += mpc5200_dma.o
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@ -0,0 +1,787 @@
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/*
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* Copyright 2018 NXP
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/soc.h>
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#include <sound/pcm.h>
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#include "fsl_micfil.h"
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#include "imx-pcm.h"
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#define FSL_MICFIL_RATES SNDRV_PCM_RATE_8000_192000
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#define FSL_MICFIL_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
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SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S20_3LE | \
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SNDRV_PCM_FMTBIT_S24_LE)
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struct fsl_micfil {
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struct platform_device *pdev;
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struct regmap *regmap;
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const struct fsl_micfil_soc_data *soc;
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struct clk *mclk;
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struct snd_dmaengine_dai_dma_data dma_params_rx;
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unsigned int dataline;
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bool slave_mode;
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char name[32];
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unsigned int mclk_streams;
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};
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struct fsl_micfil_soc_data {
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unsigned int fifos;
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unsigned int fifo_depth;
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unsigned int dataline;
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bool imx;
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};
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static struct fsl_micfil_soc_data fsl_micfil_imx8mm = {
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.imx = true,
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.fifos = 8,
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.fifo_depth = 8,
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.dataline = 0xf,
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};
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static const struct of_device_id fsl_micfil_dt_ids[] = {
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{ .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm },
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{}
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};
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MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);
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static const struct snd_soc_component_driver fsl_micfil_component = {
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.name = "fsl-micfil",
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};
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static inline unsigned int get_pdm_clk(struct fsl_micfil *micfil,
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unsigned int rate);
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static inline unsigned int get_clk_div(struct fsl_micfil *micfil,
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unsigned int rate)
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{
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u32 ctrl2_reg;
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unsigned long mclk_rate;
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unsigned int clk_div;
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unsigned int osr;
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regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
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osr = 16 - ((ctrl2_reg & MICFIL_CTRL2_CICOSR_MASK)
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>> MICFIL_CTRL2_CICOSR_SHIFT);
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mclk_rate = clk_get_rate(micfil->mclk);
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clk_div = mclk_rate / (get_pdm_clk(micfil, rate) * 2);
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return clk_div;
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}
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static inline unsigned int get_pdm_clk(struct fsl_micfil *micfil,
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unsigned int rate)
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{
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u32 ctrl2_reg;
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unsigned int qsel, osr;
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unsigned int bclk;
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regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
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osr = 16 - ((ctrl2_reg & MICFIL_CTRL2_CICOSR_MASK)
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>> MICFIL_CTRL2_CICOSR_SHIFT);
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regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
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qsel = ((ctrl2_reg & MICFIL_CTRL2_QSEL_MASK)
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>> MICFIL_CTRL2_QSEL_SHIFT);
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switch (qsel) {
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case MICFIL_HIGH_QUALITY:
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bclk = rate * 8 * osr;
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break;
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case MICFIL_MEDIUM_QUALITY:
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case MICFIL_VLOW0_QUALITY:
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bclk = rate * 4 * osr;
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break;
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case MICFIL_LOW_QUALITY:
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case MICFIL_VLOW1_QUALITY:
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bclk = rate * 2 * osr;
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break;
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case MICFIL_VLOW2_QUALITY:
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bclk = rate * osr;
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break;
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default:
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bclk = 0;
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break;
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}
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return bclk;
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}
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/* Check if BSY_FIL flag in STAT register is set.
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* Read this flag for max 10 times, sleep 100ms
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* after each read and return error if it's not
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* cleared after 10 retries.
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*/
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static int fsl_micfil_bsy(struct device *dev)
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{
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struct fsl_micfil *micfil = dev_get_drvdata(dev);
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int i;
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int ret;
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u32 stat;
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for (i = 0; i < MICFIL_MAX_RETRY; i++) {
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ret = regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat);
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if (ret) {
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dev_err(dev, "failed to read register %d\n",
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REG_MICFIL_STAT);
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return ret;
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}
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if (stat & MICFIL_STAT_BSY_FIL_MASK)
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usleep_range(MICFIL_SLEEP_MIN,
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MICFIL_SLEEP_MAX);
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else
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return 0;
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}
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return -EINVAL;
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}
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/* The SRES is a self-negated bit which provides the CPU with the
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* capability to initialize the PDM Interface module through the
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* slave-bus interface. This bit always reads as zero, and this
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* bit is only effective when MDIS is cleared
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*/
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static int fsl_micfil_reset(struct device *dev)
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{
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struct fsl_micfil *micfil = dev_get_drvdata(dev);
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int ret;
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ret = regmap_update_bits(micfil->regmap,
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REG_MICFIL_CTRL1,
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MICFIL_CTRL1_MDIS_MASK,
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0);
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if (ret) {
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dev_err(dev, "failed to clear MDIS bit %d\n", ret);
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return ret;
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}
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ret = regmap_update_bits(micfil->regmap,
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REG_MICFIL_CTRL1,
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MICFIL_CTRL1_SRES_MASK,
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MICFIL_CTRL1_SRES);
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if (ret) {
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dev_err(dev, "failed to reset MICFIL: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static int fsl_micfil_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
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struct device *dev = &micfil->pdev->dev;
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if (!micfil) {
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dev_err(dev, "micfil dai priv_data not set\n");
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return -EINVAL;
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}
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return 0;
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}
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static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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{
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struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
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struct device *dev = &micfil->pdev->dev;
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int ret;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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ret = fsl_micfil_reset(dev);
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if (ret) {
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dev_err(dev, "failed to soft reset\n");
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return ret;
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}
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/* DMA Interrupt Selection - DISEL bits
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* 00 - DMA and IRQ disabled
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* 01 - DMA req enabled
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* 10 - IRQ enabled
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* 11 - reserved
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*/
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ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
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MICFIL_CTRL1_DISEL_MASK,
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(1 << MICFIL_CTRL1_DISEL_SHIFT));
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if (ret) {
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dev_err(dev, "failed to update DISEL bits\n");
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return ret;
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}
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/* Enable the module */
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ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
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MICFIL_CTRL1_PDMIEN_MASK,
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MICFIL_CTRL1_PDMIEN);
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if (ret) {
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dev_err(dev, "failed to enable the module\n");
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return ret;
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}
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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/* Disable the module */
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ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
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MICFIL_CTRL1_PDMIEN_MASK,
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0);
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if (ret) {
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dev_err(dev, "failed to enable the module\n");
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return ret;
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}
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ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
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MICFIL_CTRL1_DISEL_MASK,
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(0 << MICFIL_CTRL1_DISEL_SHIFT));
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if (ret) {
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dev_err(dev, "failed to update DISEL bits\n");
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return ret;
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}
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
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unsigned int channels = params_channels(params);
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unsigned int rate = params_rate(params);
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struct device *dev = &micfil->pdev->dev;
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unsigned int clk_div;
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int ret;
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/* 1. Disable the module */
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ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
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MICFIL_CTRL1_PDMIEN_MASK, 0);
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if (ret) {
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dev_err(dev, "failed to disable the module\n");
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return ret;
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}
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/* enable channels */
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ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
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0xFF, ((1 << channels) - 1));
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if (ret) {
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dev_err(dev, "failed to enable channels %d, reg 0x%X\n", ret,
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REG_MICFIL_CTRL1);
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return ret;
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}
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/* The following bits must not change
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* when BSY_FIL is asserted
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*/
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if (!fsl_micfil_bsy(dev)) {
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/* set CICOSR */
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ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
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MICFIL_CTRL2_CICOSR_MASK,
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MICFIL_CTRL2_OSR_DEFAULT);
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if (ret) {
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dev_err(dev, "failed to set CICOSR in reg 0x%X\n",
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REG_MICFIL_CTRL2);
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return ret;
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}
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/* Do not enable the clock if it is already enabled */
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if (!(micfil->mclk_streams & BIT(substream->stream))) {
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ret = clk_prepare_enable(micfil->mclk);
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if (ret)
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return ret;
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micfil->mclk_streams |= BIT(substream->stream);
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}
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/* set CLK_DIV */
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clk_div = get_clk_div(micfil, rate);
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ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
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MICFIL_CTRL2_CLKDIV_MASK, clk_div);
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if (ret) {
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dev_err(dev, "failed to set CLKDIV in reg 0x%X\n",
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REG_MICFIL_CTRL2);
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return ret;
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}
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}
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micfil->dma_params_rx.fifo_num = channels;
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return 0;
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}
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static int fsl_micfil_hw_free(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
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if (!micfil->slave_mode &&
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micfil->mclk_streams & BIT(substream->stream)) {
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clk_disable_unprepare(micfil->mclk);
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micfil->mclk_streams &= ~BIT(substream->stream);
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}
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return 0;
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}
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static int fsl_micfil_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
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unsigned int freq, int dir)
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{
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struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
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struct device *dev = &micfil->pdev->dev;
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int ret;
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if (!freq)
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return 0;
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ret = clk_set_rate(micfil->mclk, freq);
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if (ret < 0)
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dev_err(dev, "failed to set mclk[%lu] to rate %u\n",
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clk_get_rate(micfil->mclk), freq);
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return ret;
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}
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static int fsl_micfil_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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{
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struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
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/* DAI MODE */
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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break;
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default:
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return -EINVAL;
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}
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/* DAI CLK INVERSION */
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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break;
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default:
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return -EINVAL;
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}
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micfil->slave_mode = false;
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return 0;
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}
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static struct snd_soc_dai_ops fsl_micfil_dai_ops = {
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.startup = fsl_micfil_startup,
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.trigger = fsl_micfil_trigger,
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.hw_params = fsl_micfil_hw_params,
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.hw_free = fsl_micfil_hw_free,
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.set_sysclk = fsl_micfil_set_dai_sysclk,
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.set_fmt = fsl_micfil_set_dai_fmt,
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};
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static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
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{
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struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
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struct device *dev = cpu_dai->dev;
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unsigned int val;
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int ret;
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/* set qsel to medium */
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ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
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MICFIL_CTRL2_QSEL_MASK, MICFIL_MEDIUM_QUALITY);
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if (ret) {
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dev_err(dev, "failed to set quality mode bits, reg 0x%X\n",
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REG_MICFIL_CTRL2);
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return ret;
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}
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||||
regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x77777777);
|
||||
|
||||
snd_soc_dai_init_dma_data(cpu_dai, NULL,
|
||||
&micfil->dma_params_rx);
|
||||
|
||||
/* FIFO Watermark Control - FIFOWMK*/
|
||||
val = MICFIL_FIFO_CTRL_FIFOWMK(micfil->soc->fifo_depth) - 1;
|
||||
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
|
||||
MICFIL_FIFO_CTRL_FIFOWMK_MASK,
|
||||
val);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to set FIFOWMK\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
snd_soc_dai_set_drvdata(cpu_dai, micfil);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct snd_soc_dai_driver fsl_micfil_dai = {
|
||||
.probe = fsl_micfil_dai_probe,
|
||||
.capture = {
|
||||
.stream_name = "CPU-Capture",
|
||||
.channels_min = 1,
|
||||
.channels_max = 8,
|
||||
.rates = FSL_MICFIL_RATES,
|
||||
.formats = FSL_MICFIL_FORMATS,
|
||||
},
|
||||
.ops = &fsl_micfil_dai_ops,
|
||||
};
|
||||
|
||||
/* REG MAP */
|
||||
static const struct reg_default fsl_micfil_reg_defaults[] = {
|
||||
{REG_MICFIL_CTRL1, 0x00000000},
|
||||
{REG_MICFIL_CTRL2, 0x00000000},
|
||||
{REG_MICFIL_STAT, 0x00000000},
|
||||
{REG_MICFIL_FIFO_CTRL, 0x00000007},
|
||||
{REG_MICFIL_FIFO_STAT, 0x00000000},
|
||||
{REG_MICFIL_DATACH0, 0x00000000},
|
||||
{REG_MICFIL_DATACH1, 0x00000000},
|
||||
{REG_MICFIL_DATACH2, 0x00000000},
|
||||
{REG_MICFIL_DATACH3, 0x00000000},
|
||||
{REG_MICFIL_DATACH4, 0x00000000},
|
||||
{REG_MICFIL_DATACH5, 0x00000000},
|
||||
{REG_MICFIL_DATACH6, 0x00000000},
|
||||
{REG_MICFIL_DATACH7, 0x00000000},
|
||||
{REG_MICFIL_DC_CTRL, 0x00000000},
|
||||
{REG_MICFIL_OUT_CTRL, 0x00000000},
|
||||
{REG_MICFIL_OUT_STAT, 0x00000000},
|
||||
{REG_MICFIL_VAD0_CTRL1, 0x00000000},
|
||||
{REG_MICFIL_VAD0_CTRL2, 0x000A0000},
|
||||
{REG_MICFIL_VAD0_STAT, 0x00000000},
|
||||
{REG_MICFIL_VAD0_SCONFIG, 0x00000000},
|
||||
{REG_MICFIL_VAD0_NCONFIG, 0x80000000},
|
||||
{REG_MICFIL_VAD0_NDATA, 0x00000000},
|
||||
{REG_MICFIL_VAD0_ZCD, 0x00000004},
|
||||
};
|
||||
|
||||
static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg)
|
||||
{
|
||||
switch (reg) {
|
||||
case REG_MICFIL_CTRL1:
|
||||
case REG_MICFIL_CTRL2:
|
||||
case REG_MICFIL_STAT:
|
||||
case REG_MICFIL_FIFO_CTRL:
|
||||
case REG_MICFIL_FIFO_STAT:
|
||||
case REG_MICFIL_DATACH0:
|
||||
case REG_MICFIL_DATACH1:
|
||||
case REG_MICFIL_DATACH2:
|
||||
case REG_MICFIL_DATACH3:
|
||||
case REG_MICFIL_DATACH4:
|
||||
case REG_MICFIL_DATACH5:
|
||||
case REG_MICFIL_DATACH6:
|
||||
case REG_MICFIL_DATACH7:
|
||||
case REG_MICFIL_DC_CTRL:
|
||||
case REG_MICFIL_OUT_CTRL:
|
||||
case REG_MICFIL_OUT_STAT:
|
||||
case REG_MICFIL_VAD0_CTRL1:
|
||||
case REG_MICFIL_VAD0_CTRL2:
|
||||
case REG_MICFIL_VAD0_STAT:
|
||||
case REG_MICFIL_VAD0_SCONFIG:
|
||||
case REG_MICFIL_VAD0_NCONFIG:
|
||||
case REG_MICFIL_VAD0_NDATA:
|
||||
case REG_MICFIL_VAD0_ZCD:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg)
|
||||
{
|
||||
switch (reg) {
|
||||
case REG_MICFIL_CTRL1:
|
||||
case REG_MICFIL_CTRL2:
|
||||
case REG_MICFIL_STAT: /* Write 1 to Clear */
|
||||
case REG_MICFIL_FIFO_CTRL:
|
||||
case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */
|
||||
case REG_MICFIL_DC_CTRL:
|
||||
case REG_MICFIL_OUT_CTRL:
|
||||
case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */
|
||||
case REG_MICFIL_VAD0_CTRL1:
|
||||
case REG_MICFIL_VAD0_CTRL2:
|
||||
case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */
|
||||
case REG_MICFIL_VAD0_SCONFIG:
|
||||
case REG_MICFIL_VAD0_NCONFIG:
|
||||
case REG_MICFIL_VAD0_ZCD:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg)
|
||||
{
|
||||
switch (reg) {
|
||||
case REG_MICFIL_CTRL1:
|
||||
case REG_MICFIL_DATACH0:
|
||||
case REG_MICFIL_DATACH1:
|
||||
case REG_MICFIL_DATACH2:
|
||||
case REG_MICFIL_DATACH3:
|
||||
case REG_MICFIL_DATACH4:
|
||||
case REG_MICFIL_DATACH5:
|
||||
case REG_MICFIL_DATACH6:
|
||||
case REG_MICFIL_DATACH7:
|
||||
case REG_MICFIL_VAD0_NDATA:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct regmap_config fsl_micfil_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
|
||||
.max_register = REG_MICFIL_VAD0_ZCD,
|
||||
.reg_defaults = fsl_micfil_reg_defaults,
|
||||
.num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults),
|
||||
.readable_reg = fsl_micfil_readable_reg,
|
||||
.volatile_reg = fsl_micfil_volatile_reg,
|
||||
.writeable_reg = fsl_micfil_writeable_reg,
|
||||
.cache_type = REGCACHE_RBTREE,
|
||||
};
|
||||
|
||||
/* END OF REGMAP */
|
||||
|
||||
static irqreturn_t micfil_isr(int irq, void *devid)
|
||||
{
|
||||
struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
|
||||
struct platform_device *pdev = micfil->pdev;
|
||||
u32 stat_reg;
|
||||
u32 ctrl1_reg;
|
||||
bool dma_enabled;
|
||||
int i;
|
||||
|
||||
regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
|
||||
regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg);
|
||||
dma_enabled = MICFIL_DMA_ENABLED(ctrl1_reg);
|
||||
|
||||
if (stat_reg & MICFIL_STAT_BSY_FIL_MASK)
|
||||
dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n");
|
||||
|
||||
if (stat_reg & MICFIL_STAT_FIR_RDY_MASK)
|
||||
dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n");
|
||||
|
||||
if (stat_reg & MICFIL_STAT_LOWFREQF_MASK) {
|
||||
dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n");
|
||||
regmap_update_bits(micfil->regmap, REG_MICFIL_STAT,
|
||||
MICFIL_STAT_LOWFREQF_MASK, 1);
|
||||
}
|
||||
|
||||
/* Channel 0-7 Output Data Flags */
|
||||
for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) {
|
||||
if (stat_reg & MICFIL_STAT_CHXF_MASK(i))
|
||||
dev_dbg(&pdev->dev,
|
||||
"isr: Data available in Data Channel %d\n", i);
|
||||
/* if DMA is not enabled, field must be written with 1
|
||||
* to clear
|
||||
*/
|
||||
if (!dma_enabled)
|
||||
regmap_update_bits(micfil->regmap,
|
||||
REG_MICFIL_STAT,
|
||||
MICFIL_STAT_CHXF_MASK(i),
|
||||
1);
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int fsl_micfil_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
const struct of_device_id *of_id;
|
||||
struct fsl_micfil *micfil;
|
||||
struct resource *res;
|
||||
void __iomem *regs;
|
||||
int irq, ret;
|
||||
unsigned long irqflag = 0;
|
||||
|
||||
micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL);
|
||||
if (!micfil)
|
||||
return -ENOMEM;
|
||||
|
||||
micfil->pdev = pdev;
|
||||
strncpy(micfil->name, np->name, sizeof(micfil->name) - 1);
|
||||
|
||||
of_id = of_match_device(fsl_micfil_dt_ids, &pdev->dev);
|
||||
if (!of_id || !of_id->data)
|
||||
return -EINVAL;
|
||||
|
||||
micfil->soc = of_id->data;
|
||||
|
||||
/* ipg_clk is used to control the registers
|
||||
* ipg_clk_app is used to operate the filter
|
||||
*/
|
||||
micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app");
|
||||
if (IS_ERR(micfil->mclk)) {
|
||||
dev_err(&pdev->dev, "failed to get core clock: %ld\n",
|
||||
PTR_ERR(micfil->mclk));
|
||||
return PTR_ERR(micfil->mclk);
|
||||
}
|
||||
|
||||
/* init regmap */
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
regs = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(regs))
|
||||
return PTR_ERR(regs);
|
||||
|
||||
micfil->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
|
||||
"ipg_clk",
|
||||
regs,
|
||||
&fsl_micfil_regmap_config);
|
||||
if (IS_ERR(micfil->regmap)) {
|
||||
dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n",
|
||||
PTR_ERR(micfil->regmap));
|
||||
return PTR_ERR(micfil->regmap);
|
||||
}
|
||||
|
||||
/* dataline mask for RX */
|
||||
ret = of_property_read_u32_index(np,
|
||||
"fsl,dataline",
|
||||
0,
|
||||
&micfil->dataline);
|
||||
if (ret)
|
||||
micfil->dataline = 1;
|
||||
|
||||
if (micfil->dataline & (~micfil->soc->dataline)) {
|
||||
dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n",
|
||||
micfil->soc->dataline);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* get IRQs */
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
|
||||
return irq;
|
||||
}
|
||||
|
||||
if (of_property_read_bool(np, "shared-interrupt"))
|
||||
irqflag = IRQF_SHARED;
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, irq, micfil_isr, irqflag,
|
||||
micfil->name, micfil);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
|
||||
return ret;
|
||||
}
|
||||
|
||||
micfil->slave_mode = false;
|
||||
|
||||
micfil->dma_params_rx.chan_name = "rx";
|
||||
micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0;
|
||||
micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
|
||||
|
||||
platform_set_drvdata(pdev, micfil);
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
|
||||
regcache_cache_only(micfil->regmap, true);
|
||||
|
||||
ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component,
|
||||
&fsl_micfil_dai, 1);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to register component %s\n",
|
||||
fsl_micfil_component.name);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (micfil->soc->imx)
|
||||
ret = imx_pcm_platform_register(&pdev->dev);
|
||||
else
|
||||
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
|
||||
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to pcm register\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsl_micfil_remove(struct platform_device *pdev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int __maybe_unused fsl_micfil_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct fsl_micfil *micfil = dev_get_drvdata(dev);
|
||||
|
||||
regcache_cache_only(micfil->regmap, true);
|
||||
|
||||
if (micfil->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
|
||||
clk_disable_unprepare(micfil->mclk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __maybe_unused fsl_micfil_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct fsl_micfil *micfil = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
/* enable mclk */
|
||||
if (micfil->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) {
|
||||
ret = clk_prepare_enable(micfil->mclk);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to enable mclk");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
regcache_cache_only(micfil->regmap, false);
|
||||
regcache_mark_dirty(micfil->regmap);
|
||||
regcache_sync(micfil->regmap);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_PM_SLEEP */
|
||||
|
||||
static const struct dev_pm_ops fsl_micfil_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(fsl_micfil_runtime_suspend,
|
||||
fsl_micfil_runtime_resume,
|
||||
NULL)
|
||||
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
||||
pm_runtime_force_resume)
|
||||
};
|
||||
|
||||
static struct platform_driver fsl_micfil_driver = {
|
||||
.probe = fsl_micfil_probe,
|
||||
.remove = fsl_micfil_remove,
|
||||
.driver = {
|
||||
.name = "fsl-micfil-dai",
|
||||
.pm = &fsl_micfil_pm_ops,
|
||||
.of_match_table = fsl_micfil_dt_ids,
|
||||
},
|
||||
};
|
||||
module_platform_driver(fsl_micfil_driver);
|
||||
|
||||
MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>");
|
||||
MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -0,0 +1,136 @@
|
|||
/*
|
||||
* fsl_micfil.h - PDM Microphone Interface for the NXP i.MX SoC
|
||||
*
|
||||
* Copyright (C) 2018 NXP
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef _FSL_MICFIL_H
|
||||
#define _FSL_MICFIL_H
|
||||
|
||||
/* MICFIL Register Map */
|
||||
#define REG_MICFIL_CTRL1 0x00
|
||||
#define REG_MICFIL_CTRL2 0x04
|
||||
#define REG_MICFIL_STAT 0x08
|
||||
#define REG_MICFIL_FIFO_CTRL 0x10
|
||||
#define REG_MICFIL_FIFO_STAT 0x14
|
||||
#define REG_MICFIL_DATACH0 0x24
|
||||
#define REG_MICFIL_DATACH1 0x28
|
||||
#define REG_MICFIL_DATACH2 0x2C
|
||||
#define REG_MICFIL_DATACH3 0x30
|
||||
#define REG_MICFIL_DATACH4 0x34
|
||||
#define REG_MICFIL_DATACH5 0x38
|
||||
#define REG_MICFIL_DATACH6 0x3C
|
||||
#define REG_MICFIL_DATACH7 0x40
|
||||
#define REG_MICFIL_DC_CTRL 0x64
|
||||
#define REG_MICFIL_OUT_CTRL 0x74
|
||||
#define REG_MICFIL_OUT_STAT 0x7C
|
||||
#define REG_MICFIL_VAD0_CTRL1 0x90
|
||||
#define REG_MICFIL_VAD0_CTRL2 0x94
|
||||
#define REG_MICFIL_VAD0_STAT 0x98
|
||||
#define REG_MICFIL_VAD0_SCONFIG 0x9C
|
||||
#define REG_MICFIL_VAD0_NCONFIG 0xA0
|
||||
#define REG_MICFIL_VAD0_NDATA 0xA4
|
||||
#define REG_MICFIL_VAD0_ZCD 0xA8
|
||||
|
||||
/* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */
|
||||
#define MICFIL_CTRL1_MDIS_SHIFT 31
|
||||
#define MICFIL_CTRL1_MDIS_MASK BIT(MICFIL_CTRL1_MDIS_SHIFT)
|
||||
#define MICFIL_CTRL1_MDIS BIT(MICFIL_CTRL1_MDIS_SHIFT)
|
||||
#define MICFIL_CTRL1_DOZEN_SHIFT 30
|
||||
#define MICFIL_CTRL1_DOZEN_MASK BIT(MICFIL_CTRL1_DOZEN_SHIFT)
|
||||
#define MICFIL_CTRL1_DOZEN BIT(MICFIL_CTRL1_DOZEN_SHIFT)
|
||||
#define MICFIL_CTRL1_PDMIEN_SHIFT 29
|
||||
#define MICFIL_CTRL1_PDMIEN_MASK BIT(MICFIL_CTRL1_PDMIEN_SHIFT)
|
||||
#define MICFIL_CTRL1_PDMIEN BIT(MICFIL_CTRL1_PDMIEN_SHIFT)
|
||||
#define MICFIL_CTRL1_DBG_SHIFT 28
|
||||
#define MICFIL_CTRL1_DBG_MASK BIT(MICFIL_CTRL1_DBG_SHIFT)
|
||||
#define MICFIL_CTRL1_DBG BIT(MICFIL_CTRL1_DBG_SHIFT)
|
||||
#define MICFIL_CTRL1_SRES_SHIFT 27
|
||||
#define MICFIL_CTRL1_SRES_MASK BIT(MICFIL_CTRL1_SRES_SHIFT)
|
||||
#define MICFIL_CTRL1_SRES BIT(MICFIL_CTRL1_SRES_SHIFT)
|
||||
#define MICFIL_CTRL1_DBGE_SHIFT 26
|
||||
#define MICFIL_CTRL1_DBGE_MASK BIT(MICFIL_CTRL1_DBGE_SHIFT)
|
||||
#define MICFIL_CTRL1_DBGE BIT(MICFIL_CTRL1_DBGE_SHIFT)
|
||||
#define MICFIL_CTRL1_DISEL_SHIFT 24
|
||||
#define MICFIL_CTRL1_DISEL_WIDTH 2
|
||||
#define MICFIL_CTRL1_DISEL_MASK ((BIT(MICFIL_CTRL1_DISEL_WIDTH) - 1) \
|
||||
<< MICFIL_CTRL1_DISEL_SHIFT)
|
||||
#define MICFIL_CTRL1_DISEL(v) (((v) << MICFIL_CTRL1_DISEL_SHIFT) \
|
||||
& MICFIL_CTRL1_DISEL_MASK)
|
||||
#define MICFIL_CTRL1_ERREN_SHIFT 23
|
||||
#define MICFIL_CTRL1_ERREN_MASK BIT(MICFIL_CTRL1_ERREN_SHIFT)
|
||||
#define MICFIL_CTRL1_ERREN BIT(MICFIL_CTRL1_ERREN_SHIFT)
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#define MICFIL_CTRL1_CHEN_SHIFT 0
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#define MICFIL_CTRL1_CHEN_WIDTH 8
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#define MICFIL_CTRL1_CHEN_MASK(x) (BIT(x) << MICFIL_CTRL1_CHEN_SHIFT)
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#define MICFIL_CTRL1_CHEN(x) (MICFIL_CTRL1_CHEN_MASK(x))
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/* MICFIL Control Register 2 -- REG_MICFILL_CTRL2 0x04 */
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#define MICFIL_CTRL2_QSEL_SHIFT 25
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#define MICFIL_CTRL2_QSEL_WIDTH 3
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#define MICFIL_CTRL2_QSEL_MASK ((BIT(MICFIL_CTRL2_QSEL_WIDTH) - 1) \
|
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<< MICFIL_CTRL2_QSEL_SHIFT)
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#define MICFIL_HIGH_QUALITY BIT(MICFIL_CTRL2_QSEL_SHIFT)
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#define MICFIL_MEDIUM_QUALITY (0 << MICFIL_CTRL2_QSEL_SHIFT)
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#define MICFIL_LOW_QUALITY (7 << MICFIL_CTRL2_QSEL_SHIFT)
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#define MICFIL_VLOW0_QUALITY (6 << MICFIL_CTRL2_QSEL_SHIFT)
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#define MICFIL_VLOW1_QUALITY (5 << MICFIL_CTRL2_QSEL_SHIFT)
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#define MICFIL_VLOW2_QUALITY (4 << MICFIL_CTRL2_QSEL_SHIFT)
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#define MICFIL_CTRL2_CICOSR_SHIFT 16
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#define MICFIL_CTRL2_CICOSR_WIDTH 4
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#define MICFIL_CTRL2_CICOSR_MASK ((BIT(MICFIL_CTRL2_CICOSR_WIDTH) - 1) \
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||||
<< MICFIL_CTRL2_CICOSR_SHIFT)
|
||||
#define MICFIL_CTRL2_CICOSR(v) (((v) << MICFIL_CTRL2_CICOSR_SHIFT) \
|
||||
& MICFIL_CTRL2_CICOSR_MASK)
|
||||
#define MICFIL_CTRL2_CLKDIV_SHIFT 0
|
||||
#define MICFIL_CTRL2_CLKDIV_WIDTH 8
|
||||
#define MICFIL_CTRL2_CLKDIV_MASK ((BIT(MICFIL_CTRL2_CLKDIV_WIDTH) - 1) \
|
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<< MICFIL_CTRL2_CLKDIV_SHIFT)
|
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#define MICFIL_CTRL2_CLKDIV(v) (((v) << MICFIL_CTRL2_CLKDIV_SHIFT) \
|
||||
& MICFIL_CTRL2_CLKDIV_MASK)
|
||||
|
||||
/* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */
|
||||
#define MICFIL_STAT_BSY_FIL_SHIFT 31
|
||||
#define MICFIL_STAT_BSY_FIL_MASK BIT(MICFIL_STAT_BSY_FIL_SHIFT)
|
||||
#define MICFIL_STAT_BSY_FIL BIT(MICFIL_STAT_BSY_FIL_SHIFT)
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||||
#define MICFIL_STAT_FIR_RDY_SHIFT 30
|
||||
#define MICFIL_STAT_FIR_RDY_MASK BIT(MICFIL_STAT_FIR_RDY_SHIFT)
|
||||
#define MICFIL_STAT_FIR_RDY BIT(MICFIL_STAT_FIR_RDY_SHIFT)
|
||||
#define MICFIL_STAT_LOWFREQF_SHIFT 29
|
||||
#define MICFIL_STAT_LOWFREQF_MASK BIT(MICFIL_STAT_LOWFREQF_SHIFT)
|
||||
#define MICFIL_STAT_LOWFREQF BIT(MICFIL_STAT_LOWFREQF_SHIFT)
|
||||
#define MICFIL_STAT_CHXF_SHIFT(v) (v)
|
||||
#define MICFIL_STAT_CHXF_MASK(v) BIT(MICFIL_STAT_CHXF_SHIFT(v))
|
||||
#define MICFIL_STAT_CHXF(v) BIT(MICFIL_STAT_CHXF_SHIFT(v))
|
||||
|
||||
/* Micfil FIFO Control Register -- REG_MICFIL_FIFO_CTRL 0x10 */
|
||||
#define MICFIL_FIFO_CTRL_FIFOWMK_SHIFT 0
|
||||
#define MICFIL_FIFO_CTRL_FIFOWMK_WIDTH 3
|
||||
#define MICFIL_FIFO_CTRL_FIFOWMK_MASK ((BIT(MICFIL_FIFO_CTRL_FIFOWMK_WIDTH) - 1) \
|
||||
<< MICFIL_FIFO_CTRL_FIFOWMK_SHIFT)
|
||||
#define MICFIL_FIFO_CTRL_FIFOWMK(v) (((v) << MICFIL_FIFO_CTRL_FIFOWMK_SHIFT) \
|
||||
& MICFIL_FIFO_CTRL_FIFOWMK_MASK)
|
||||
|
||||
/* Constants */
|
||||
#define MICFIL_DMA_IRQ_DISABLED(v) ((v) & MICFIL_CTRL1_DISEL_MASK)
|
||||
#define MICFIL_DMA_ENABLED(v) ((0x1 << MICFIL_CTRL1_DISEL_SHIFT) \
|
||||
== ((v) & MICFIL_CTRL1_DISEL_MASK))
|
||||
#define MICFIL_IRQ_ENABLED(v) ((0x2 << MICFIL_CTRL1_DISEL_SHIFT) \
|
||||
== ((v) & MICFIL_CTRL1_DISEL_MASK))
|
||||
#define MICFIL_OUTPUT_CHANNELS 8
|
||||
|
||||
#define FIFO_PTRWID 3
|
||||
#define FIFO_LEN BIT(FIFO_PTRWID)
|
||||
|
||||
#define MICFIL_MAX_RETRY 10
|
||||
#define MICFIL_SLEEP_MIN 90000 /* in us */
|
||||
#define MICFIL_SLEEP_MAX 100000 /* in us */
|
||||
#define MICFIL_DMA_MAXBURST_RX 6
|
||||
#define MICFIL_CTRL2_OSR_DEFAULT (0 << MICFIL_CTRL2_CICOSR_SHIFT)
|
||||
|
||||
#endif /* _FSL_MICFIL_H */
|
||||
Loading…
Reference in New Issue