Merge branch 'merge' into next
This commit is contained in:
commit
ea4e89afed
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@ -288,13 +288,6 @@ label##_hv: \
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/* Exception addition: Hard disable interrupts */
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#define DISABLE_INTS SOFT_DISABLE_INTS(r10,r11)
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/* Exception addition: Keep interrupt state */
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#define ENABLE_INTS \
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ld r11,PACAKMSR(r13); \
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ld r12,_MSR(r1); \
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rlwimi r11,r12,0,MSR_EE; \
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mtmsrd r11,1
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#define ADD_NVGPRS \
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bl .save_nvgprs
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@ -18,10 +18,6 @@
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#include <linux/atomic.h>
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/* Define a way to iterate across irqs. */
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#define for_each_irq(i) \
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for ((i) = 0; (i) < NR_IRQS; ++(i))
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extern atomic_t ppc_n_lost_interrupts;
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/* This number is used when no interrupt has been assigned */
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@ -763,16 +763,6 @@ do_work:
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SOFT_DISABLE_INTS(r3,r4)
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1: bl .preempt_schedule_irq
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/* Hard-disable interrupts again (and update PACA) */
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#ifdef CONFIG_PPC_BOOK3E
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wrteei 0
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#else
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ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */
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mtmsrd r10,1
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#endif /* CONFIG_PPC_BOOK3E */
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li r0,PACA_IRQ_HARD_DIS
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stb r0,PACAIRQHAPPENED(r13)
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/* Re-test flags and eventually loop */
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clrrdi r9,r1,THREAD_SHIFT
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ld r4,TI_FLAGS(r9)
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@ -783,14 +773,6 @@ do_work:
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user_work:
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#endif /* CONFIG_PREEMPT */
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/* Enable interrupts */
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#ifdef CONFIG_PPC_BOOK3E
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wrteei 1
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#else
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ori r10,r10,MSR_EE
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mtmsrd r10,1
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#endif /* CONFIG_PPC_BOOK3E */
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andi. r0,r4,_TIF_NEED_RESCHED
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beq 1f
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bl .restore_interrupts
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@ -764,8 +764,8 @@ alignment_common:
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std r3,_DAR(r1)
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std r4,_DSISR(r1)
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bl .save_nvgprs
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DISABLE_INTS
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addi r3,r1,STACK_FRAME_OVERHEAD
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ENABLE_INTS
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bl .alignment_exception
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b .ret_from_except
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@ -260,11 +260,17 @@ EXPORT_SYMBOL(arch_local_irq_restore);
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* if they are currently disabled. This is typically called before
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* schedule() or do_signal() when returning to userspace. We do it
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* in C to avoid the burden of dealing with lockdep etc...
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*
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* NOTE: This is called with interrupts hard disabled but not marked
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* as such in paca->irq_happened, so we need to resync this.
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*/
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void restore_interrupts(void)
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{
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if (irqs_disabled())
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if (irqs_disabled()) {
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local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
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local_irq_enable();
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} else
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__hard_irq_enable();
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}
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#endif /* CONFIG_PPC64 */
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@ -330,14 +336,10 @@ void migrate_irqs(void)
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alloc_cpumask_var(&mask, GFP_KERNEL);
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for_each_irq(irq) {
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for_each_irq_desc(irq, desc) {
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struct irq_data *data;
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struct irq_chip *chip;
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desc = irq_to_desc(irq);
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if (!desc)
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continue;
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data = irq_desc_get_irq_data(desc);
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if (irqd_is_per_cpu(data))
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continue;
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@ -23,14 +23,11 @@
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void machine_kexec_mask_interrupts(void) {
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unsigned int i;
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struct irq_desc *desc;
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for_each_irq(i) {
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struct irq_desc *desc = irq_to_desc(i);
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for_each_irq_desc(i, desc) {
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struct irq_chip *chip;
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if (!desc)
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continue;
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chip = irq_desc_get_chip(desc);
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if (!chip)
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continue;
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@ -248,7 +248,7 @@ void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
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addr, regs->nip, regs->link, code);
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}
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if (!arch_irq_disabled_regs(regs))
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if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
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local_irq_enable();
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memset(&info, 0, sizeof(info));
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@ -1019,7 +1019,9 @@ void __kprobes program_check_exception(struct pt_regs *regs)
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return;
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}
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local_irq_enable();
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/* We restore the interrupt state now */
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if (!arch_irq_disabled_regs(regs))
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local_irq_enable();
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#ifdef CONFIG_MATH_EMULATION
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/* (reason & REASON_ILLEGAL) would be the obvious thing here,
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@ -1069,6 +1071,10 @@ void alignment_exception(struct pt_regs *regs)
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{
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int sig, code, fixed = 0;
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/* We restore the interrupt state now */
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if (!arch_irq_disabled_regs(regs))
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local_irq_enable();
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/* we don't implement logging of alignment exceptions */
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if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
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fixed = fix_alignment(regs);
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@ -114,7 +114,7 @@ static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
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pr_devel("axon_msi: woff %x roff %x msi %x\n",
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write_offset, msic->read_offset, msi);
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if (msi < NR_IRQS && irq_get_chip_data(msi) == msic) {
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if (msi < nr_irqs && irq_get_chip_data(msi) == msic) {
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generic_handle_irq(msi);
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msic->fifo_virt[idx] = cpu_to_le32(0xffffffff);
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} else {
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@ -276,9 +276,6 @@ static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
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if (rc)
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return rc;
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/* We rely on being able to stash a virq in a u16 */
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BUILD_BUG_ON(NR_IRQS > 65536);
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list_for_each_entry(entry, &dev->msi_list, list) {
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virq = irq_create_direct_mapping(msic->irq_domain);
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if (virq == NO_IRQ) {
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@ -392,7 +389,8 @@ static int axon_msi_probe(struct platform_device *device)
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}
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memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES);
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msic->irq_domain = irq_domain_add_nomap(dn, 0, &msic_host_ops, msic);
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/* We rely on being able to stash a virq in a u16, so limit irqs to < 65536 */
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msic->irq_domain = irq_domain_add_nomap(dn, 65536, &msic_host_ops, msic);
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if (!msic->irq_domain) {
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printk(KERN_ERR "axon_msi: couldn't allocate irq_domain for %s\n",
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dn->full_name);
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@ -248,6 +248,6 @@ void beatic_deinit_IRQ(void)
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{
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int i;
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for (i = 1; i < NR_IRQS; i++)
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for (i = 1; i < nr_irqs; i++)
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beat_destruct_irq_plug(i);
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}
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@ -57,9 +57,9 @@ static int max_real_irqs;
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static DEFINE_RAW_SPINLOCK(pmac_pic_lock);
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#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
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static unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
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static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
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/* The max irq number this driver deals with is 128; see max_irqs */
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static DECLARE_BITMAP(ppc_lost_interrupts, 128);
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static DECLARE_BITMAP(ppc_cached_irq_mask, 128);
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static int pmac_irq_cascade = -1;
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static struct irq_domain *pmac_pic_host;
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@ -30,9 +30,9 @@ config PPC_SPLPAR
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two or more partitions.
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config EEH
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bool "PCI Extended Error Handling (EEH)" if EXPERT
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bool
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depends on PPC_PSERIES && PCI
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default y if !EXPERT
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default y
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config PSERIES_MSI
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bool
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@ -51,8 +51,7 @@
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static intctl_cpm2_t __iomem *cpm2_intctl;
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static struct irq_domain *cpm2_pic_host;
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#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
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static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
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static unsigned long ppc_cached_irq_mask[2]; /* 2 32-bit registers */
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static const u_char irq_to_siureg[] = {
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1, 1, 1, 1, 1, 1, 1, 1,
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@ -18,69 +18,45 @@
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extern int cpm_get_irq(struct pt_regs *regs);
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static struct irq_domain *mpc8xx_pic_host;
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#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
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static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
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static unsigned long mpc8xx_cached_irq_mask;
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static sysconf8xx_t __iomem *siu_reg;
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int cpm_get_irq(struct pt_regs *regs);
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static inline unsigned long mpc8xx_irqd_to_bit(struct irq_data *d)
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{
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return 0x80000000 >> irqd_to_hwirq(d);
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}
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static void mpc8xx_unmask_irq(struct irq_data *d)
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{
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int bit, word;
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unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
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bit = irq_nr & 0x1f;
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word = irq_nr >> 5;
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ppc_cached_irq_mask[word] |= (1 << (31-bit));
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out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
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mpc8xx_cached_irq_mask |= mpc8xx_irqd_to_bit(d);
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out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask);
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}
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static void mpc8xx_mask_irq(struct irq_data *d)
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{
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int bit, word;
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unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
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bit = irq_nr & 0x1f;
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word = irq_nr >> 5;
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ppc_cached_irq_mask[word] &= ~(1 << (31-bit));
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out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
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mpc8xx_cached_irq_mask &= ~mpc8xx_irqd_to_bit(d);
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out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask);
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}
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static void mpc8xx_ack(struct irq_data *d)
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{
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int bit;
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unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
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bit = irq_nr & 0x1f;
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out_be32(&siu_reg->sc_sipend, 1 << (31-bit));
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out_be32(&siu_reg->sc_sipend, mpc8xx_irqd_to_bit(d));
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}
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static void mpc8xx_end_irq(struct irq_data *d)
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{
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int bit, word;
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unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
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bit = irq_nr & 0x1f;
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word = irq_nr >> 5;
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ppc_cached_irq_mask[word] |= (1 << (31-bit));
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out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
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mpc8xx_cached_irq_mask |= mpc8xx_irqd_to_bit(d);
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out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask);
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}
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static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type)
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{
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if (flow_type & IRQ_TYPE_EDGE_FALLING) {
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irq_hw_number_t hw = (unsigned int)irqd_to_hwirq(d);
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/* only external IRQ senses are programmable */
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if ((flow_type & IRQ_TYPE_EDGE_FALLING) && !(irqd_to_hwirq(d) & 1)) {
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unsigned int siel = in_be32(&siu_reg->sc_siel);
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/* only external IRQ senses are programmable */
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if ((hw & 1) == 0) {
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siel |= (0x80000000 >> hw);
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out_be32(&siu_reg->sc_siel, siel);
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__irq_set_handler_locked(d->irq, handle_edge_irq);
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}
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siel |= mpc8xx_irqd_to_bit(d);
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out_be32(&siu_reg->sc_siel, siel);
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__irq_set_handler_locked(d->irq, handle_edge_irq);
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}
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return 0;
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}
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@ -132,6 +108,9 @@ static int mpc8xx_pic_host_xlate(struct irq_domain *h, struct device_node *ct,
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IRQ_TYPE_EDGE_FALLING,
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};
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if (intspec[0] > 0x1f)
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return 0;
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*out_hwirq = intspec[0];
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if (intsize > 1 && intspec[1] < 4)
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*out_flags = map_pic_senses[intspec[1]];
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|
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@ -188,6 +188,7 @@ void xics_migrate_irqs_away(void)
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{
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int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
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unsigned int irq, virq;
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struct irq_desc *desc;
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/* If we used to be the default server, move to the new "boot_cpuid" */
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if (hw_cpu == xics_default_server)
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|
@ -202,8 +203,7 @@ void xics_migrate_irqs_away(void)
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/* Allow IPIs again... */
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icp_ops->set_priority(DEFAULT_PRIORITY);
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for_each_irq(virq) {
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struct irq_desc *desc;
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for_each_irq_desc(virq, desc) {
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struct irq_chip *chip;
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long server;
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unsigned long flags;
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@ -212,9 +212,8 @@ void xics_migrate_irqs_away(void)
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/* We can't set affinity on ISA interrupts */
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if (virq < NUM_ISA_INTERRUPTS)
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continue;
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desc = irq_to_desc(virq);
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/* We only need to migrate enabled IRQS */
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if (!desc || !desc->action)
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if (!desc->action)
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continue;
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if (desc->irq_data.domain != xics_host)
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continue;
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|
|
|
@ -469,7 +469,7 @@ static irqreturn_t pmz_interrupt(int irq, void *dev_id)
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tty = NULL;
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if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
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if (!ZS_IS_OPEN(uap_a)) {
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pmz_debug("ChanA interrupt while open !\n");
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pmz_debug("ChanA interrupt while not open !\n");
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goto skip_a;
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}
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write_zsreg(uap_a, R0, RES_H_IUS);
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|
@ -493,8 +493,8 @@ static irqreturn_t pmz_interrupt(int irq, void *dev_id)
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spin_lock(&uap_b->port.lock);
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tty = NULL;
|
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if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
|
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if (!ZS_IS_OPEN(uap_a)) {
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pmz_debug("ChanB interrupt while open !\n");
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if (!ZS_IS_OPEN(uap_b)) {
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pmz_debug("ChanB interrupt while not open !\n");
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goto skip_b;
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}
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write_zsreg(uap_b, R0, RES_H_IUS);
|
||||
|
|
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