pinctrl: Qualcomm SPMI PMIC GPIO pin controller driver
This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm GPIO sub-function blocks found in the PMIC chips. Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>wifi-calibration
Ivan T. Ivanov
Linus Walleij
parent
89a7117d56
commit
eadff30244
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@ -47,4 +47,17 @@ config PINCTRL_MSM8X74
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This is the pinctrl, pinmux, pinconf and gpiolib driver for the
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Qualcomm TLMM block found in the Qualcomm 8974 platform.
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config PINCTRL_QCOM_SPMI_PMIC
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tristate "Qualcomm SPMI PMIC pin controller driver"
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depends on GPIOLIB && OF && SPMI
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select REGMAP_SPMI
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select PINMUX
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select PINCONF
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select GENERIC_PINCONF
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help
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This is the pinctrl, pinmux, pinconf and gpiolib driver for the
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Qualcomm GPIO and MPP blocks found in the Qualcomm PMIC's chips,
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which are using SPMI for communication with SoC. Example PMIC's
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devices are pm8841, pm8941 and pma8084.
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endif
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@ -5,3 +5,4 @@ obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
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obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
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obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
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obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
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obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
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@ -0,0 +1,933 @@
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/*
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* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/gpio.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
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#include "../core.h"
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#include "../pinctrl-utils.h"
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#define PMIC_GPIO_ADDRESS_RANGE 0x100
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/* type and subtype registers base address offsets */
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#define PMIC_GPIO_REG_TYPE 0x4
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#define PMIC_GPIO_REG_SUBTYPE 0x5
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/* GPIO peripheral type and subtype out_values */
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#define PMIC_GPIO_TYPE 0x10
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#define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1
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#define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5
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#define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9
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#define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd
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#define PMIC_MPP_REG_RT_STS 0x10
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#define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
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/* control register base address offsets */
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#define PMIC_GPIO_REG_MODE_CTL 0x40
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#define PMIC_GPIO_REG_DIG_VIN_CTL 0x41
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#define PMIC_GPIO_REG_DIG_PULL_CTL 0x42
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#define PMIC_GPIO_REG_DIG_OUT_CTL 0x45
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#define PMIC_GPIO_REG_EN_CTL 0x46
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/* PMIC_GPIO_REG_MODE_CTL */
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#define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1
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#define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1
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#define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7
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#define PMIC_GPIO_REG_MODE_DIR_SHIFT 4
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#define PMIC_GPIO_REG_MODE_DIR_MASK 0x7
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/* PMIC_GPIO_REG_DIG_VIN_CTL */
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#define PMIC_GPIO_REG_VIN_SHIFT 0
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#define PMIC_GPIO_REG_VIN_MASK 0x7
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/* PMIC_GPIO_REG_DIG_PULL_CTL */
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#define PMIC_GPIO_REG_PULL_SHIFT 0
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#define PMIC_GPIO_REG_PULL_MASK 0x7
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#define PMIC_GPIO_PULL_DOWN 4
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#define PMIC_GPIO_PULL_DISABLE 5
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/* PMIC_GPIO_REG_DIG_OUT_CTL */
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#define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0
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#define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3
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#define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4
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#define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3
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/*
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* Output type - indicates pin should be configured as push-pull,
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* open drain or open source.
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*/
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#define PMIC_GPIO_OUT_BUF_CMOS 0
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#define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1
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#define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2
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/* PMIC_GPIO_REG_EN_CTL */
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#define PMIC_GPIO_REG_MASTER_EN_SHIFT 7
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#define PMIC_GPIO_PHYSICAL_OFFSET 1
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/* Qualcomm specific pin configurations */
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#define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1)
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#define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2)
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/**
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* struct pmic_gpio_pad - keep current GPIO settings
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* @base: Address base in SPMI device.
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* @irq: IRQ number which this GPIO generate.
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* @is_enabled: Set to false when GPIO should be put in high Z state.
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* @out_value: Cached pin output value
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* @have_buffer: Set to true if GPIO output could be configured in push-pull,
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* open-drain or open-source mode.
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* @output_enabled: Set to true if GPIO output logic is enabled.
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* @input_enabled: Set to true if GPIO input buffer logic is enabled.
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* @num_sources: Number of power-sources supported by this GPIO.
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* @power_source: Current power-source used.
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* @buffer_type: Push-pull, open-drain or open-source.
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* @pullup: Constant current which flow trough GPIO output buffer.
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* @strength: No, Low, Medium, High
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* @function: See pmic_gpio_functions[]
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*/
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struct pmic_gpio_pad {
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u16 base;
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int irq;
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bool is_enabled;
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bool out_value;
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bool have_buffer;
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bool output_enabled;
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bool input_enabled;
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unsigned int num_sources;
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unsigned int power_source;
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unsigned int buffer_type;
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unsigned int pullup;
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unsigned int strength;
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unsigned int function;
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};
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struct pmic_gpio_state {
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struct device *dev;
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struct regmap *map;
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struct pinctrl_dev *ctrl;
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struct gpio_chip chip;
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};
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struct pmic_gpio_bindings {
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const char *property;
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unsigned param;
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};
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static struct pmic_gpio_bindings pmic_gpio_bindings[] = {
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{"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP},
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{"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH},
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};
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static const char *const pmic_gpio_groups[] = {
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"gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
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"gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
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"gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
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"gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
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"gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
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};
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static const char *const pmic_gpio_functions[] = {
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PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED,
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PMIC_GPIO_FUNC_FUNC1, PMIC_GPIO_FUNC_FUNC2,
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PMIC_GPIO_FUNC_DTEST1, PMIC_GPIO_FUNC_DTEST2,
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PMIC_GPIO_FUNC_DTEST3, PMIC_GPIO_FUNC_DTEST4,
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};
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static inline struct pmic_gpio_state *to_gpio_state(struct gpio_chip *chip)
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{
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return container_of(chip, struct pmic_gpio_state, chip);
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};
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static int pmic_gpio_read(struct pmic_gpio_state *state,
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struct pmic_gpio_pad *pad, unsigned int addr)
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{
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unsigned int val;
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int ret;
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ret = regmap_read(state->map, pad->base + addr, &val);
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if (ret < 0)
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dev_err(state->dev, "read 0x%x failed\n", addr);
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else
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ret = val;
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return ret;
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}
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static int pmic_gpio_write(struct pmic_gpio_state *state,
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struct pmic_gpio_pad *pad, unsigned int addr,
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unsigned int val)
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{
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int ret;
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ret = regmap_write(state->map, pad->base + addr, val);
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if (ret < 0)
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dev_err(state->dev, "write 0x%x failed\n", addr);
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return ret;
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}
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static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev)
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{
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/* Every PIN is a group */
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return pctldev->desc->npins;
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}
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static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev,
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unsigned pin)
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{
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return pctldev->desc->pins[pin].name;
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}
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static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
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const unsigned **pins, unsigned *num_pins)
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{
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*pins = &pctldev->desc->pins[pin].number;
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*num_pins = 1;
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return 0;
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}
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static int pmic_gpio_parse_dt_config(struct device_node *np,
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struct pinctrl_dev *pctldev,
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unsigned long **configs,
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unsigned int *nconfs)
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{
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struct pmic_gpio_bindings *par;
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unsigned long cfg;
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int ret, i;
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u32 val;
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for (i = 0; i < ARRAY_SIZE(pmic_gpio_bindings); i++) {
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par = &pmic_gpio_bindings[i];
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ret = of_property_read_u32(np, par->property, &val);
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/* property not found */
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if (ret == -EINVAL)
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continue;
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/* use zero as default value */
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if (ret)
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val = 0;
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dev_dbg(pctldev->dev, "found %s with value %u\n",
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par->property, val);
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cfg = pinconf_to_config_packed(par->param, val);
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ret = pinctrl_utils_add_config(pctldev, configs, nconfs, cfg);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int pmic_gpio_dt_subnode_to_map(struct pinctrl_dev *pctldev,
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struct device_node *np,
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struct pinctrl_map **map,
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unsigned *reserv, unsigned *nmaps,
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enum pinctrl_map_type type)
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{
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unsigned long *configs = NULL;
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unsigned nconfs = 0;
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struct property *prop;
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const char *group;
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int ret;
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ret = pmic_gpio_parse_dt_config(np, pctldev, &configs, &nconfs);
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if (ret < 0)
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return ret;
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if (!nconfs)
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return 0;
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ret = of_property_count_strings(np, "pins");
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if (ret < 0)
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goto exit;
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ret = pinctrl_utils_reserve_map(pctldev, map, reserv, nmaps, ret);
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if (ret < 0)
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goto exit;
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of_property_for_each_string(np, "pins", prop, group) {
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ret = pinctrl_utils_add_map_configs(pctldev, map,
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reserv, nmaps, group,
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configs, nconfs, type);
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if (ret < 0)
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break;
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}
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exit:
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kfree(configs);
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return ret;
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}
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static int pmic_gpio_dt_node_to_map(struct pinctrl_dev *pctldev,
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struct device_node *np_config,
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struct pinctrl_map **map, unsigned *nmaps)
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{
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enum pinctrl_map_type type;
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struct device_node *np;
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unsigned reserv;
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int ret;
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ret = 0;
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*map = NULL;
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*nmaps = 0;
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reserv = 0;
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type = PIN_MAP_TYPE_CONFIGS_GROUP;
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for_each_child_of_node(np_config, np) {
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ret = pinconf_generic_dt_subnode_to_map(pctldev, np, map,
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&reserv, nmaps, type);
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if (ret)
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break;
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ret = pmic_gpio_dt_subnode_to_map(pctldev, np, map, &reserv,
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nmaps, type);
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if (ret)
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break;
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}
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if (ret < 0)
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pinctrl_utils_dt_free_map(pctldev, *map, *nmaps);
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return ret;
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}
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static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
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.get_groups_count = pmic_gpio_get_groups_count,
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.get_group_name = pmic_gpio_get_group_name,
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.get_group_pins = pmic_gpio_get_group_pins,
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.dt_node_to_map = pmic_gpio_dt_node_to_map,
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.dt_free_map = pinctrl_utils_dt_free_map,
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};
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static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev)
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{
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return ARRAY_SIZE(pmic_gpio_functions);
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}
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static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev,
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unsigned function)
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{
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return pmic_gpio_functions[function];
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}
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static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
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unsigned function,
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const char *const **groups,
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unsigned *const num_qgroups)
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{
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*groups = pmic_gpio_groups;
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*num_qgroups = pctldev->desc->npins;
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return 0;
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}
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static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
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unsigned pin)
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{
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struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
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struct pmic_gpio_pad *pad;
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unsigned int val;
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int ret;
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pad = pctldev->desc->pins[pin].drv_data;
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pad->function = function;
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val = 0;
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if (pad->output_enabled) {
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if (pad->input_enabled)
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val = 2;
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else
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val = 1;
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}
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val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
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val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
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ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
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if (ret < 0)
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return ret;
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val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
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return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
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}
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static const struct pinmux_ops pmic_gpio_pinmux_ops = {
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.get_functions_count = pmic_gpio_get_functions_count,
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.get_function_name = pmic_gpio_get_function_name,
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.get_function_groups = pmic_gpio_get_function_groups,
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.set_mux = pmic_gpio_set_mux,
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};
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static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
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unsigned int pin, unsigned long *config)
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{
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unsigned param = pinconf_to_config_param(*config);
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struct pmic_gpio_pad *pad;
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unsigned arg;
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pad = pctldev->desc->pins[pin].drv_data;
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switch (param) {
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case PIN_CONFIG_DRIVE_PUSH_PULL:
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arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_CMOS;
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break;
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case PIN_CONFIG_DRIVE_OPEN_DRAIN:
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arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
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break;
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case PIN_CONFIG_DRIVE_OPEN_SOURCE:
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arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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arg = pad->pullup == PMIC_GPIO_PULL_DOWN;
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break;
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case PIN_CONFIG_BIAS_DISABLE:
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arg = pad->pullup = PMIC_GPIO_PULL_DISABLE;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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arg = pad->pullup == PMIC_GPIO_PULL_UP_30;
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break;
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case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
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arg = !pad->is_enabled;
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break;
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case PIN_CONFIG_POWER_SOURCE:
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arg = pad->power_source;
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break;
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case PIN_CONFIG_INPUT_ENABLE:
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arg = pad->input_enabled;
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break;
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case PIN_CONFIG_OUTPUT:
|
||||
arg = pad->out_value;
|
||||
break;
|
||||
case PMIC_GPIO_CONF_PULL_UP:
|
||||
arg = pad->pullup;
|
||||
break;
|
||||
case PMIC_GPIO_CONF_STRENGTH:
|
||||
arg = pad->strength;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
*config = pinconf_to_config_packed(param, arg);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
|
||||
unsigned long *configs, unsigned nconfs)
|
||||
{
|
||||
struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct pmic_gpio_pad *pad;
|
||||
unsigned param, arg;
|
||||
unsigned int val;
|
||||
int i, ret;
|
||||
|
||||
pad = pctldev->desc->pins[pin].drv_data;
|
||||
|
||||
for (i = 0; i < nconfs; i++) {
|
||||
param = pinconf_to_config_param(configs[i]);
|
||||
arg = pinconf_to_config_argument(configs[i]);
|
||||
|
||||
switch (param) {
|
||||
case PIN_CONFIG_DRIVE_PUSH_PULL:
|
||||
pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS;
|
||||
break;
|
||||
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
|
||||
if (!pad->have_buffer)
|
||||
return -EINVAL;
|
||||
pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
|
||||
break;
|
||||
case PIN_CONFIG_DRIVE_OPEN_SOURCE:
|
||||
if (!pad->have_buffer)
|
||||
return -EINVAL;
|
||||
pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_DISABLE:
|
||||
pad->pullup = PMIC_GPIO_PULL_DISABLE;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
pad->pullup = PMIC_GPIO_PULL_UP_30;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
if (arg)
|
||||
pad->pullup = PMIC_GPIO_PULL_DOWN;
|
||||
else
|
||||
pad->pullup = PMIC_GPIO_PULL_DISABLE;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
|
||||
pad->is_enabled = false;
|
||||
break;
|
||||
case PIN_CONFIG_POWER_SOURCE:
|
||||
if (arg > pad->num_sources)
|
||||
return -EINVAL;
|
||||
pad->power_source = arg;
|
||||
break;
|
||||
case PIN_CONFIG_INPUT_ENABLE:
|
||||
pad->input_enabled = arg ? true : false;
|
||||
break;
|
||||
case PIN_CONFIG_OUTPUT:
|
||||
pad->output_enabled = true;
|
||||
pad->out_value = arg;
|
||||
break;
|
||||
case PMIC_GPIO_CONF_PULL_UP:
|
||||
if (arg > PMIC_GPIO_PULL_UP_1P5_30)
|
||||
return -EINVAL;
|
||||
pad->pullup = arg;
|
||||
break;
|
||||
case PMIC_GPIO_CONF_STRENGTH:
|
||||
if (arg > PMIC_GPIO_STRENGTH_LOW)
|
||||
return -EINVAL;
|
||||
pad->strength = arg;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT;
|
||||
|
||||
ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT;
|
||||
|
||||
ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT;
|
||||
val = pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
|
||||
|
||||
ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
val = 0;
|
||||
if (pad->output_enabled) {
|
||||
if (pad->input_enabled)
|
||||
val = 2;
|
||||
else
|
||||
val = 1;
|
||||
}
|
||||
|
||||
val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
|
||||
val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
|
||||
val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
|
||||
|
||||
return pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
|
||||
}
|
||||
|
||||
static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
|
||||
struct seq_file *s, unsigned pin)
|
||||
{
|
||||
struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct pmic_gpio_pad *pad;
|
||||
int ret, val;
|
||||
|
||||
static const char *const biases[] = {
|
||||
"pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
|
||||
"pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
|
||||
};
|
||||
static const char *const buffer_types[] = {
|
||||
"push-pull", "open-drain", "open-source"
|
||||
};
|
||||
static const char *const strengths[] = {
|
||||
"no", "high", "medium", "low"
|
||||
};
|
||||
|
||||
pad = pctldev->desc->pins[pin].drv_data;
|
||||
|
||||
seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
|
||||
|
||||
val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);
|
||||
|
||||
if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
|
||||
seq_puts(s, " ---");
|
||||
} else {
|
||||
|
||||
if (!pad->input_enabled) {
|
||||
ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
|
||||
if (!ret) {
|
||||
ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
|
||||
pad->out_value = ret;
|
||||
}
|
||||
}
|
||||
|
||||
seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in");
|
||||
seq_printf(s, " %-7s", pmic_gpio_functions[pad->function]);
|
||||
seq_printf(s, " vin-%d", pad->power_source);
|
||||
seq_printf(s, " %-27s", biases[pad->pullup]);
|
||||
seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
|
||||
seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
|
||||
seq_printf(s, " %-7s", strengths[pad->strength]);
|
||||
}
|
||||
}
|
||||
|
||||
static const struct pinconf_ops pmic_gpio_pinconf_ops = {
|
||||
.pin_config_group_get = pmic_gpio_config_get,
|
||||
.pin_config_group_set = pmic_gpio_config_set,
|
||||
.pin_config_group_dbg_show = pmic_gpio_config_dbg_show,
|
||||
};
|
||||
|
||||
static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
|
||||
{
|
||||
struct pmic_gpio_state *state = to_gpio_state(chip);
|
||||
unsigned long config;
|
||||
|
||||
config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
|
||||
|
||||
return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
|
||||
}
|
||||
|
||||
static int pmic_gpio_direction_output(struct gpio_chip *chip,
|
||||
unsigned pin, int val)
|
||||
{
|
||||
struct pmic_gpio_state *state = to_gpio_state(chip);
|
||||
unsigned long config;
|
||||
|
||||
config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
|
||||
|
||||
return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
|
||||
}
|
||||
|
||||
static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
|
||||
{
|
||||
struct pmic_gpio_state *state = to_gpio_state(chip);
|
||||
struct pmic_gpio_pad *pad;
|
||||
int ret;
|
||||
|
||||
pad = state->ctrl->desc->pins[pin].drv_data;
|
||||
|
||||
if (!pad->is_enabled)
|
||||
return -EINVAL;
|
||||
|
||||
if (pad->input_enabled) {
|
||||
ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
|
||||
}
|
||||
|
||||
return pad->out_value;
|
||||
}
|
||||
|
||||
static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
|
||||
{
|
||||
struct pmic_gpio_state *state = to_gpio_state(chip);
|
||||
unsigned long config;
|
||||
|
||||
config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
|
||||
|
||||
pmic_gpio_config_set(state->ctrl, pin, &config, 1);
|
||||
}
|
||||
|
||||
static int pmic_gpio_request(struct gpio_chip *chip, unsigned base)
|
||||
{
|
||||
return pinctrl_request_gpio(chip->base + base);
|
||||
}
|
||||
|
||||
static void pmic_gpio_free(struct gpio_chip *chip, unsigned base)
|
||||
{
|
||||
pinctrl_free_gpio(chip->base + base);
|
||||
}
|
||||
|
||||
static int pmic_gpio_of_xlate(struct gpio_chip *chip,
|
||||
const struct of_phandle_args *gpio_desc,
|
||||
u32 *flags)
|
||||
{
|
||||
if (chip->of_gpio_n_cells < 2)
|
||||
return -EINVAL;
|
||||
|
||||
if (flags)
|
||||
*flags = gpio_desc->args[1];
|
||||
|
||||
return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
|
||||
}
|
||||
|
||||
static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
|
||||
{
|
||||
struct pmic_gpio_state *state = to_gpio_state(chip);
|
||||
struct pmic_gpio_pad *pad;
|
||||
|
||||
pad = state->ctrl->desc->pins[pin].drv_data;
|
||||
|
||||
return pad->irq;
|
||||
}
|
||||
|
||||
static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
|
||||
{
|
||||
struct pmic_gpio_state *state = to_gpio_state(chip);
|
||||
unsigned i;
|
||||
|
||||
for (i = 0; i < chip->ngpio; i++) {
|
||||
pmic_gpio_config_dbg_show(state->ctrl, s, i);
|
||||
seq_puts(s, "\n");
|
||||
}
|
||||
}
|
||||
|
||||
static const struct gpio_chip pmic_gpio_gpio_template = {
|
||||
.direction_input = pmic_gpio_direction_input,
|
||||
.direction_output = pmic_gpio_direction_output,
|
||||
.get = pmic_gpio_get,
|
||||
.set = pmic_gpio_set,
|
||||
.request = pmic_gpio_request,
|
||||
.free = pmic_gpio_free,
|
||||
.of_xlate = pmic_gpio_of_xlate,
|
||||
.to_irq = pmic_gpio_to_irq,
|
||||
.dbg_show = pmic_gpio_dbg_show,
|
||||
};
|
||||
|
||||
static int pmic_gpio_populate(struct pmic_gpio_state *state,
|
||||
struct pmic_gpio_pad *pad)
|
||||
{
|
||||
int type, subtype, val, dir;
|
||||
|
||||
type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE);
|
||||
if (type < 0)
|
||||
return type;
|
||||
|
||||
if (type != PMIC_GPIO_TYPE) {
|
||||
dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
|
||||
type, pad->base);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE);
|
||||
if (subtype < 0)
|
||||
return subtype;
|
||||
|
||||
switch (subtype) {
|
||||
case PMIC_GPIO_SUBTYPE_GPIO_4CH:
|
||||
pad->have_buffer = true;
|
||||
case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
|
||||
pad->num_sources = 4;
|
||||
break;
|
||||
case PMIC_GPIO_SUBTYPE_GPIO_8CH:
|
||||
pad->have_buffer = true;
|
||||
case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
|
||||
pad->num_sources = 8;
|
||||
break;
|
||||
default:
|
||||
dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
|
||||
if (val < 0)
|
||||
return val;
|
||||
|
||||
pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
|
||||
|
||||
dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
|
||||
dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
|
||||
switch (dir) {
|
||||
case 0:
|
||||
pad->input_enabled = true;
|
||||
pad->output_enabled = false;
|
||||
break;
|
||||
case 1:
|
||||
pad->input_enabled = false;
|
||||
pad->output_enabled = true;
|
||||
break;
|
||||
case 2:
|
||||
pad->input_enabled = true;
|
||||
pad->output_enabled = true;
|
||||
break;
|
||||
default:
|
||||
dev_err(state->dev, "unknown GPIO direction\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
|
||||
pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
|
||||
|
||||
val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
|
||||
if (val < 0)
|
||||
return val;
|
||||
|
||||
pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT;
|
||||
pad->power_source &= PMIC_GPIO_REG_VIN_MASK;
|
||||
|
||||
val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL);
|
||||
if (val < 0)
|
||||
return val;
|
||||
|
||||
pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
|
||||
pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
|
||||
|
||||
val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
|
||||
if (val < 0)
|
||||
return val;
|
||||
|
||||
pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
|
||||
pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK;
|
||||
|
||||
pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
|
||||
pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
|
||||
|
||||
/* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
|
||||
pad->is_enabled = true;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pmic_gpio_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct pinctrl_pin_desc *pindesc;
|
||||
struct pinctrl_desc *pctrldesc;
|
||||
struct pmic_gpio_pad *pad, *pads;
|
||||
struct pmic_gpio_state *state;
|
||||
int ret, npins, i;
|
||||
u32 res[2];
|
||||
|
||||
ret = of_property_read_u32_array(dev->of_node, "reg", res, 2);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "missing base address and/or range");
|
||||
return ret;
|
||||
}
|
||||
|
||||
npins = res[1] / PMIC_GPIO_ADDRESS_RANGE;
|
||||
|
||||
if (!npins)
|
||||
return -EINVAL;
|
||||
|
||||
BUG_ON(npins > ARRAY_SIZE(pmic_gpio_groups));
|
||||
|
||||
state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
|
||||
if (!state)
|
||||
return -ENOMEM;
|
||||
|
||||
platform_set_drvdata(pdev, state);
|
||||
|
||||
state->dev = &pdev->dev;
|
||||
state->map = dev_get_regmap(dev->parent, NULL);
|
||||
|
||||
pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
|
||||
if (!pindesc)
|
||||
return -ENOMEM;
|
||||
|
||||
pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
|
||||
if (!pads)
|
||||
return -ENOMEM;
|
||||
|
||||
pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
|
||||
if (!pctrldesc)
|
||||
return -ENOMEM;
|
||||
|
||||
pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
|
||||
pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
|
||||
pctrldesc->confops = &pmic_gpio_pinconf_ops;
|
||||
pctrldesc->owner = THIS_MODULE;
|
||||
pctrldesc->name = dev_name(dev);
|
||||
pctrldesc->pins = pindesc;
|
||||
pctrldesc->npins = npins;
|
||||
|
||||
for (i = 0; i < npins; i++, pindesc++) {
|
||||
pad = &pads[i];
|
||||
pindesc->drv_data = pad;
|
||||
pindesc->number = i;
|
||||
pindesc->name = pmic_gpio_groups[i];
|
||||
|
||||
pad->irq = platform_get_irq(pdev, i);
|
||||
if (pad->irq < 0)
|
||||
return pad->irq;
|
||||
|
||||
pad->base = res[0] + i * PMIC_GPIO_ADDRESS_RANGE;
|
||||
|
||||
ret = pmic_gpio_populate(state, pad);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
state->chip = pmic_gpio_gpio_template;
|
||||
state->chip.dev = dev;
|
||||
state->chip.base = -1;
|
||||
state->chip.ngpio = npins;
|
||||
state->chip.label = dev_name(dev);
|
||||
state->chip.of_gpio_n_cells = 2;
|
||||
state->chip.can_sleep = false;
|
||||
|
||||
state->ctrl = pinctrl_register(pctrldesc, dev, state);
|
||||
if (!state->ctrl)
|
||||
return -ENODEV;
|
||||
|
||||
ret = gpiochip_add(&state->chip);
|
||||
if (ret) {
|
||||
dev_err(state->dev, "can't add gpio chip\n");
|
||||
goto err_chip;
|
||||
}
|
||||
|
||||
ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to add pin range\n");
|
||||
goto err_range;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_range:
|
||||
gpiochip_remove(&state->chip);
|
||||
err_chip:
|
||||
pinctrl_unregister(state->ctrl);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int pmic_gpio_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct pmic_gpio_state *state = platform_get_drvdata(pdev);
|
||||
|
||||
gpiochip_remove(&state->chip);
|
||||
pinctrl_unregister(state->ctrl);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id pmic_gpio_of_match[] = {
|
||||
{ .compatible = "qcom,pm8941-gpio" }, /* 36 GPIO's */
|
||||
{ .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */
|
||||
{ },
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, pmic_gpio_of_match);
|
||||
|
||||
static struct platform_driver pmic_gpio_driver = {
|
||||
.driver = {
|
||||
.name = "qcom-spmi-gpio",
|
||||
.of_match_table = pmic_gpio_of_match,
|
||||
},
|
||||
.probe = pmic_gpio_probe,
|
||||
.remove = pmic_gpio_remove,
|
||||
};
|
||||
|
||||
module_platform_driver(pmic_gpio_driver);
|
||||
|
||||
MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
|
||||
MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
|
||||
MODULE_ALIAS("platform:qcom-spmi-gpio");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue