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MLK-19557-1 can: flexcan: fix CAN can't suspend on MX8QM 

The transceiver of FLEXCAN is regulated by i2c I/O Expander which
interrupt-parent is intmux, so we must set i2c I/O Expander power domain
as the sub power domain of the intmux.

In principle, the device tree describes the hardware, so the device tree
topology should follow the hardware structure. Here move the definition of
FLEXCAN to more suitable location.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
pull/10/head
Joakim Zhang 2018-09-12 18:30:21 +08:00 committed by Jason Liu
parent 5907ad8b7e
commit eb0f497c33
1 changed files with 51 additions and 48 deletions
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99
arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
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@ -1373,16 +1373,19 @@
#address-cells = <1>;
#size-cells = <0>;
pd_cm41_i2c: PD_CM41_I2C {
reg = <SC_R_M4_1_I2C>;
#power-domain-cells = <0>;
power-domains =<&pd_cm41>;
};
pd_cm41_intmux: PD_CM41_INTMUX {
reg = <SC_R_M4_1_INTMUX>;
#power-domain-cells = <0>;
power-domains =<&pd_cm41>;
#address-cells = <1>;
#size-cells = <0>;
early_power_on;
pd_cm41_i2c: PD_CM41_I2C {
reg = <SC_R_M4_1_I2C>;
#power-domain-cells = <0>;
power-domains =<&pd_cm41_intmux>;
};
};
};
@ -1836,48 +1839,6 @@
power-domains = <&pd_mipi0>;
};
flexcan1: can@5a8d0000 {
compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan";
reg = <0x0 0x5a8d0000 0x0 0x10000>;
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&wu>;
clocks = <&clk IMX8QM_CAN0_IPG_CLK>,
<&clk IMX8QM_CAN0_CLK>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX8QM_CAN0_CLK>;
assigned-clock-rates = <40000000>;
power-domains = <&pd_dma_flexcan0>;
status = "disabled";
};
flexcan2: can@5a8e0000 {
compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan";
reg = <0x0 0x5a8e0000 0x0 0x10000>;
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&wu>;
clocks = <&clk IMX8QM_CAN1_IPG_CLK>,
<&clk IMX8QM_CAN1_CLK>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX8QM_CAN1_CLK>;
assigned-clock-rates = <40000000>;
power-domains = <&pd_dma_flexcan1>;
status = "disabled";
};
flexcan3: can@5a8f0000 {
compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan";
reg = <0x0 0x5a8f0000 0x0 0x10000>;
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&wu>;
clocks = <&clk IMX8QM_CAN2_IPG_CLK>,
<&clk IMX8QM_CAN2_CLK>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX8QM_CAN2_CLK>;
assigned-clock-rates = <40000000>;
power-domains = <&pd_dma_flexcan2>;
status = "disabled";
};
i2c0_mipi_dsi0: i2c@56226000 {
compatible = "fsl,imx8qm-lpi2c";
reg = <0x0 0x56226000 0x0 0x1000>;
@ -2847,6 +2808,48 @@
power-domains = <&pd_lvds0>;
};
flexcan1: can@5a8d0000 {
compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan";
reg = <0x0 0x5a8d0000 0x0 0x10000>;
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&wu>;
clocks = <&clk IMX8QM_CAN0_IPG_CLK>,
<&clk IMX8QM_CAN0_CLK>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX8QM_CAN0_CLK>;
assigned-clock-rates = <40000000>;
power-domains = <&pd_dma_flexcan0>;
status = "disabled";
};
flexcan2: can@5a8e0000 {
compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan";
reg = <0x0 0x5a8e0000 0x0 0x10000>;
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&wu>;
clocks = <&clk IMX8QM_CAN1_IPG_CLK>,
<&clk IMX8QM_CAN1_CLK>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX8QM_CAN1_CLK>;
assigned-clock-rates = <40000000>;
power-domains = <&pd_dma_flexcan1>;
status = "disabled";
};
flexcan3: can@5a8f0000 {
compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan";
reg = <0x0 0x5a8f0000 0x0 0x10000>;
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&wu>;
clocks = <&clk IMX8QM_CAN2_IPG_CLK>,
<&clk IMX8QM_CAN2_CLK>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX8QM_CAN2_CLK>;
assigned-clock-rates = <40000000>;
power-domains = <&pd_dma_flexcan2>;
status = "disabled";
};
i2c1_lvds0: i2c@56247000 {
compatible = "fsl,imx8qm-lpi2c";
reg = <0x0 0x56247000 0x0 0x1000>;