RISC-V patches for v5.2-rc6
This tag contains fixes, defconfig, and DT data changes for the v5.2-rc series. The fixes are relatively straightforward: - Addition of a TLB fence in the vmalloc_fault path, so the CPU doesn't enter an infinite page fault loop; - Readdition of the pm_power_off export, so device drivers that reassign it can now be built as modules; - A udelay() fix for RV32, fixing a miscomputation of the delay time; - Removal of deprecated smp_mb__*() barriers. The tag also adds initial DT data infrastructure for arch/riscv, along with initial data for the SiFive FU540-C000 SoC and the corresponding HiFive Unleashed board. We also update the RV64 defconfig to include some core drivers for the FU540 in the build. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEElRDoIDdEz9/svf2Kx4+xDQu9KksFAl0HtEkACgkQx4+xDQu9 KkuRIw//f2vSrUyMh44sevr6euVD0K++hQ0AbteQ94cGHqYWWaNxfwMHFD91Gxbj wowTwgssq7H9nePsKANjiiLULnZNIkWXAlIncjzv3aXkH6JG3f9nEGR49yzvCbIZ yN8wgElJ8rcVWLd096E53Su84CzxuJJ2o3wOI1nQi8aI4h3LwkM2b/O4GxZFpnWb vIhWXqjvbUb8XL7Y+VPewtxnZItOUDHkuIkup4kP2bTgl2iDW93hzWwxNKbt6v+m 9wTzAChjcepCAXSmEGeeZ/h2HNqw2crs+NWOe0drcKxL2vKPZ6gS8ZRX/NuIoDr4 JgMILzYSO28z8N6w1cJJUdN4eGhCTvdxVTQXvkk/yZoT08X6M0xb5A1MbtizgOJ6 mZK/vM9gtuoUSZG0SRNeNoqHbWu1tIm29z435Be8hWAtzXlEfewJm8ntgFO4dGmb E8TRSgjLzdHY0Nvwx/KVtvYmE/TMybVVRsxJJ525dqJlHT7f3VuRstvw7VQJQpz2 +JfsZbYk1KjbUc25QpAqF1LUxrRQFn2JL0Cqw+L49J8eshY77rsTcAKP6ZZWiSFZ qodU0oPF4BkS1t0bnFuNwlqsAr/q9EiAnQO7+SvqQY/ZUnMNk9gCNn5k/rHMCfyD 2Dyo6iAbj+Yyb1rrQxX6QnlbHgpFxsG3N4s9E5jOPgKyEQM4JQ4= =aotJ -----END PGP SIGNATURE----- Merge tag 'riscv-for-v5.2/fixes-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V fixes from Paul Walmsley: "This contains fixes, defconfig, and DT data changes for the v5.2-rc series. The fixes are relatively straightforward: - Addition of a TLB fence in the vmalloc_fault path, so the CPU doesn't enter an infinite page fault loop - Readdition of the pm_power_off export, so device drivers that reassign it can now be built as modules - A udelay() fix for RV32, fixing a miscomputation of the delay time - Removal of deprecated smp_mb__*() barriers This also adds initial DT data infrastructure for arch/riscv, along with initial data for the SiFive FU540-C000 SoC and the corresponding HiFive Unleashed board. We also update the RV64 defconfig to include some core drivers for the FU540 in the build" * tag 'riscv-for-v5.2/fixes-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: remove unused barrier defines riscv: mm: synchronize MMU after pte change riscv: dts: add initial board data for the SiFive HiFive Unleashed riscv: dts: add initial support for the SiFive FU540-C000 SoC dt-bindings: riscv: convert cpu binding to json-schema dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540 arch: riscv: add support for building DTB files from DT source data riscv: Fix udelay in RV32. riscv: export pm_power_off again RISC-V: defconfig: enable clocks, serial console
This commit is contained in:
commit
eb7c825bf7
168
Documentation/devicetree/bindings/riscv/cpus.yaml
Normal file
168
Documentation/devicetree/bindings/riscv/cpus.yaml
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|
@ -0,0 +1,168 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/riscv/cpus.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: RISC-V bindings for 'cpus' DT nodes
|
||||
|
||||
maintainers:
|
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- Paul Walmsley <paul.walmsley@sifive.com>
|
||||
- Palmer Dabbelt <palmer@sifive.com>
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allOf:
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- $ref: /schemas/cpus.yaml#
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|
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properties:
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$nodename:
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const: cpus
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description: Container of cpu nodes
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||||
|
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'#address-cells':
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const: 1
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description: |
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A single unsigned 32-bit integer uniquely identifies each RISC-V
|
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hart in a system. (See the "reg" node under the "cpu" node,
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below).
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'#size-cells':
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const: 0
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patternProperties:
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'^cpu@[0-9a-f]+$':
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properties:
|
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compatible:
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type: array
|
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items:
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||||
- enum:
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- sifive,rocket0
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- sifive,e5
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- sifive,e51
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- sifive,u54-mc
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- sifive,u54
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- sifive,u5
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- const: riscv
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description:
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Identifies that the hart uses the RISC-V instruction set
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and identifies the type of the hart.
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|
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mmu-type:
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allOf:
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- $ref: "/schemas/types.yaml#/definitions/string"
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- enum:
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- riscv,sv32
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- riscv,sv39
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- riscv,sv48
|
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description:
|
||||
Identifies the MMU address translation mode used on this
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||||
hart. These values originate from the RISC-V Privileged
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Specification document, available from
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https://riscv.org/specifications/
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|
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riscv,isa:
|
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allOf:
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- $ref: "/schemas/types.yaml#/definitions/string"
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- enum:
|
||||
- rv64imac
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- rv64imafdc
|
||||
description:
|
||||
Identifies the specific RISC-V instruction set architecture
|
||||
supported by the hart. These are documented in the RISC-V
|
||||
User-Level ISA document, available from
|
||||
https://riscv.org/specifications/
|
||||
|
||||
timebase-frequency:
|
||||
type: integer
|
||||
minimum: 1
|
||||
description:
|
||||
Specifies the clock frequency of the system timer in Hz.
|
||||
This value is common to all harts on a single system image.
|
||||
|
||||
interrupt-controller:
|
||||
type: object
|
||||
description: Describes the CPU's local interrupt controller
|
||||
|
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properties:
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||||
'#interrupt-cells':
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const: 1
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|
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compatible:
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const: riscv,cpu-intc
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|
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interrupt-controller: true
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||||
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required:
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- '#interrupt-cells'
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- compatible
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- interrupt-controller
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||||
|
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required:
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- riscv,isa
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- timebase-frequency
|
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- interrupt-controller
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|
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examples:
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- |
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// Example 1: SiFive Freedom U540G Development Kit
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <1000000>;
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cpu@0 {
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clock-frequency = <0>;
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compatible = "sifive,rocket0", "riscv";
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device_type = "cpu";
|
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i-cache-block-size = <64>;
|
||||
i-cache-sets = <128>;
|
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i-cache-size = <16384>;
|
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reg = <0>;
|
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riscv,isa = "rv64imac";
|
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cpu_intc0: interrupt-controller {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
cpu@1 {
|
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clock-frequency = <0>;
|
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compatible = "sifive,rocket0", "riscv";
|
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d-cache-block-size = <64>;
|
||||
d-cache-sets = <64>;
|
||||
d-cache-size = <32768>;
|
||||
d-tlb-sets = <1>;
|
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d-tlb-size = <32>;
|
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device_type = "cpu";
|
||||
i-cache-block-size = <64>;
|
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i-cache-sets = <64>;
|
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i-cache-size = <32768>;
|
||||
i-tlb-sets = <1>;
|
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i-tlb-size = <32>;
|
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mmu-type = "riscv,sv39";
|
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reg = <1>;
|
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riscv,isa = "rv64imafdc";
|
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tlb-split;
|
||||
cpu_intc1: interrupt-controller {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "riscv,cpu-intc";
|
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interrupt-controller;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
// Example 2: Spike ISA Simulator with 1 Hart
|
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cpus {
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
compatible = "riscv";
|
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riscv,isa = "rv64imafdc";
|
||||
mmu-type = "riscv,sv48";
|
||||
interrupt-controller {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
compatible = "riscv,cpu-intc";
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
25
Documentation/devicetree/bindings/riscv/sifive.yaml
Normal file
25
Documentation/devicetree/bindings/riscv/sifive.yaml
Normal file
|
@ -0,0 +1,25 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/riscv/sifive.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: SiFive SoC-based boards
|
||||
|
||||
maintainers:
|
||||
- Paul Walmsley <paul.walmsley@sifive.com>
|
||||
- Palmer Dabbelt <palmer@sifive.com>
|
||||
|
||||
description:
|
||||
SiFive SoC-based boards
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- sifive,freedom-unleashed-a00
|
||||
- const: sifive,fu540-c000
|
||||
- const: sifive,fu540
|
||||
...
|
|
@ -14335,6 +14335,15 @@ S: Supported
|
|||
K: sifive
|
||||
N: sifive
|
||||
|
||||
SIFIVE FU540 SYSTEM-ON-CHIP
|
||||
M: Paul Walmsley <paul.walmsley@sifive.com>
|
||||
M: Palmer Dabbelt <palmer@sifive.com>
|
||||
L: linux-riscv@lists.infradead.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pjw/sifive.git
|
||||
S: Supported
|
||||
K: fu540
|
||||
N: fu540
|
||||
|
||||
SILEAD TOUCHSCREEN DRIVER
|
||||
M: Hans de Goede <hdegoede@redhat.com>
|
||||
L: linux-input@vger.kernel.org
|
||||
|
|
2
arch/riscv/boot/dts/Makefile
Normal file
2
arch/riscv/boot/dts/Makefile
Normal file
|
@ -0,0 +1,2 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
subdir-y += sifive
|
2
arch/riscv/boot/dts/sifive/Makefile
Normal file
2
arch/riscv/boot/dts/sifive/Makefile
Normal file
|
@ -0,0 +1,2 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
dtb-y += hifive-unleashed-a00.dtb
|
215
arch/riscv/boot/dts/sifive/fu540-c000.dtsi
Normal file
215
arch/riscv/boot/dts/sifive/fu540-c000.dtsi
Normal file
|
@ -0,0 +1,215 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/* Copyright (c) 2018-2019 SiFive, Inc */
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/clock/sifive-fu540-prci.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
compatible = "sifive,fu540-c000", "sifive,fu540";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
timebase-frequency = <1000000>;
|
||||
cpu0: cpu@0 {
|
||||
compatible = "sifive,e51", "sifive,rocket0", "riscv";
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-sets = <128>;
|
||||
i-cache-size = <16384>;
|
||||
reg = <0>;
|
||||
riscv,isa = "rv64imac";
|
||||
status = "disabled";
|
||||
cpu0_intc: interrupt-controller {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
cpu1: cpu@1 {
|
||||
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-sets = <64>;
|
||||
d-cache-size = <32768>;
|
||||
d-tlb-sets = <1>;
|
||||
d-tlb-size = <32>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-sets = <64>;
|
||||
i-cache-size = <32768>;
|
||||
i-tlb-sets = <1>;
|
||||
i-tlb-size = <32>;
|
||||
mmu-type = "riscv,sv39";
|
||||
reg = <1>;
|
||||
riscv,isa = "rv64imafdc";
|
||||
tlb-split;
|
||||
cpu1_intc: interrupt-controller {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
cpu2: cpu@2 {
|
||||
clock-frequency = <0>;
|
||||
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-sets = <64>;
|
||||
d-cache-size = <32768>;
|
||||
d-tlb-sets = <1>;
|
||||
d-tlb-size = <32>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-sets = <64>;
|
||||
i-cache-size = <32768>;
|
||||
i-tlb-sets = <1>;
|
||||
i-tlb-size = <32>;
|
||||
mmu-type = "riscv,sv39";
|
||||
reg = <2>;
|
||||
riscv,isa = "rv64imafdc";
|
||||
tlb-split;
|
||||
cpu2_intc: interrupt-controller {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
cpu3: cpu@3 {
|
||||
clock-frequency = <0>;
|
||||
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-sets = <64>;
|
||||
d-cache-size = <32768>;
|
||||
d-tlb-sets = <1>;
|
||||
d-tlb-size = <32>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-sets = <64>;
|
||||
i-cache-size = <32768>;
|
||||
i-tlb-sets = <1>;
|
||||
i-tlb-size = <32>;
|
||||
mmu-type = "riscv,sv39";
|
||||
reg = <3>;
|
||||
riscv,isa = "rv64imafdc";
|
||||
tlb-split;
|
||||
cpu3_intc: interrupt-controller {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
cpu4: cpu@4 {
|
||||
clock-frequency = <0>;
|
||||
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-sets = <64>;
|
||||
d-cache-size = <32768>;
|
||||
d-tlb-sets = <1>;
|
||||
d-tlb-size = <32>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-sets = <64>;
|
||||
i-cache-size = <32768>;
|
||||
i-tlb-sets = <1>;
|
||||
i-tlb-size = <32>;
|
||||
mmu-type = "riscv,sv39";
|
||||
reg = <4>;
|
||||
riscv,isa = "rv64imafdc";
|
||||
tlb-split;
|
||||
cpu4_intc: interrupt-controller {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
};
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
|
||||
ranges;
|
||||
plic0: interrupt-controller@c000000 {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "sifive,plic-1.0.0";
|
||||
reg = <0x0 0xc000000 0x0 0x4000000>;
|
||||
riscv,ndev = <53>;
|
||||
interrupt-controller;
|
||||
interrupts-extended = <
|
||||
&cpu0_intc 0xffffffff
|
||||
&cpu1_intc 0xffffffff &cpu1_intc 9
|
||||
&cpu2_intc 0xffffffff &cpu2_intc 9
|
||||
&cpu3_intc 0xffffffff &cpu3_intc 9
|
||||
&cpu4_intc 0xffffffff &cpu4_intc 9>;
|
||||
};
|
||||
prci: clock-controller@10000000 {
|
||||
compatible = "sifive,fu540-c000-prci";
|
||||
reg = <0x0 0x10000000 0x0 0x1000>;
|
||||
clocks = <&hfclk>, <&rtcclk>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
uart0: serial@10010000 {
|
||||
compatible = "sifive,fu540-c000-uart", "sifive,uart0";
|
||||
reg = <0x0 0x10010000 0x0 0x1000>;
|
||||
interrupt-parent = <&plic0>;
|
||||
interrupts = <4>;
|
||||
clocks = <&prci PRCI_CLK_TLCLK>;
|
||||
};
|
||||
uart1: serial@10011000 {
|
||||
compatible = "sifive,fu540-c000-uart", "sifive,uart0";
|
||||
reg = <0x0 0x10011000 0x0 0x1000>;
|
||||
interrupt-parent = <&plic0>;
|
||||
interrupts = <5>;
|
||||
clocks = <&prci PRCI_CLK_TLCLK>;
|
||||
};
|
||||
i2c0: i2c@10030000 {
|
||||
compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
|
||||
reg = <0x0 0x10030000 0x0 0x1000>;
|
||||
interrupt-parent = <&plic0>;
|
||||
interrupts = <50>;
|
||||
clocks = <&prci PRCI_CLK_TLCLK>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
qspi0: spi@10040000 {
|
||||
compatible = "sifive,fu540-c000-spi", "sifive,spi0";
|
||||
reg = <0x0 0x10040000 0x0 0x1000
|
||||
0x0 0x20000000 0x0 0x10000000>;
|
||||
interrupt-parent = <&plic0>;
|
||||
interrupts = <51>;
|
||||
clocks = <&prci PRCI_CLK_TLCLK>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
qspi1: spi@10041000 {
|
||||
compatible = "sifive,fu540-c000-spi", "sifive,spi0";
|
||||
reg = <0x0 0x10041000 0x0 0x1000
|
||||
0x0 0x30000000 0x0 0x10000000>;
|
||||
interrupt-parent = <&plic0>;
|
||||
interrupts = <52>;
|
||||
clocks = <&prci PRCI_CLK_TLCLK>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
qspi2: spi@10050000 {
|
||||
compatible = "sifive,fu540-c000-spi", "sifive,spi0";
|
||||
reg = <0x0 0x10050000 0x0 0x1000>;
|
||||
interrupt-parent = <&plic0>;
|
||||
interrupts = <6>;
|
||||
clocks = <&prci PRCI_CLK_TLCLK>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
65
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
Normal file
65
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
Normal file
|
@ -0,0 +1,65 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/* Copyright (c) 2018-2019 SiFive, Inc */
|
||||
|
||||
#include "fu540-c000.dtsi"
|
||||
|
||||
/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
|
||||
#define RTCCLK_FREQ 1000000
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
model = "SiFive HiFive Unleashed A00";
|
||||
compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
|
||||
|
||||
chosen {
|
||||
};
|
||||
|
||||
cpus {
|
||||
timebase-frequency = <RTCCLK_FREQ>;
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0x2 0x00000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
};
|
||||
|
||||
hfclk: hfclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <33333333>;
|
||||
clock-output-names = "hfclk";
|
||||
};
|
||||
|
||||
rtcclk: rtcclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <RTCCLK_FREQ>;
|
||||
clock-output-names = "rtcclk";
|
||||
};
|
||||
};
|
||||
|
||||
&qspi0 {
|
||||
flash@0 {
|
||||
compatible = "issi,is25wp256", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
m25p,fast-read;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
&qspi2 {
|
||||
status = "okay";
|
||||
mmc@0 {
|
||||
compatible = "mmc-spi-slot";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <20000000>;
|
||||
voltage-ranges = <3300 3300>;
|
||||
disable-wp;
|
||||
};
|
||||
};
|
|
@ -49,6 +49,8 @@ CONFIG_SERIAL_8250=y
|
|||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
|
||||
CONFIG_SERIAL_SIFIVE=y
|
||||
CONFIG_SERIAL_SIFIVE_CONSOLE=y
|
||||
CONFIG_HVC_RISCV_SBI=y
|
||||
# CONFIG_PTP_1588_CLOCK is not set
|
||||
CONFIG_DRM=y
|
||||
|
@ -64,6 +66,8 @@ CONFIG_USB_OHCI_HCD_PLATFORM=y
|
|||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_UAS=y
|
||||
CONFIG_VIRTIO_MMIO=y
|
||||
CONFIG_CLK_SIFIVE=y
|
||||
CONFIG_CLK_SIFIVE_FU540_PRCI=y
|
||||
CONFIG_SIFIVE_PLIC=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXT4_FS_POSIX_ACL=y
|
||||
|
|
|
@ -15,11 +15,6 @@
|
|||
#include <asm/barrier.h>
|
||||
#include <asm/bitsperlong.h>
|
||||
|
||||
#ifndef smp_mb__before_clear_bit
|
||||
#define smp_mb__before_clear_bit() smp_mb()
|
||||
#define smp_mb__after_clear_bit() smp_mb()
|
||||
#endif /* smp_mb__before_clear_bit */
|
||||
|
||||
#include <asm-generic/bitops/__ffs.h>
|
||||
#include <asm-generic/bitops/ffz.h>
|
||||
#include <asm-generic/bitops/fls.h>
|
||||
|
|
|
@ -13,6 +13,7 @@ static void default_power_off(void)
|
|||
}
|
||||
|
||||
void (*pm_power_off)(void) = default_power_off;
|
||||
EXPORT_SYMBOL(pm_power_off);
|
||||
|
||||
void machine_restart(char *cmd)
|
||||
{
|
||||
|
|
|
@ -80,7 +80,7 @@ EXPORT_SYMBOL(__delay);
|
|||
|
||||
void udelay(unsigned long usecs)
|
||||
{
|
||||
unsigned long ucycles = usecs * lpj_fine * UDELAY_MULT;
|
||||
u64 ucycles = (u64)usecs * lpj_fine * UDELAY_MULT;
|
||||
|
||||
if (unlikely(usecs > MAX_UDELAY_US)) {
|
||||
__delay((u64)usecs * riscv_timebase / 1000000ULL);
|
||||
|
|
|
@ -16,6 +16,7 @@
|
|||
|
||||
#include <asm/pgalloc.h>
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/tlbflush.h>
|
||||
|
||||
/*
|
||||
* This routine handles page faults. It determines the address and the
|
||||
|
@ -265,6 +266,18 @@ vmalloc_fault:
|
|||
pte_k = pte_offset_kernel(pmd_k, addr);
|
||||
if (!pte_present(*pte_k))
|
||||
goto no_context;
|
||||
|
||||
/*
|
||||
* The kernel assumes that TLBs don't cache invalid
|
||||
* entries, but in RISC-V, SFENCE.VMA specifies an
|
||||
* ordering constraint, not a cache flush; it is
|
||||
* necessary even after writing invalid entries.
|
||||
* Relying on flush_tlb_fix_spurious_fault would
|
||||
* suffice, but the extra traps reduce
|
||||
* performance. So, eagerly SFENCE.VMA.
|
||||
*/
|
||||
local_flush_tlb_page(addr);
|
||||
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
|
Loading…
Reference in a new issue