net/ps3: Fix gelic RX DMA restart
Fix the condition where PS3 network RX hangs when no network TX is occurring by calling gelic_card_enable_rxdmac() during RX_DMA_CHAIN_END event processing. The gelic hardware automatically clears its RX_DMA_EN flag when it detects an RX_DMA_CHAIN_END event. In its processing of RX_DMA_CHAIN_END the gelic driver is required to set RX_DMA_EN (with a call to gelic_card_enable_rxdmac()) to restart RX DMA transfers. The existing gelic driver code does not set RX_DMA_EN directly in its processing of the RX_DMA_CHAIN_END event, but uses a flag variable card->rx_dma_restart_required to schedule the setting of RX_DMA_EN until next inside the interrupt handler. It seems this delayed setting of RX_DMA_EN causes the hang since the next RX interrupt after the RX_DMA_CHAIN_END event where RX_DMA_EN is scheduled to be set will not occur since RX_DMA_EN was not set. In the case were network TX is occuring, RX_DMA_EN is set in the next TX interrupt and RX processing continues. Signed-off-by: Geoff Levand <geoff@infradead.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -993,10 +993,6 @@ static int gelic_card_decode_one_descr(struct gelic_card *card)
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int dmac_chain_ended;
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status = gelic_descr_get_status(descr);
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/* is this descriptor terminated with next_descr == NULL? */
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dmac_chain_ended =
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be32_to_cpu(descr->dmac_cmd_status) &
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GELIC_DESCR_RX_DMA_CHAIN_END;
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if (status == GELIC_DESCR_DMA_CARDOWNED)
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return 0;
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@ -1059,6 +1055,11 @@ static int gelic_card_decode_one_descr(struct gelic_card *card)
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/* ok, we've got a packet in descr */
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gelic_net_pass_skb_up(descr, card, netdev);
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refill:
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/* is the current descriptor terminated with next_descr == NULL? */
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dmac_chain_ended =
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be32_to_cpu(descr->dmac_cmd_status) &
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GELIC_DESCR_RX_DMA_CHAIN_END;
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/*
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* So that always DMAC can see the end
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* of the descriptor chain to avoid
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@ -1087,10 +1088,9 @@ refill:
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* If dmac chain was met, DMAC stopped.
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* thus re-enable it
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*/
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if (dmac_chain_ended) {
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card->rx_dma_restart_required = 1;
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dev_dbg(ctodev(card), "reenable rx dma scheduled\n");
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}
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if (dmac_chain_ended)
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gelic_card_enable_rxdmac(card);
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return 1;
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}
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@ -1156,11 +1156,6 @@ static irqreturn_t gelic_card_interrupt(int irq, void *ptr)
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status &= card->irq_mask;
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if (card->rx_dma_restart_required) {
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card->rx_dma_restart_required = 0;
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gelic_card_enable_rxdmac(card);
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}
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if (status & GELIC_CARD_RXINT) {
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gelic_card_rx_irq_off(card);
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napi_schedule(&card->napi);
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@ -289,7 +289,6 @@ struct gelic_card {
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struct gelic_descr_chain tx_chain;
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struct gelic_descr_chain rx_chain;
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int rx_dma_restart_required;
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/*
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* tx_lock guards tx descriptor list and
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* tx_dma_progress.
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