pcmcia: synclink_cs: replace sum of bitmasks with OR operation.
Suggested by coccinelle and manually verified. Signed-off-by: Alexandru Juncu <alexj@rosedu.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -1182,14 +1182,14 @@ static irqreturn_t mgslpc_isr(int dummy, void *dev_id)
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}
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count++;
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if (gis & (BIT1 + BIT0)) {
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if (gis & (BIT1 | BIT0)) {
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isr = read_reg16(info, CHB + ISR);
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if (isr & IRQ_DCD)
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dcd_change(info, tty);
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if (isr & IRQ_CTS)
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cts_change(info, tty);
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}
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if (gis & (BIT3 + BIT2))
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if (gis & (BIT3 | BIT2))
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{
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isr = read_reg16(info, CHA + ISR);
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if (isr & IRQ_TIMER) {
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@ -1210,7 +1210,7 @@ static irqreturn_t mgslpc_isr(int dummy, void *dev_id)
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if (isr & IRQ_RXTIME) {
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issue_command(info, CHA, CMD_RXFIFO_READ);
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}
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if (isr & (IRQ_RXEOM + IRQ_RXFIFO)) {
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if (isr & (IRQ_RXEOM | IRQ_RXFIFO)) {
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if (info->params.mode == MGSL_MODE_HDLC)
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rx_ready_hdlc(info, isr & IRQ_RXEOM);
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else
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@ -3031,11 +3031,11 @@ static void loopback_enable(MGSLPC_INFO *info)
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unsigned char val;
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/* CCR1:02..00 CM[2..0] Clock Mode = 111 (clock mode 7) */
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val = read_reg(info, CHA + CCR1) | (BIT2 + BIT1 + BIT0);
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val = read_reg(info, CHA + CCR1) | (BIT2 | BIT1 | BIT0);
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write_reg(info, CHA + CCR1, val);
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/* CCR2:04 SSEL Clock source select, 1=submode b */
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val = read_reg(info, CHA + CCR2) | (BIT4 + BIT5);
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val = read_reg(info, CHA + CCR2) | (BIT4 | BIT5);
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write_reg(info, CHA + CCR2, val);
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/* set LinkSpeed if available, otherwise default to 2Mbps */
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@ -3125,10 +3125,10 @@ static void hdlc_mode(MGSLPC_INFO *info)
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val |= BIT4;
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break; // FM0
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case HDLC_ENCODING_BIPHASE_MARK:
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val |= BIT4 + BIT2;
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val |= BIT4 | BIT2;
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break; // FM1
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case HDLC_ENCODING_BIPHASE_LEVEL:
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val |= BIT4 + BIT3;
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val |= BIT4 | BIT3;
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break; // Manchester
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}
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write_reg(info, CHA + CCR0, val);
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@ -3185,7 +3185,7 @@ static void hdlc_mode(MGSLPC_INFO *info)
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*/
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val = 0x00;
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if (info->params.crc_type == HDLC_CRC_NONE)
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val |= BIT2 + BIT1;
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val |= BIT2 | BIT1;
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if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
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val |= BIT5;
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switch (info->params.preamble_length)
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@ -3197,7 +3197,7 @@ static void hdlc_mode(MGSLPC_INFO *info)
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val |= BIT6;
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break;
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case HDLC_PREAMBLE_LENGTH_64BITS:
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val |= BIT7 + BIT6;
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val |= BIT7 | BIT6;
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break;
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}
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write_reg(info, CHA + CCR3, val);
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@ -3264,8 +3264,8 @@ static void hdlc_mode(MGSLPC_INFO *info)
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clear_reg_bits(info, CHA + PVR, BIT3);
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irq_enable(info, CHA,
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IRQ_RXEOM + IRQ_RXFIFO + IRQ_ALLSENT +
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IRQ_UNDERRUN + IRQ_TXFIFO);
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IRQ_RXEOM | IRQ_RXFIFO | IRQ_ALLSENT |
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IRQ_UNDERRUN | IRQ_TXFIFO);
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issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
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wait_command_complete(info, CHA);
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read_reg16(info, CHA + ISR); /* clear pending IRQs */
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@ -3582,8 +3582,8 @@ static void async_mode(MGSLPC_INFO *info)
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} else
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clear_reg_bits(info, CHA + PVR, BIT3);
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irq_enable(info, CHA,
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IRQ_RXEOM + IRQ_RXFIFO + IRQ_BREAK_ON + IRQ_RXTIME +
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IRQ_ALLSENT + IRQ_TXFIFO);
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IRQ_RXEOM | IRQ_RXFIFO | IRQ_BREAK_ON | IRQ_RXTIME |
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IRQ_ALLSENT | IRQ_TXFIFO);
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issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
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wait_command_complete(info, CHA);
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read_reg16(info, CHA + ISR); /* clear pending IRQs */
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