mtd: update the ABI document about the ecc step size
We add a new sys node for ecc step size. So update the ABI document about it. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> [Brian: edited description, modified 'ecc_strength'] Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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@ -128,9 +128,8 @@ KernelVersion: 3.4
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Contact: linux-mtd@lists.infradead.org
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Description:
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Maximum number of bit errors that the device is capable of
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correcting within each region covering an ecc step. This will
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always be a non-negative integer. Note that some devices will
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have multiple ecc steps within each writesize region.
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correcting within each region covering an ECC step (see
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ecc_step_size). This will always be a non-negative integer.
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In the case of devices lacking any ECC capability, it is 0.
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@ -173,3 +172,15 @@ Description:
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This is generally applicable only to NAND flash devices with ECC
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capability. It is ignored on devices lacking ECC capability;
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i.e., devices for which ecc_strength is zero.
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What: /sys/class/mtd/mtdX/ecc_step_size
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Date: May 2013
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KernelVersion: 3.10
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Contact: linux-mtd@lists.infradead.org
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Description:
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The size of a single region covered by ECC, known as the ECC
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step. Devices may have several equally sized ECC steps within
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each writesize region.
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It will always be a non-negative integer. In the case of
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devices lacking any ECC capability, it is 0.
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