MIPS: Octeon: Remove usage of cvmx_wait() everywhere.
Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17389/ Signed-off-by: James Hogan <jhogan@kernel.org>
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@ -862,7 +862,7 @@ int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
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*/
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cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 0);
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cvmx_wait(100000000ull);
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__delay(100000000ull);
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for (retry_loop_cnt = 0; retry_loop_cnt < 10; retry_loop_cnt++) {
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retry_cnt = 100000;
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@ -215,7 +215,7 @@ int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode)
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spxx_clk_ctl.u64 = 0;
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spxx_clk_ctl.s.runbist = 1;
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cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
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cvmx_wait(10 * MS);
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__delay(10 * MS);
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spxx_bist_stat.u64 = cvmx_read_csr(CVMX_SPXX_BIST_STAT(interface));
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if (spxx_bist_stat.s.stat0)
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cvmx_dprintf
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@ -265,14 +265,14 @@ int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode)
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spxx_clk_ctl.s.rcvtrn = 0;
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spxx_clk_ctl.s.srxdlck = 0;
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cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
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cvmx_wait(100 * MS);
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__delay(100 * MS);
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/* Reset SRX0 DLL */
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spxx_clk_ctl.s.srxdlck = 1;
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cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
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/* Waiting for Inf0 Spi4 RX DLL to lock */
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cvmx_wait(100 * MS);
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__delay(100 * MS);
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/* Enable dynamic alignment */
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spxx_trn4_ctl.s.trntest = 0;
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@ -527,7 +527,7 @@ int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout)
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spxx_clk_ctl.s.rcvtrn = 1;
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spxx_clk_ctl.s.srxdlck = 1;
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cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
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cvmx_wait(1000 * MS);
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__delay(1000 * MS);
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/* SRX0 clear the boot bit */
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spxx_trn4_ctl.u64 = cvmx_read_csr(CVMX_SPXX_TRN4_CTL(interface));
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@ -536,7 +536,7 @@ int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout)
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/* Wait for the training sequence to complete */
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cvmx_dprintf("SPI%d: Waiting for training\n", interface);
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cvmx_wait(1000 * MS);
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__delay(1000 * MS);
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/* Wait a really long time here */
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timeout_time = cvmx_get_cycle() + 1000ull * MS * 600;
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/*
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@ -36,6 +36,8 @@
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#ifndef __CVMX_FPA_H__
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#define __CVMX_FPA_H__
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#include <linux/delay.h>
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#include <asm/octeon/cvmx-address.h>
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#include <asm/octeon/cvmx-fpa-defs.h>
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@ -165,7 +167,7 @@ static inline void cvmx_fpa_enable(void)
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}
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/* Enforce a 10 cycle delay between config and enable */
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cvmx_wait(10);
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__delay(10);
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}
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/* FIXME: CVMX_FPA_CTL_STATUS read is unmodelled */
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@ -30,6 +30,7 @@
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/delay.h>
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enum cvmx_mips_space {
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CVMX_MIPS_SPACE_XKSEG = 3LL,
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@ -428,18 +429,6 @@ static inline uint64_t cvmx_get_cycle(void)
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return cycle;
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}
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/**
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* Wait for the specified number of cycle
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*
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*/
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static inline void cvmx_wait(uint64_t cycles)
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{
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uint64_t done = cvmx_get_cycle() + cycles;
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while (cvmx_get_cycle() < done)
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; /* Spin */
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}
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/**
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* Reads a chip global cycle counter. This counts CPU cycles since
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* chip reset. The counter is 64 bit.
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@ -481,7 +470,7 @@ static inline uint64_t cvmx_get_cycle_global(void)
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result = -1; \
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break; \
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} else \
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cvmx_wait(100); \
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__delay(100); \
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} \
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} while (0); \
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result; \
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@ -639,7 +639,7 @@ static int __cvmx_pcie_rc_initialize_link_gen1(int pcie_port)
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cvmx_dprintf("PCIe: Port %d link timeout\n", pcie_port);
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return -1;
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}
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cvmx_wait(10000);
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__delay(10000);
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pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
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} while (pciercx_cfg032.s.dlla == 0);
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@ -821,7 +821,7 @@ retry:
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* don't poll PESCX_CTL_STATUS2[PCIERST], but simply wait a
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* fixed number of cycles.
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*/
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cvmx_wait(400000);
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__delay(400000);
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/*
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* PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of
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@ -1018,7 +1018,7 @@ retry:
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i = in_p_offset;
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while (i--) {
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cvmx_write64_uint32(write_address, 0);
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cvmx_wait(10000);
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__delay(10000);
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}
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/*
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@ -1034,7 +1034,7 @@ retry:
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dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
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old_in_fif_p_count = dbg_data.s.data & 0xff;
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cvmx_write64_uint32(write_address, 0);
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cvmx_wait(10000);
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__delay(10000);
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dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
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in_fif_p_count = dbg_data.s.data & 0xff;
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} while (in_fif_p_count != ((old_in_fif_p_count+1) & 0xff));
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@ -1053,7 +1053,7 @@ retry:
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cvmx_dprintf("PCIe: Port %d aligning TLP counters as workaround to maintain ordering\n", pcie_port);
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while (in_fif_p_count != 0) {
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cvmx_write64_uint32(write_address, 0);
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cvmx_wait(10000);
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__delay(10000);
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in_fif_p_count = (in_fif_p_count + 1) & 0xff;
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}
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/*
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@ -1105,7 +1105,7 @@ static int __cvmx_pcie_rc_initialize_link_gen2(int pcie_port)
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do {
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if (cvmx_get_cycle() - start_cycle > octeon_get_clock_rate())
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return -1;
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cvmx_wait(10000);
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__delay(10000);
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pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
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} while ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1));
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