clk: zte: pd_bit is not 0 on zx296718
The bit 0 of PLL_CFG0 register is not powerdown on zx296718, but part of of postdiv2 field. The consequence is that functions like hw_to_idx() and zx_pll_enable() will end up tampering the postdiv2 of the PLL. Let's fix it by defining pd_bit 0xff which is obviously invalid for a bit position and having PLL driver check the validity before operating on the bit. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
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@ -52,7 +52,10 @@ static int hw_to_idx(struct clk_zx_pll *zx_pll)
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/* For matching the value in lookup table */
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hw_cfg0 &= ~BIT(zx_pll->lock_bit);
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hw_cfg0 |= BIT(zx_pll->pd_bit);
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/* Check availability of pd_bit */
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if (zx_pll->pd_bit < 32)
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hw_cfg0 |= BIT(zx_pll->pd_bit);
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for (i = 0; i < zx_pll->count; i++) {
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if (hw_cfg0 == config[i].cfg0 && hw_cfg1 == config[i].cfg1)
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@ -108,6 +111,10 @@ static int zx_pll_enable(struct clk_hw *hw)
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struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
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u32 reg;
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/* If pd_bit is not available, simply return success. */
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if (zx_pll->pd_bit > 31)
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return 0;
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reg = readl_relaxed(zx_pll->reg_base);
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writel_relaxed(reg & ~BIT(zx_pll->pd_bit), zx_pll->reg_base);
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@ -120,6 +127,9 @@ static void zx_pll_disable(struct clk_hw *hw)
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struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
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u32 reg;
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if (zx_pll->pd_bit > 31)
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return;
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reg = readl_relaxed(zx_pll->reg_base);
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writel_relaxed(reg | BIT(zx_pll->pd_bit), zx_pll->reg_base);
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}
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@ -66,8 +66,12 @@ struct clk_zx_pll {
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CLK_GET_RATE_NOCACHE), \
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}
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/*
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* The pd_bit is not available on ZX296718, so let's pass something
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* bigger than 31, e.g. 0xff, to indicate that.
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*/
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#define ZX296718_PLL(_name, _parent, _reg, _table) \
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ZX_PLL(_name, _parent, _reg, _table, 0, 30)
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ZX_PLL(_name, _parent, _reg, _table, 0xff, 30)
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struct zx_clk_gate {
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struct clk_gate gate;
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