Intel FB: obvious changes and corrections
Intel FB: obvious changes and corrections Signed-off-by: Krzysztof Halasa <khc@pm.waw.pl> Cc: "Antonino A. Daplas" <adaplas@pol.net> Cc: <sylvain.meyer@worldonline.fr> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -355,7 +355,10 @@ struct intelfb_info {
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struct intelfb_output_rec output[MAX_OUTPUTS];
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};
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#define IS_I9XX(dinfo) (((dinfo)->chipset == INTEL_915G)||(dinfo->chipset == INTEL_915GM)||((dinfo)->chipset == INTEL_945G)||(dinfo->chipset==INTEL_945GM))
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#define IS_I9XX(dinfo) (((dinfo)->chipset == INTEL_915G) || \
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((dinfo)->chipset == INTEL_915GM) || \
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((dinfo)->chipset == INTEL_945G) || \
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((dinfo)->chipset==INTEL_945GM))
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#ifndef FBIO_WAITFORVSYNC
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#define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
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@ -434,14 +434,14 @@ void intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
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unsigned red, unsigned green, unsigned blue,
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unsigned transp)
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{
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u32 palette_reg = (dinfo->pipe == PIPE_A) ?
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PALETTE_A : PALETTE_B;
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#if VERBOSE > 0
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DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
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regno, red, green, blue);
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#endif
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u32 palette_reg = (dinfo->pipe == PIPE_A) ?
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PALETTE_A : PALETTE_B;
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OUTREG(palette_reg + (regno << 2),
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(red << PALETTE_8_RED_SHIFT) |
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(green << PALETTE_8_GREEN_SHIFT) |
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@ -1305,8 +1305,8 @@ int intelfbhw_program_mode(struct intelfb_info *dinfo,
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count = 0;
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do {
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tmp_val[count%3] = INREG(0x70000);
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if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
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tmp_val[count % 3] = INREG(PIPEA_DSL);
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if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1] == tmp_val[2]))
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break;
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count++;
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udelay(1);
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@ -2004,7 +2004,6 @@ intelfbhw_enable_irq(struct intelfb_info *dinfo, int reenable) {
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void
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intelfbhw_disable_irq(struct intelfb_info *dinfo) {
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u16 tmp;
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if (test_and_clear_bit(0, &dinfo->irq_flags)) {
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if (dinfo->vsync.pan_display) {
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@ -2016,8 +2015,7 @@ intelfbhw_disable_irq(struct intelfb_info *dinfo) {
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OUTREG16(IMR, 0xffff);
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OUTREG16(IER, 0x0);
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tmp = INREG16(IIR);
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OUTREG16(IIR, tmp);
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OUTREG16(IIR, INREG16(IIR)); /* clear IRQ requests */
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spin_unlock_irq(&dinfo->int_lock);
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free_irq(dinfo->pdev->irq, dinfo);
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@ -93,7 +93,7 @@
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#define IIR 0x20A4
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#define IMR 0x20A8
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#define VSYNC_PIPE_A_INTERRUPT (1 << 7)
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#define PIPE_A_EVENT_INTERRUPT (1 << 4)
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#define PIPE_A_EVENT_INTERRUPT (1 << 6)
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#define VSYNC_PIPE_B_INTERRUPT (1 << 5)
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#define PIPE_B_EVENT_INTERRUPT (1 << 4)
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#define HOST_PORT_EVENT_INTERRUPT (1 << 3)
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@ -276,6 +276,8 @@
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#define DVOB_SRCDIM 0x61144
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#define DVOC_SRCDIM 0x61164
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#define PIPEA_DSL 0x70000
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#define PIPEB_DSL 0x71000
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#define PIPEACONF 0x70008
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#define PIPEBCONF 0x71008
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#define PIPECONF_ENABLE (1 << 31)
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