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MLK-19652 ARM64: dts: imx8mq-evk: add touch and mipi-hdmi support for both B4 and B3 board 

For imx8mq-evk board, B4 board change touch/mipi-hdmi connected i2c bus from i2c1 to i2c3.
So this patch make the touch and mipi-hdmi work for both B4 and B3 board.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
pull/10/head
Haibo Chen 2018-09-20 20:31:50 +08:00 committed by Jason Liu
parent 9bd8ff09d3
commit ee9c297415
15 changed files with 476 additions and 350 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm64/boot/dts/freescale/Makefile
View File

@ -90,11 +90,15 @@ dtb-$(CONFIG_ARCH_FSL_IMX8MQ) += fsl-imx8mq-ddr3l-arm2.dtb \
fsl-imx8mq-evk-m4.dtb \
fsl-imx8mq-evk-pcie1-m2.dtb \
fsl-imx8mq-evk-lcdif-adv7535.dtb \
fsl-imx8mq-evk-lcdif-adv7535-b3.dtb \
fsl-imx8mq-evk-lcdif-rm67191.dtb \
fsl-imx8mq-evk-lcdif-rm67191-b3.dtb \
fsl-imx8mq-evk-mipi-csi2.dtb \
fsl-imx8mq-evk-pdm.dtb \
fsl-imx8mq-evk-dcss-adv7535.dtb \
fsl-imx8mq-evk-dcss-adv7535-b3.dtb \
fsl-imx8mq-evk-dcss-rm67191.dtb \
fsl-imx8mq-evk-dcss-rm67191-b3.dtb \
fsl-imx8mq-evk-dual-display.dtb \
fsl-imx8mq-evk-ak4497.dtb \
fsl-imx8mq-evk-audio-tdm.dtb \

12
arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-b3.dts
View File

@ -16,6 +16,7 @@
/delete-node/ &ov5640_mipi;
/delete-node/ &ov5640_mipi2;
/delete-node/ &synaptics_dsx_ts;
/delete-node/ &adv_bridge;
&i2c1 {
@ -65,6 +66,17 @@
};
};
synaptics_dsx_ts: synaptics_dsx_ts@20 {
compatible = "synaptics_dsx";
reg = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_dsi_ts_int>;
interrupt-parent = <&gpio5>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
synaptics,diagonal-rotation;
status = "disabled";
};
adv_bridge: adv7535@3d {
compatible = "adi,adv7533";
reg = <0x3d>;

16
arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-adv7535-b3.dts 100644
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@ -0,0 +1,16 @@
/*
* Copyright 2018 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "fsl-imx8mq-evk-b3.dts"
#include "fsl-imx8mq-evk-dcss-adv7535.dtsi"

62
arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-adv7535.dts
View File

@ -1,5 +1,5 @@
/*
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -13,62 +13,4 @@
*/
#include "fsl-imx8mq-evk.dts"
&hdmi {
status = "disabled";
};
&dcss {
status = "okay";
disp-dev = "mipi_disp";
clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
<&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
<&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
<&clk IMX8MQ_CLK_DC_PIXEL_DIV>,
<&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_DISP_DTRC_DIV>;
clock-names = "apb", "axi", "rtrm", "pix_div", "pix_out", "dtrc";
assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>,
<&clk IMX8MQ_CLK_DISP_AXI_SRC>,
<&clk IMX8MQ_CLK_DISP_RTRM_SRC>,
<&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_SYS1_PLL_800M>;
assigned-clock-rates = <594000000>,
<800000000>,
<400000000>,
<400000000>;
dcss_disp0: port@0 {
reg = <0>;
dcss_disp0_mipi_dsi: mipi_dsi {
remote-endpoint = <&mipi_dsi_in>;
};
};
};
&mipi_dsi_phy {
status = "okay";
};
&mipi_dsi {
status = "okay";
port@1 {
mipi_dsi_in: endpoint {
remote-endpoint = <&dcss_disp0_mipi_dsi>;
};
};
};
&mipi_dsi_bridge {
status = "okay";
};
&adv_bridge {
status = "okay";
};
#include "fsl-imx8mq-evk-dcss-adv7535.dtsi"

72
arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-adv7535.dtsi 100644
View File

@ -0,0 +1,72 @@
/*
* Copyright 2018 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
&hdmi {
status = "disabled";
};
&dcss {
status = "okay";
disp-dev = "mipi_disp";
clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
<&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
<&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
<&clk IMX8MQ_CLK_DC_PIXEL_DIV>,
<&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_DISP_DTRC_DIV>;
clock-names = "apb", "axi", "rtrm", "pix_div", "pix_out", "dtrc";
assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>,
<&clk IMX8MQ_CLK_DISP_AXI_SRC>,
<&clk IMX8MQ_CLK_DISP_RTRM_SRC>,
<&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_SYS1_PLL_800M>;
assigned-clock-rates = <594000000>,
<800000000>,
<400000000>,
<400000000>;
dcss_disp0: port@0 {
reg = <0>;
dcss_disp0_mipi_dsi: mipi_dsi {
remote-endpoint = <&mipi_dsi_in>;
};
};
};
&mipi_dsi_phy {
status = "okay";
};
&mipi_dsi {
status = "okay";
port@1 {
mipi_dsi_in: endpoint {
remote-endpoint = <&dcss_disp0_mipi_dsi>;
};
};
};
&mipi_dsi_bridge {
status = "okay";
};
&adv_bridge {
status = "okay";
};

16
arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191-b3.dts 100644
View File

@ -0,0 +1,16 @@
/*
* Copyright 2018 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "fsl-imx8mq-evk-b3.dts"
#include "fsl-imx8mq-evk-dcss-rm67191.dtsi"

126
arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dts
View File

@ -1,5 +1,5 @@
/*
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -13,126 +13,4 @@
*/
#include "fsl-imx8mq-evk.dts"
&hdmi {
status = "disabled";
};
&dcss {
status = "okay";
disp-dev = "mipi_disp";
clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
<&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
<&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
<&clk IMX8MQ_CLK_DC_PIXEL_DIV>,
<&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_DISP_DTRC_DIV>;
clock-names = "apb", "axi", "rtrm", "pix_div", "pix_out", "dtrc";
assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>,
<&clk IMX8MQ_CLK_DISP_AXI_SRC>,
<&clk IMX8MQ_CLK_DISP_RTRM_SRC>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
<&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>,
<&clk IMX8MQ_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_CLK_25M>;
assigned-clock-rates = <600000000>,
<800000000>,
<400000000>,
<0>,
<400000000>,
<599999999>;
dcss_disp0: port@0 {
reg = <0>;
dcss_disp0_mipi_dsi: mipi_dsi {
remote-endpoint = <&mipi_dsi_in>;
};
};
};
&mipi_dsi_phy {
status = "okay";
};
&mipi_dsi {
status = "okay";
assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF_SRC>,
<&clk IMX8MQ_CLK_DSI_CORE_SRC>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
<&clk IMX8MQ_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_SYS1_PLL_266M>,
<&clk IMX8MQ_CLK_25M>;
assigned-clock-rates = <24000000>,
<266000000>,
<0>,
<599999999>;
port@1 {
mipi_dsi_in: endpoint {
remote-endpoint = <&dcss_disp0_mipi_dsi>;
};
};
};
&mipi_dsi_bridge {
status = "okay";
panel@0 {
compatible = "raydium,rm67191";
reg = <0>;
pinctrl-0 = <&pinctrl_mipi_dsi_en>;
reset-gpio = <&gpio5 6 GPIO_ACTIVE_HIGH>;
dsi-lanes = <4>;
panel-width-mm = <68>;
panel-height-mm = <121>;
port {
panel1_in: endpoint {
remote-endpoint = <&mipi_dsi_bridge_out>;
};
};
};
port@2 {
mipi_dsi_bridge_out: endpoint {
remote-endpoint = <&panel1_in>;
};
};
};
&iomuxc {
imx8mq-evk {
pinctrl_mipi_dsi_en: mipi_dsi_en {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16
>;
};
pinctrl_i2c1_synaptics_dsx_io: synaptics_dsx_iogrp {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x19
>;
};
};
};
&i2c1 {
synaptics_dsx_ts@20 {
compatible = "synaptics_dsx";
reg = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_synaptics_dsx_io>;
interrupt-parent = <&gpio5>;
interrupts = <7 8>;
synaptics,diagonal-rotation;
status = "okay";
};
};
#include "fsl-imx8mq-evk-dcss-rm67191.dtsi"

121
arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dtsi 100644
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@ -0,0 +1,121 @@
/*
* Copyright 2018 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
&hdmi {
status = "disabled";
};
&dcss {
status = "okay";
disp-dev = "mipi_disp";
clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
<&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
<&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
<&clk IMX8MQ_CLK_DC_PIXEL_DIV>,
<&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_DISP_DTRC_DIV>;
clock-names = "apb", "axi", "rtrm", "pix_div", "pix_out", "dtrc";
assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>,
<&clk IMX8MQ_CLK_DISP_AXI_SRC>,
<&clk IMX8MQ_CLK_DISP_RTRM_SRC>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
<&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>,
<&clk IMX8MQ_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_CLK_25M>;
assigned-clock-rates = <600000000>,
<800000000>,
<400000000>,
<0>,
<400000000>,
<599999999>;
dcss_disp0: port@0 {
reg = <0>;
dcss_disp0_mipi_dsi: mipi_dsi {
remote-endpoint = <&mipi_dsi_in>;
};
};
};
&mipi_dsi_phy {
status = "okay";
};
&mipi_dsi {
status = "okay";
assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF_SRC>,
<&clk IMX8MQ_CLK_DSI_CORE_SRC>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
<&clk IMX8MQ_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_SYS1_PLL_266M>,
<&clk IMX8MQ_CLK_25M>;
assigned-clock-rates = <24000000>,
<266000000>,
<0>,
<599999999>;
port@1 {
mipi_dsi_in: endpoint {
remote-endpoint = <&dcss_disp0_mipi_dsi>;
};
};
};
&mipi_dsi_bridge {
status = "okay";
panel@0 {
compatible = "raydium,rm67191";
reg = <0>;
pinctrl-0 = <&pinctrl_mipi_dsi_en>;
reset-gpio = <&gpio5 6 GPIO_ACTIVE_HIGH>;
dsi-lanes = <4>;
panel-width-mm = <68>;
panel-height-mm = <121>;
port {
panel1_in: endpoint {
remote-endpoint = <&mipi_dsi_bridge_out>;
};
};
};
port@2 {
mipi_dsi_bridge_out: endpoint {
remote-endpoint = <&panel1_in>;
};
};
};
&iomuxc {
imx8mq-evk {
pinctrl_mipi_dsi_en: mipi_dsi_en {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16
>;
};
};
};
&synaptics_dsx_ts {
status = "okay";
};

16
arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-adv7535-b3.dts 100644
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@ -0,0 +1,16 @@
/*
* Copyright 2018 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "fsl-imx8mq-evk-b3.dts"
#include "fsl-imx8mq-evk-lcdif-adv7535.dtsi"

57
arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-adv7535.dts
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@ -1,5 +1,5 @@
/*
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -13,57 +13,4 @@
*/
#include "fsl-imx8mq-evk.dts"
/ {
display-subsystem {
status = "disabled";
};
};
&irqsteer_dcss {
status = "disabled";
};
&dcss {
status = "disabled";
};
&hdmi {
status = "disabled";
};
&lcdif {
status = "okay";
max-res = <1920>, <1080>;
port@0 {
lcdif_mipi_dsi: mipi-dsi-endpoint {
remote-endpoint = <&mipi_dsi_in>;
};
};
};
&mipi_dsi_phy {
status = "okay";
};
&mipi_dsi {
status = "okay";
as_bridge;
sync-pol = <1>;
pwr-delay = <10>;
port@1 {
mipi_dsi_in: endpoint {
remote-endpoint = <&lcdif_mipi_dsi>;
};
};
};
&mipi_dsi_bridge {
status = "okay";
};
&adv_bridge {
status = "okay";
};
#include "fsl-imx8mq-evk-lcdif-adv7535.dtsi"

67
arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-adv7535.dtsi 100644
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@ -0,0 +1,67 @@
/*
* Copyright 2018 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/ {
display-subsystem {
status = "disabled";
};
};
&irqsteer_dcss {
status = "disabled";
};
&dcss {
status = "disabled";
};
&hdmi {
status = "disabled";
};
&lcdif {
status = "okay";
max-res = <1920>, <1080>;
port@0 {
lcdif_mipi_dsi: mipi-dsi-endpoint {
remote-endpoint = <&mipi_dsi_in>;
};
};
};
&mipi_dsi_phy {
status = "okay";
};
&mipi_dsi {
status = "okay";
as_bridge;
sync-pol = <1>;
pwr-delay = <10>;
port@1 {
mipi_dsi_in: endpoint {
remote-endpoint = <&lcdif_mipi_dsi>;
};
};
};
&mipi_dsi_bridge {
status = "okay";
};
&adv_bridge {
status = "okay";
};

16
arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191-b3.dts 100644
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@ -0,0 +1,16 @@
/*
* Copyright 2018 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "fsl-imx8mq-evk-b3.dts"
#include "fsl-imx8mq-evk-lcdif-rm67191.dtsi"

103
arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dts
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@ -1,5 +1,5 @@
/*
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -13,103 +13,4 @@
*/
#include "fsl-imx8mq-evk.dts"
/ {
display-subsystem {
status = "disabled";
};
};
&irqsteer_dcss {
status = "disabled";
};
&dcss {
status = "disabled";
};
&hdmi {
status = "disabled";
};
&lcdif {
status = "okay";
max-res = <1080>, <1920>;
assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
<&clk IMX8MQ_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_CLK_25M>;
assigned-clock-rate = <120000000>,
<0>,
<599999999>;
port@0 {
lcdif_mipi_dsi: mipi-dsi-endpoint {
remote-endpoint = <&mipi_dsi_in>;
};
};
};
&mipi_dsi_phy {
status = "okay";
};
&mipi_dsi {
status = "okay";
as_bridge;
sync-pol = <1>;
assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF_SRC>,
<&clk IMX8MQ_CLK_DSI_CORE_SRC>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
<&clk IMX8MQ_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_SYS1_PLL_266M>,
<&clk IMX8MQ_CLK_25M>;
assigned-clock-rates = <24000000>,
<266000000>,
<0>,
<599999999>;
port@1 {
mipi_dsi_in: endpoint {
remote-endpoint = <&lcdif_mipi_dsi>;
};
};
};
&mipi_dsi_bridge {
status = "okay";
panel@0 {
compatible = "raydium,rm67191";
reg = <0>;
pinctrl-0 = <&pinctrl_mipi_dsi_en>;
reset-gpio = <&gpio5 6 GPIO_ACTIVE_HIGH>;
dsi-lanes = <4>;
panel-width-mm = <68>;
panel-height-mm = <121>;
port {
panel1_in: endpoint {
remote-endpoint = <&mipi_dsi_bridge_out>;
};
};
};
port@2 {
mipi_dsi_bridge_out: endpoint {
remote-endpoint = <&panel1_in>;
};
};
};
&iomuxc {
imx8mq-evk {
pinctrl_mipi_dsi_en: mipi_dsi_en {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16
>;
};
};
};
#include "fsl-imx8mq-evk-lcdif-rm67191.dtsi"

117
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@ -0,0 +1,117 @@
/*
* Copyright 2018 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/ {
display-subsystem {
status = "disabled";
};
};
&irqsteer_dcss {
status = "disabled";
};
&dcss {
status = "disabled";
};
&hdmi {
status = "disabled";
};
&lcdif {
status = "okay";
max-res = <1080>, <1920>;
assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
<&clk IMX8MQ_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_CLK_25M>;
assigned-clock-rate = <120000000>,
<0>,
<599999999>;
port@0 {
lcdif_mipi_dsi: mipi-dsi-endpoint {
remote-endpoint = <&mipi_dsi_in>;
};
};
};
&mipi_dsi_phy {
status = "okay";
};
&mipi_dsi {
status = "okay";
as_bridge;
sync-pol = <1>;
assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF_SRC>,
<&clk IMX8MQ_CLK_DSI_CORE_SRC>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
<&clk IMX8MQ_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_SYS1_PLL_266M>,
<&clk IMX8MQ_CLK_25M>;
assigned-clock-rates = <24000000>,
<266000000>,
<0>,
<599999999>;
port@1 {
mipi_dsi_in: endpoint {
remote-endpoint = <&lcdif_mipi_dsi>;
};
};
};
&mipi_dsi_bridge {
status = "okay";
panel@0 {
compatible = "raydium,rm67191";
reg = <0>;
pinctrl-0 = <&pinctrl_mipi_dsi_en>;
reset-gpio = <&gpio5 6 GPIO_ACTIVE_HIGH>;
dsi-lanes = <4>;
panel-width-mm = <68>;
panel-height-mm = <121>;
port {
panel1_in: endpoint {
remote-endpoint = <&mipi_dsi_bridge_out>;
};
};
};
port@2 {
mipi_dsi_bridge_out: endpoint {
remote-endpoint = <&panel1_in>;
};
};
};
&iomuxc {
imx8mq-evk {
pinctrl_mipi_dsi_en: mipi_dsi_en {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16
>;
};
};
};
&synaptics_dsx_ts {
status = "okay";
};

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@ -600,16 +600,6 @@
};
};
dsi_touch: synaptics_dsx_ts@20 {
compatible = "synaptics_dsx";
reg = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_dsi_ts_int>;
interrupt-parent = <&gpio5>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
/* rest-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>; */
status = "disabled";
};
};
&i2c2 {
@ -670,6 +660,17 @@
ak4497,pdn-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
};
synaptics_dsx_ts: synaptics_dsx_ts@20 {
compatible = "synaptics_dsx";
reg = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_dsi_ts_int>;
interrupt-parent = <&gpio5>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
synaptics,diagonal-rotation;
status = "disabled";
};
adv_bridge: adv7535@3d {
compatible = "adi,adv7533";
reg = <0x3d>;