drm/i915: GFX_MODE Flush TLB Invalidate Mode must be '1' for scanline waits
On SNB, if bit 13 of GFX_MODE, Flush TLB Invalidate Mode, is not set to 1, the hardware can not program the scanline values. Those scanline values then control when the signal is sent from the display engine to the render ring for MI_WAIT_FOR_EVENTs. Note setting this bit means that TLB invalidations must be performed explicitly through the appropriate bits being set in PIPE_CONTROL. References: https://bugzilla.kernel.org/show_bug.cgi?id=52311 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@vger.kernel.org Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -515,6 +515,11 @@ static int init_render_ring(struct intel_ring_buffer *ring)
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if (INTEL_INFO(dev)->gen >= 6)
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I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
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/* Required for the hardware to program scanline values for waiting */
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if (INTEL_INFO(dev)->gen == 6)
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I915_WRITE(GFX_MODE,
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_MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
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if (IS_GEN7(dev))
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I915_WRITE(GFX_MODE_GEN7,
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_MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
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