ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4210
This patch adds the bus nodes for Exynos4210 SoC. Exynos4210 SoC has one power line for all buses to translate data between DRAM and sub-blocks. Following list specifies the detailed relation between DRAM and sub-blocks: - DMC/ACP clock for DMC (Dynamic Memory Controller) - ACLK200 clock for LCD0 - ACLK100 clock for PERIL/PERIR/MFC(PCLK) - ACLK160 clock for CAM/TV/LCD0/LCD1 - ACLK133 clock for FSYS/GPS - GDL/GDR clock for LEFTBUS/RIGHTBUS - SCLK_MFC clock for MFC Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
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@ -257,6 +257,165 @@
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power-domains = <&pd_lcd1>;
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#iommu-cells = <0>;
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};
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bus_dmc: bus_dmc {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_DMC>;
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clock-names = "bus";
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operating-points-v2 = <&bus_dmc_opp_table>;
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status = "disabled";
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};
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bus_acp: bus_acp {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_ACP>;
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clock-names = "bus";
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operating-points-v2 = <&bus_acp_opp_table>;
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status = "disabled";
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};
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bus_peri: bus_peri {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_ACLK100>;
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clock-names = "bus";
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operating-points-v2 = <&bus_peri_opp_table>;
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status = "disabled";
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};
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bus_fsys: bus_fsys {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_ACLK133>;
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clock-names = "bus";
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operating-points-v2 = <&bus_fsys_opp_table>;
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status = "disabled";
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};
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bus_display: bus_display {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_ACLK160>;
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clock-names = "bus";
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operating-points-v2 = <&bus_display_opp_table>;
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status = "disabled";
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};
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bus_lcd0: bus_lcd0 {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_ACLK200>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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bus_leftbus: bus_leftbus {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_GDL>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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bus_rightbus: bus_rightbus {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_GDR>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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bus_mfc: bus_mfc {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_SCLK_MFC>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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bus_dmc_opp_table: opp_table1 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@134000000 {
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opp-hz = /bits/ 64 <134000000>;
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opp-microvolt = <1025000>;
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};
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opp@267000000 {
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opp-hz = /bits/ 64 <267000000>;
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opp-microvolt = <1050000>;
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};
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opp@400000000 {
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opp-hz = /bits/ 64 <400000000>;
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opp-microvolt = <1150000>;
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};
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};
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bus_acp_opp_table: opp_table2 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@134000000 {
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opp-hz = /bits/ 64 <134000000>;
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};
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opp@160000000 {
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opp-hz = /bits/ 64 <160000000>;
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};
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opp@200000000 {
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opp-hz = /bits/ 64 <200000000>;
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};
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};
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bus_peri_opp_table: opp_table3 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@5000000 {
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opp-hz = /bits/ 64 <5000000>;
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};
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opp@100000000 {
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opp-hz = /bits/ 64 <100000000>;
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};
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};
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bus_fsys_opp_table: opp_table4 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@10000000 {
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opp-hz = /bits/ 64 <10000000>;
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};
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opp@134000000 {
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opp-hz = /bits/ 64 <134000000>;
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};
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};
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bus_display_opp_table: opp_table5 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@100000000 {
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opp-hz = /bits/ 64 <100000000>;
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};
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opp@134000000 {
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opp-hz = /bits/ 64 <134000000>;
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};
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opp@160000000 {
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opp-hz = /bits/ 64 <160000000>;
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};
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};
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bus_leftbus_opp_table: opp_table6 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@100000000 {
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opp-hz = /bits/ 64 <100000000>;
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};
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opp@160000000 {
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opp-hz = /bits/ 64 <160000000>;
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};
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opp@200000000 {
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opp-hz = /bits/ 64 <200000000>;
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};
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};
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};
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&gic {
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