media: atmel-isc: Rework the format list
To improve the readability of code, split the format array into two, one for the format description, other for the register configuration. Meanwhile, add the flag member to indicate the format can be achieved from the sensor or be produced by the controller, and rename members related to the register configuration. Also add more formats support: GREY, ARGB444, ARGB555 and ARGB32. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
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@ -89,34 +89,63 @@ struct isc_subdev_entity {
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struct list_head list;
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};
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/* Indicate the format is generated by the sensor */
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#define FMT_FLAG_FROM_SENSOR BIT(0)
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/* Indicate the format is produced by ISC itself */
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#define FMT_FLAG_FROM_CONTROLLER BIT(1)
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/* Indicate a Raw Bayer format */
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#define FMT_FLAG_RAW_FORMAT BIT(2)
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#define FMT_FLAG_RAW_FROM_SENSOR (FMT_FLAG_FROM_SENSOR | \
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FMT_FLAG_RAW_FORMAT)
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/*
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* struct isc_format - ISC media bus format information
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* @fourcc: Fourcc code for this format
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* @mbus_code: V4L2 media bus format code.
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* flags: Indicate format from sensor or converted by controller
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* @bpp: Bits per pixel (when stored in memory)
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* @reg_bps: reg value for bits per sample
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* (when transferred over a bus)
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* @pipeline: pipeline switch
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* @sd_support: Subdev supports this format
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* @isc_support: ISC can convert raw format to this format
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*/
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struct isc_format {
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u32 fourcc;
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u32 mbus_code;
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u32 flags;
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u8 bpp;
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u32 reg_bps;
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u32 reg_bay_cfg;
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u32 reg_rlp_mode;
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u32 reg_dcfg_imode;
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u32 reg_dctrl_dview;
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u32 pipeline;
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bool sd_support;
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bool isc_support;
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};
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/* Pipeline bitmap */
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#define WB_ENABLE BIT(0)
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#define CFA_ENABLE BIT(1)
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#define CC_ENABLE BIT(2)
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#define GAM_ENABLE BIT(3)
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#define GAM_BENABLE BIT(4)
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#define GAM_GENABLE BIT(5)
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#define GAM_RENABLE BIT(6)
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#define CSC_ENABLE BIT(7)
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#define CBC_ENABLE BIT(8)
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#define SUB422_ENABLE BIT(9)
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#define SUB420_ENABLE BIT(10)
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#define GAM_ENABLES (GAM_RENABLE | GAM_GENABLE | GAM_BENABLE | GAM_ENABLE)
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struct fmt_config {
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u32 fourcc;
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u32 pfe_cfg0_bps;
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u32 cfa_baycfg;
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u32 rlp_cfg_mode;
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u32 dcfg_imode;
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u32 dctrl_dview;
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u32 bits_pipeline;
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};
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#define HIST_ENTRIES 512
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#define HIST_BAYER (ISC_HIS_CFG_MODE_B + 1)
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@ -181,80 +210,320 @@ struct isc_device {
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struct list_head subdev_entities;
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};
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#define RAW_FMT_IND_START 0
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#define RAW_FMT_IND_END 11
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#define ISC_FMT_IND_START 12
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#define ISC_FMT_IND_END 14
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static struct isc_format formats_list[] = {
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{
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.fourcc = V4L2_PIX_FMT_SBGGR8,
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.mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
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.flags = FMT_FLAG_RAW_FROM_SENSOR,
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.bpp = 8,
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},
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{
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.fourcc = V4L2_PIX_FMT_SGBRG8,
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.mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
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.flags = FMT_FLAG_RAW_FROM_SENSOR,
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.bpp = 8,
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},
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{
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.fourcc = V4L2_PIX_FMT_SGRBG8,
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.mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
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.flags = FMT_FLAG_RAW_FROM_SENSOR,
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.bpp = 8,
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},
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{
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.fourcc = V4L2_PIX_FMT_SRGGB8,
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.mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
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.flags = FMT_FLAG_RAW_FROM_SENSOR,
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.bpp = 8,
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},
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{
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.fourcc = V4L2_PIX_FMT_SBGGR10,
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.mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
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.flags = FMT_FLAG_RAW_FROM_SENSOR,
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.bpp = 16,
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},
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{
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.fourcc = V4L2_PIX_FMT_SGBRG10,
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.mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
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.flags = FMT_FLAG_RAW_FROM_SENSOR,
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.bpp = 16,
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},
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{
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.fourcc = V4L2_PIX_FMT_SGRBG10,
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.mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
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.flags = FMT_FLAG_RAW_FROM_SENSOR,
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.bpp = 16,
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},
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{
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.fourcc = V4L2_PIX_FMT_SRGGB10,
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.mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
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.flags = FMT_FLAG_RAW_FROM_SENSOR,
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.bpp = 16,
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},
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{
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.fourcc = V4L2_PIX_FMT_SBGGR12,
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.mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
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.flags = FMT_FLAG_RAW_FROM_SENSOR,
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.bpp = 16,
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},
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{
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.fourcc = V4L2_PIX_FMT_SGBRG12,
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.mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
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.flags = FMT_FLAG_RAW_FROM_SENSOR,
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.bpp = 16,
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},
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{
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.fourcc = V4L2_PIX_FMT_SGRBG12,
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.mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
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.flags = FMT_FLAG_RAW_FROM_SENSOR,
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.bpp = 16,
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},
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{
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.fourcc = V4L2_PIX_FMT_SRGGB12,
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.mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
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.flags = FMT_FLAG_RAW_FROM_SENSOR,
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.bpp = 16,
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},
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{
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.fourcc = V4L2_PIX_FMT_YUV420,
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.mbus_code = 0x0,
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.flags = FMT_FLAG_FROM_CONTROLLER,
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.bpp = 12,
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},
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{
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.fourcc = V4L2_PIX_FMT_YUV422P,
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.mbus_code = 0x0,
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.flags = FMT_FLAG_FROM_CONTROLLER,
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.bpp = 16,
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},
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{
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.fourcc = V4L2_PIX_FMT_GREY,
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.mbus_code = MEDIA_BUS_FMT_Y8_1X8,
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.flags = FMT_FLAG_FROM_CONTROLLER |
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FMT_FLAG_FROM_SENSOR,
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.bpp = 8,
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},
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{
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.fourcc = V4L2_PIX_FMT_ARGB444,
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.mbus_code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE,
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.flags = FMT_FLAG_FROM_CONTROLLER,
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.bpp = 16,
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},
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{
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.fourcc = V4L2_PIX_FMT_ARGB555,
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.mbus_code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
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.flags = FMT_FLAG_FROM_CONTROLLER,
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.bpp = 16,
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},
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{
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.fourcc = V4L2_PIX_FMT_RGB565,
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.mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE,
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.flags = FMT_FLAG_FROM_CONTROLLER,
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.bpp = 16,
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},
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{
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.fourcc = V4L2_PIX_FMT_ARGB32,
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.mbus_code = MEDIA_BUS_FMT_ARGB8888_1X32,
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.flags = FMT_FLAG_FROM_CONTROLLER,
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.bpp = 32,
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},
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{
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.fourcc = V4L2_PIX_FMT_YUYV,
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.mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
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.flags = FMT_FLAG_FROM_CONTROLLER |
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FMT_FLAG_FROM_SENSOR,
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.bpp = 16,
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},
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};
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static struct isc_format isc_formats[] = {
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{ V4L2_PIX_FMT_SBGGR8, MEDIA_BUS_FMT_SBGGR8_1X8, 8,
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ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_DAT8,
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ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, 0x0,
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false, false },
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{ V4L2_PIX_FMT_SGBRG8, MEDIA_BUS_FMT_SGBRG8_1X8, 8,
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ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_GBGB, ISC_RLP_CFG_MODE_DAT8,
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ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, 0x0,
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false, false },
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{ V4L2_PIX_FMT_SGRBG8, MEDIA_BUS_FMT_SGRBG8_1X8, 8,
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ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_GRGR, ISC_RLP_CFG_MODE_DAT8,
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ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, 0x0,
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false, false },
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{ V4L2_PIX_FMT_SRGGB8, MEDIA_BUS_FMT_SRGGB8_1X8, 8,
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ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_RGRG, ISC_RLP_CFG_MODE_DAT8,
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ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, 0x0,
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false, false },
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{ V4L2_PIX_FMT_SBGGR10, MEDIA_BUS_FMT_SBGGR10_1X10, 16,
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ISC_PFG_CFG0_BPS_TEN, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_DAT10,
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ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,
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false, false },
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{ V4L2_PIX_FMT_SGBRG10, MEDIA_BUS_FMT_SGBRG10_1X10, 16,
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ISC_PFG_CFG0_BPS_TEN, ISC_BAY_CFG_GBGB, ISC_RLP_CFG_MODE_DAT10,
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ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,
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false, false },
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{ V4L2_PIX_FMT_SGRBG10, MEDIA_BUS_FMT_SGRBG10_1X10, 16,
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ISC_PFG_CFG0_BPS_TEN, ISC_BAY_CFG_GRGR, ISC_RLP_CFG_MODE_DAT10,
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ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,
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false, false },
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{ V4L2_PIX_FMT_SRGGB10, MEDIA_BUS_FMT_SRGGB10_1X10, 16,
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ISC_PFG_CFG0_BPS_TEN, ISC_BAY_CFG_RGRG, ISC_RLP_CFG_MODE_DAT10,
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ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,
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false, false },
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{ V4L2_PIX_FMT_SBGGR12, MEDIA_BUS_FMT_SBGGR12_1X12, 16,
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ISC_PFG_CFG0_BPS_TWELVE, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_DAT12,
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ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,
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false, false },
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{ V4L2_PIX_FMT_SGBRG12, MEDIA_BUS_FMT_SGBRG12_1X12, 16,
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ISC_PFG_CFG0_BPS_TWELVE, ISC_BAY_CFG_GBGB, ISC_RLP_CFG_MODE_DAT12,
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ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,
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false, false },
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{ V4L2_PIX_FMT_SGRBG12, MEDIA_BUS_FMT_SGRBG12_1X12, 16,
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ISC_PFG_CFG0_BPS_TWELVE, ISC_BAY_CFG_GRGR, ISC_RLP_CFG_MODE_DAT12,
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ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,
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false, false },
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{ V4L2_PIX_FMT_SRGGB12, MEDIA_BUS_FMT_SRGGB12_1X12, 16,
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ISC_PFG_CFG0_BPS_TWELVE, ISC_BAY_CFG_RGRG, ISC_RLP_CFG_MODE_DAT12,
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ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,
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false, false },
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{ V4L2_PIX_FMT_YUV420, 0x0, 12,
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ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_YYCC,
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ISC_DCFG_IMODE_YC420P, ISC_DCTRL_DVIEW_PLANAR, 0x7fb,
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false, false },
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{ V4L2_PIX_FMT_YUV422P, 0x0, 16,
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ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_YYCC,
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ISC_DCFG_IMODE_YC422P, ISC_DCTRL_DVIEW_PLANAR, 0x3fb,
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false, false },
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{ V4L2_PIX_FMT_RGB565, MEDIA_BUS_FMT_RGB565_2X8_LE, 16,
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ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_RGB565,
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ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x7b,
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false, false },
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{ V4L2_PIX_FMT_YUYV, MEDIA_BUS_FMT_YUYV8_2X8, 16,
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ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_DAT8,
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ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, 0x0,
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false, false },
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struct fmt_config fmt_configs_list[] = {
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{
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.fourcc = V4L2_PIX_FMT_SBGGR8,
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.pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
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.cfa_baycfg = ISC_BAY_CFG_BGBG,
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.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8,
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.dcfg_imode = ISC_DCFG_IMODE_PACKED8,
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.dctrl_dview = ISC_DCTRL_DVIEW_PACKED,
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.bits_pipeline = 0x0,
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},
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{
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.fourcc = V4L2_PIX_FMT_SGBRG8,
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.pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
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.cfa_baycfg = ISC_BAY_CFG_GBGB,
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.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8,
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.dcfg_imode = ISC_DCFG_IMODE_PACKED8,
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.dctrl_dview = ISC_DCTRL_DVIEW_PACKED,
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.bits_pipeline = 0x0,
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},
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{
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.fourcc = V4L2_PIX_FMT_SGRBG8,
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.pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
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.cfa_baycfg = ISC_BAY_CFG_GRGR,
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.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8,
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.dcfg_imode = ISC_DCFG_IMODE_PACKED8,
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.dctrl_dview = ISC_DCTRL_DVIEW_PACKED,
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.bits_pipeline = 0x0,
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},
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{
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.fourcc = V4L2_PIX_FMT_SRGGB8,
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.pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
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.cfa_baycfg = ISC_BAY_CFG_RGRG,
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.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8,
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.dcfg_imode = ISC_DCFG_IMODE_PACKED8,
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.dctrl_dview = ISC_DCTRL_DVIEW_PACKED,
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.bits_pipeline = 0x0,
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},
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{
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.fourcc = V4L2_PIX_FMT_SBGGR10,
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.pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
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.cfa_baycfg = ISC_BAY_CFG_BGBG,
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.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT10,
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.dcfg_imode = ISC_DCFG_IMODE_PACKED16,
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.dctrl_dview = ISC_DCTRL_DVIEW_PACKED,
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.bits_pipeline = 0x0,
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},
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{
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.fourcc = V4L2_PIX_FMT_SGBRG10,
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.pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
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.cfa_baycfg = ISC_BAY_CFG_GBGB,
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.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT10,
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.dcfg_imode = ISC_DCFG_IMODE_PACKED16,
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.dctrl_dview = ISC_DCTRL_DVIEW_PACKED,
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.bits_pipeline = 0x0,
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},
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{
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.fourcc = V4L2_PIX_FMT_SGRBG10,
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.pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
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.cfa_baycfg = ISC_BAY_CFG_GRGR,
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.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT10,
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.dcfg_imode = ISC_DCFG_IMODE_PACKED16,
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.dctrl_dview = ISC_DCTRL_DVIEW_PACKED,
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.bits_pipeline = 0x0,
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},
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{
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.fourcc = V4L2_PIX_FMT_SRGGB10,
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.pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
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.cfa_baycfg = ISC_BAY_CFG_RGRG,
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.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT10,
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.dcfg_imode = ISC_DCFG_IMODE_PACKED16,
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.dctrl_dview = ISC_DCTRL_DVIEW_PACKED,
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.bits_pipeline = 0x0,
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},
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{
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.fourcc = V4L2_PIX_FMT_SBGGR12,
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.pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
|
||||
.cfa_baycfg = ISC_BAY_CFG_BGBG,
|
||||
.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT12,
|
||||
.dcfg_imode = ISC_DCFG_IMODE_PACKED16,
|
||||
.dctrl_dview = ISC_DCTRL_DVIEW_PACKED,
|
||||
.bits_pipeline = 0x0,
|
||||
},
|
||||
{
|
||||
.fourcc = V4L2_PIX_FMT_SGBRG12,
|
||||
.pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
|
||||
.cfa_baycfg = ISC_BAY_CFG_GBGB,
|
||||
.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT12,
|
||||
.dcfg_imode = ISC_DCFG_IMODE_PACKED16,
|
||||
.dctrl_dview = ISC_DCTRL_DVIEW_PACKED,
|
||||
.bits_pipeline = 0x0
|
||||
},
|
||||
{
|
||||
.fourcc = V4L2_PIX_FMT_SGRBG12,
|
||||
.pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
|
||||
.cfa_baycfg = ISC_BAY_CFG_GRGR,
|
||||
.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT12,
|
||||
.dcfg_imode = ISC_DCFG_IMODE_PACKED16,
|
||||
.dctrl_dview = ISC_DCTRL_DVIEW_PACKED,
|
||||
.bits_pipeline = 0x0,
|
||||
},
|
||||
{
|
||||
.fourcc = V4L2_PIX_FMT_SRGGB12,
|
||||
.pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
|
||||
.cfa_baycfg = ISC_BAY_CFG_RGRG,
|
||||
.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT12,
|
||||
.dcfg_imode = ISC_DCFG_IMODE_PACKED16,
|
||||
.dctrl_dview = ISC_DCTRL_DVIEW_PACKED,
|
||||
.bits_pipeline = 0x0,
|
||||
},
|
||||
{
|
||||
.fourcc = V4L2_PIX_FMT_YUV420,
|
||||
.pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
|
||||
.cfa_baycfg = ISC_BAY_CFG_BGBG,
|
||||
.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC,
|
||||
.dcfg_imode = ISC_DCFG_IMODE_YC420P,
|
||||
.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR,
|
||||
.bits_pipeline = SUB420_ENABLE | SUB422_ENABLE |
|
||||
CBC_ENABLE | CSC_ENABLE |
|
||||
GAM_ENABLES |
|
||||
CFA_ENABLE | WB_ENABLE,
|
||||
},
|
||||
{
|
||||
.fourcc = V4L2_PIX_FMT_YUV422P,
|
||||
.pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
|
||||
.cfa_baycfg = ISC_BAY_CFG_BGBG,
|
||||
.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC,
|
||||
.dcfg_imode = ISC_DCFG_IMODE_YC422P,
|
||||
.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR,
|
||||
.bits_pipeline = SUB422_ENABLE |
|
||||
CBC_ENABLE | CSC_ENABLE |
|
||||
GAM_ENABLES |
|
||||
CFA_ENABLE | WB_ENABLE,
|
||||
},
|
||||
{
|
||||
.fourcc = V4L2_PIX_FMT_GREY,
|
||||
.pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
|
||||
.cfa_baycfg = ISC_BAY_CFG_BGBG,
|
||||
.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY8,
|
||||
.dcfg_imode = ISC_DCFG_IMODE_PACKED8,
|
||||
.dctrl_dview = ISC_DCTRL_DVIEW_PACKED,
|
||||
.bits_pipeline = CBC_ENABLE | CSC_ENABLE |
|
||||
GAM_ENABLES |
|
||||
CFA_ENABLE | WB_ENABLE,
|
||||
},
|
||||
{
|
||||
.fourcc = V4L2_PIX_FMT_ARGB444,
|
||||
.pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
|
||||
.cfa_baycfg = ISC_BAY_CFG_BGBG,
|
||||
.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB444,
|
||||
.dcfg_imode = ISC_DCFG_IMODE_PACKED16,
|
||||
.dctrl_dview = ISC_DCTRL_DVIEW_PACKED,
|
||||
.bits_pipeline = GAM_ENABLES | CFA_ENABLE | WB_ENABLE,
|
||||
},
|
||||
{
|
||||
.fourcc = V4L2_PIX_FMT_ARGB555,
|
||||
.pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
|
||||
.cfa_baycfg = ISC_BAY_CFG_BGBG,
|
||||
.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB555,
|
||||
.dcfg_imode = ISC_DCFG_IMODE_PACKED16,
|
||||
.dctrl_dview = ISC_DCTRL_DVIEW_PACKED,
|
||||
.bits_pipeline = GAM_ENABLES | CFA_ENABLE | WB_ENABLE,
|
||||
},
|
||||
{
|
||||
.fourcc = V4L2_PIX_FMT_RGB565,
|
||||
.pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
|
||||
.cfa_baycfg = ISC_BAY_CFG_BGBG,
|
||||
.rlp_cfg_mode = ISC_RLP_CFG_MODE_RGB565,
|
||||
.dcfg_imode = ISC_DCFG_IMODE_PACKED16,
|
||||
.dctrl_dview = ISC_DCTRL_DVIEW_PACKED,
|
||||
.bits_pipeline = GAM_ENABLES | CFA_ENABLE | WB_ENABLE,
|
||||
},
|
||||
{
|
||||
.fourcc = V4L2_PIX_FMT_ARGB32,
|
||||
.pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
|
||||
.cfa_baycfg = ISC_BAY_CFG_BGBG,
|
||||
.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB32,
|
||||
.dcfg_imode = ISC_DCFG_IMODE_PACKED32,
|
||||
.dctrl_dview = ISC_DCTRL_DVIEW_PACKED,
|
||||
.bits_pipeline = GAM_ENABLES | CFA_ENABLE | WB_ENABLE,
|
||||
},
|
||||
{
|
||||
.fourcc = V4L2_PIX_FMT_YUYV,
|
||||
.pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
|
||||
.cfa_baycfg = ISC_BAY_CFG_BGBG,
|
||||
.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8,
|
||||
.dcfg_imode = ISC_DCFG_IMODE_PACKED8,
|
||||
.dctrl_dview = ISC_DCTRL_DVIEW_PACKED,
|
||||
.bits_pipeline = 0x0
|
||||
},
|
||||
};
|
||||
|
||||
#define GAMMA_MAX 2
|
||||
|
@ -633,11 +902,27 @@ static inline bool sensor_is_preferred(const struct isc_format *isc_fmt)
|
|||
!isc_fmt->isc_support;
|
||||
}
|
||||
|
||||
static struct fmt_config *get_fmt_config(u32 fourcc)
|
||||
{
|
||||
struct fmt_config *config;
|
||||
int i;
|
||||
|
||||
config = &fmt_configs_list[0];
|
||||
for (i = 0; i < ARRAY_SIZE(fmt_configs_list); i++) {
|
||||
if (config->fourcc == fourcc)
|
||||
return config;
|
||||
|
||||
config++;
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void isc_start_dma(struct isc_device *isc)
|
||||
{
|
||||
struct regmap *regmap = isc->regmap;
|
||||
struct v4l2_pix_format *pixfmt = &isc->fmt.fmt.pix;
|
||||
u32 sizeimage = pixfmt->sizeimage;
|
||||
struct fmt_config *config = get_fmt_config(isc->current_fmt->fourcc);
|
||||
u32 dctrl_dview;
|
||||
dma_addr_t addr0;
|
||||
|
||||
|
@ -660,7 +945,7 @@ static void isc_start_dma(struct isc_device *isc)
|
|||
if (sensor_is_preferred(isc->current_fmt))
|
||||
dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
|
||||
else
|
||||
dctrl_dview = isc->current_fmt->reg_dctrl_dview;
|
||||
dctrl_dview = config->dctrl_dview;
|
||||
|
||||
regmap_write(regmap, ISC_DCTRL, dctrl_dview | ISC_DCTRL_IE_IS);
|
||||
regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_CAPTURE);
|
||||
|
@ -670,6 +955,7 @@ static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)
|
|||
{
|
||||
struct regmap *regmap = isc->regmap;
|
||||
struct isc_ctrls *ctrls = &isc->ctrls;
|
||||
struct fmt_config *config = get_fmt_config(isc->raw_fmt->fourcc);
|
||||
u32 val, bay_cfg;
|
||||
const u32 *gamma;
|
||||
unsigned int i;
|
||||
|
@ -683,7 +969,7 @@ static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)
|
|||
if (!pipeline)
|
||||
return;
|
||||
|
||||
bay_cfg = isc->raw_fmt->reg_bay_cfg;
|
||||
bay_cfg = config->cfa_baycfg;
|
||||
|
||||
regmap_write(regmap, ISC_WB_CFG, bay_cfg);
|
||||
regmap_write(regmap, ISC_WB_O_RGR, 0x0);
|
||||
|
@ -736,11 +1022,13 @@ static void isc_set_histogram(struct isc_device *isc)
|
|||
{
|
||||
struct regmap *regmap = isc->regmap;
|
||||
struct isc_ctrls *ctrls = &isc->ctrls;
|
||||
struct fmt_config *config = get_fmt_config(isc->raw_fmt->fourcc);
|
||||
|
||||
if (ctrls->awb && (ctrls->hist_stat != HIST_ENABLED)) {
|
||||
regmap_write(regmap, ISC_HIS_CFG, ISC_HIS_CFG_MODE_R |
|
||||
(isc->raw_fmt->reg_bay_cfg << ISC_HIS_CFG_BAYSEL_SHIFT) |
|
||||
ISC_HIS_CFG_RAR);
|
||||
regmap_write(regmap, ISC_HIS_CFG,
|
||||
ISC_HIS_CFG_MODE_R |
|
||||
(config->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT) |
|
||||
ISC_HIS_CFG_RAR);
|
||||
regmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_EN);
|
||||
regmap_write(regmap, ISC_INTEN, ISC_INT_HISDONE);
|
||||
ctrls->hist_id = ISC_HIS_CFG_MODE_R;
|
||||
|
@ -757,8 +1045,10 @@ static void isc_set_histogram(struct isc_device *isc)
|
|||
}
|
||||
|
||||
static inline void isc_get_param(const struct isc_format *fmt,
|
||||
u32 *rlp_mode, u32 *dcfg)
|
||||
u32 *rlp_mode, u32 *dcfg)
|
||||
{
|
||||
struct fmt_config *config = get_fmt_config(fmt->fourcc);
|
||||
|
||||
*dcfg = ISC_DCFG_YMBSIZE_BEATS8;
|
||||
|
||||
switch (fmt->fourcc) {
|
||||
|
@ -770,8 +1060,8 @@ static inline void isc_get_param(const struct isc_format *fmt,
|
|||
case V4L2_PIX_FMT_SGBRG12:
|
||||
case V4L2_PIX_FMT_SGRBG12:
|
||||
case V4L2_PIX_FMT_SRGGB12:
|
||||
*rlp_mode = fmt->reg_rlp_mode;
|
||||
*dcfg |= fmt->reg_dcfg_imode;
|
||||
*rlp_mode = config->rlp_cfg_mode;
|
||||
*dcfg |= config->dcfg_imode;
|
||||
break;
|
||||
default:
|
||||
*rlp_mode = ISC_RLP_CFG_MODE_DAT8;
|
||||
|
@ -784,20 +1074,22 @@ static int isc_configure(struct isc_device *isc)
|
|||
{
|
||||
struct regmap *regmap = isc->regmap;
|
||||
const struct isc_format *current_fmt = isc->current_fmt;
|
||||
struct fmt_config *curfmt_config = get_fmt_config(current_fmt->fourcc);
|
||||
struct fmt_config *rawfmt_config = get_fmt_config(isc->raw_fmt->fourcc);
|
||||
struct isc_subdev_entity *subdev = isc->current_subdev;
|
||||
u32 pfe_cfg0, rlp_mode, dcfg, mask, pipeline;
|
||||
|
||||
if (sensor_is_preferred(current_fmt)) {
|
||||
pfe_cfg0 = current_fmt->reg_bps;
|
||||
pfe_cfg0 = curfmt_config->pfe_cfg0_bps;
|
||||
pipeline = 0x0;
|
||||
isc_get_param(current_fmt, &rlp_mode, &dcfg);
|
||||
isc->ctrls.hist_stat = HIST_INIT;
|
||||
} else {
|
||||
pfe_cfg0 = isc->raw_fmt->reg_bps;
|
||||
pipeline = current_fmt->pipeline;
|
||||
rlp_mode = current_fmt->reg_rlp_mode;
|
||||
dcfg = current_fmt->reg_dcfg_imode | ISC_DCFG_YMBSIZE_BEATS8 |
|
||||
ISC_DCFG_CMBSIZE_BEATS8;
|
||||
pfe_cfg0 = rawfmt_config->pfe_cfg0_bps;
|
||||
pipeline = curfmt_config->bits_pipeline;
|
||||
rlp_mode = curfmt_config->rlp_cfg_mode;
|
||||
dcfg = curfmt_config->dcfg_imode |
|
||||
ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
|
||||
}
|
||||
|
||||
pfe_cfg0 |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE;
|
||||
|
@ -1382,6 +1674,7 @@ static void isc_awb_work(struct work_struct *w)
|
|||
struct isc_device *isc =
|
||||
container_of(w, struct isc_device, awb_work);
|
||||
struct regmap *regmap = isc->regmap;
|
||||
struct fmt_config *config = get_fmt_config(isc->raw_fmt->fourcc);
|
||||
struct isc_ctrls *ctrls = &isc->ctrls;
|
||||
u32 hist_id = ctrls->hist_id;
|
||||
u32 baysel;
|
||||
|
@ -1399,7 +1692,7 @@ static void isc_awb_work(struct work_struct *w)
|
|||
}
|
||||
|
||||
ctrls->hist_id = hist_id;
|
||||
baysel = isc->raw_fmt->reg_bay_cfg << ISC_HIS_CFG_BAYSEL_SHIFT;
|
||||
baysel = config->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT;
|
||||
|
||||
pm_runtime_get_sync(isc->dev);
|
||||
|
||||
|
@ -1500,10 +1793,10 @@ static void isc_async_unbind(struct v4l2_async_notifier *notifier,
|
|||
|
||||
static struct isc_format *find_format_by_code(unsigned int code, int *index)
|
||||
{
|
||||
struct isc_format *fmt = &isc_formats[0];
|
||||
struct isc_format *fmt = &formats_list[0];
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(isc_formats); i++) {
|
||||
for (i = 0; i < ARRAY_SIZE(formats_list); i++) {
|
||||
if (fmt->mbus_code == code) {
|
||||
*index = i;
|
||||
return fmt;
|
||||
|
@ -1520,37 +1813,36 @@ static int isc_formats_init(struct isc_device *isc)
|
|||
struct isc_format *fmt;
|
||||
struct v4l2_subdev *subdev = isc->current_subdev->sd;
|
||||
unsigned int num_fmts, i, j;
|
||||
u32 list_size = ARRAY_SIZE(formats_list);
|
||||
struct v4l2_subdev_mbus_code_enum mbus_code = {
|
||||
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
|
||||
};
|
||||
|
||||
fmt = &isc_formats[0];
|
||||
for (i = 0; i < ARRAY_SIZE(isc_formats); i++) {
|
||||
fmt->isc_support = false;
|
||||
fmt->sd_support = false;
|
||||
|
||||
fmt++;
|
||||
}
|
||||
|
||||
while (!v4l2_subdev_call(subdev, pad, enum_mbus_code,
|
||||
NULL, &mbus_code)) {
|
||||
mbus_code.index++;
|
||||
|
||||
fmt = find_format_by_code(mbus_code.code, &i);
|
||||
if (!fmt)
|
||||
if ((!fmt) || (!(fmt->flags & FMT_FLAG_FROM_SENSOR)))
|
||||
continue;
|
||||
|
||||
fmt->sd_support = true;
|
||||
|
||||
if (i <= RAW_FMT_IND_END) {
|
||||
for (j = ISC_FMT_IND_START; j <= ISC_FMT_IND_END; j++)
|
||||
isc_formats[j].isc_support = true;
|
||||
|
||||
if (fmt->flags & FMT_FLAG_RAW_FORMAT)
|
||||
isc->raw_fmt = fmt;
|
||||
}
|
||||
}
|
||||
|
||||
fmt = &isc_formats[0];
|
||||
for (i = 0, num_fmts = 0; i < ARRAY_SIZE(isc_formats); i++) {
|
||||
fmt = &formats_list[0];
|
||||
for (i = 0; i < list_size; i++) {
|
||||
if (fmt->flags & FMT_FLAG_FROM_CONTROLLER)
|
||||
fmt->isc_support = true;
|
||||
|
||||
fmt++;
|
||||
}
|
||||
|
||||
fmt = &formats_list[0];
|
||||
num_fmts = 0;
|
||||
for (i = 0; i < list_size; i++) {
|
||||
if (fmt->isc_support || fmt->sd_support)
|
||||
num_fmts++;
|
||||
|
||||
|
@ -1567,8 +1859,8 @@ static int isc_formats_init(struct isc_device *isc)
|
|||
if (!isc->user_formats)
|
||||
return -ENOMEM;
|
||||
|
||||
fmt = &isc_formats[0];
|
||||
for (i = 0, j = 0; i < ARRAY_SIZE(isc_formats); i++) {
|
||||
fmt = &formats_list[0];
|
||||
for (i = 0, j = 0; i < list_size; i++) {
|
||||
if (fmt->isc_support || fmt->sd_support)
|
||||
isc->user_formats[j++] = fmt;
|
||||
|
||||
|
|
Loading…
Reference in a new issue