mtd: rawnand: denali_dt: set clk_x_rate to 200 MHz unconditionally
commitpull/10/head3f6e698604
upstream. Since commit1bb8866677
("mtd: nand: denali: handle timing parameters by setup_data_interface()"), denali_dt.c gets the clock rate from the clock driver. The driver expects the frequency of the bus interface clock, whereas the clock driver of SOCFPGA provides the core clock. Thus, the setup_data_interface() hook calculates timing parameters based on a wrong frequency. To make it work without relying on the clock driver, hard-code the clock frequency, 200MHz. This is fine for existing DT of UniPhier, and also fixes the issue of SOCFPGA because both platforms use 200 MHz for the bus interface clock. Fixes:1bb8866677
("mtd: nand: denali: handle timing parameters by setup_data_interface()") Cc: linux-stable <stable@vger.kernel.org> #4.14+ Reported-by: Philipp Rosenberger <p.rosenberger@linutronix.de> Suggested-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Richard Weinberger <richard@nod.at> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Sudip Mukherjee <sudipm.mukherjee@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
parent
c4bfed85ba
commit
f1059632a4
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@ -122,7 +122,11 @@ static int denali_dt_probe(struct platform_device *pdev)
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if (ret)
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return ret;
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denali->clk_x_rate = clk_get_rate(dt->clk);
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/*
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* Hardcode the clock rate for the backward compatibility.
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* This works for both SOCFPGA and UniPhier.
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*/
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denali->clk_x_rate = 200000000;
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ret = denali_init(denali);
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if (ret)
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