arm64: KVM: add missing dsb before invalidating Stage-2 TLBs
When performing a Stage-2 TLB invalidation, it is necessary to make sure the write to the page tables is observable by all CPUs. For this purpose, add dsb instructions to __kvm_tlb_flush_vmid_ipa and __kvm_flush_vm_context before doing the TLB invalidation itself. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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@ -604,6 +604,8 @@ END(__kvm_vcpu_run)
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// void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
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ENTRY(__kvm_tlb_flush_vmid_ipa)
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dsb ishst
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kern_hyp_va x0
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ldr x2, [x0, #KVM_VTTBR]
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msr vttbr_el2, x2
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@ -625,6 +627,7 @@ ENTRY(__kvm_tlb_flush_vmid_ipa)
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ENDPROC(__kvm_tlb_flush_vmid_ipa)
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ENTRY(__kvm_flush_vm_context)
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dsb ishst
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tlbi alle1is
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ic ialluis
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dsb sy
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