Merge commit 'v2.6.31-rc8' into sched/core
Merge reason: bump from rc5 to rc8, but also pick up TP_perf_assign() API, a patch will be queued that depends on it. Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
commit
f14eff1cc2
|
@ -94,28 +94,37 @@ What: /sys/block/<disk>/queue/physical_block_size
|
|||
Date: May 2009
|
||||
Contact: Martin K. Petersen <martin.petersen@oracle.com>
|
||||
Description:
|
||||
This is the smallest unit the storage device can write
|
||||
without resorting to read-modify-write operation. It is
|
||||
usually the same as the logical block size but may be
|
||||
bigger. One example is SATA drives with 4KB sectors
|
||||
that expose a 512-byte logical block size to the
|
||||
operating system.
|
||||
This is the smallest unit a physical storage device can
|
||||
write atomically. It is usually the same as the logical
|
||||
block size but may be bigger. One example is SATA
|
||||
drives with 4KB sectors that expose a 512-byte logical
|
||||
block size to the operating system. For stacked block
|
||||
devices the physical_block_size variable contains the
|
||||
maximum physical_block_size of the component devices.
|
||||
|
||||
What: /sys/block/<disk>/queue/minimum_io_size
|
||||
Date: April 2009
|
||||
Contact: Martin K. Petersen <martin.petersen@oracle.com>
|
||||
Description:
|
||||
Storage devices may report a preferred minimum I/O size,
|
||||
which is the smallest request the device can perform
|
||||
without incurring a read-modify-write penalty. For disk
|
||||
drives this is often the physical block size. For RAID
|
||||
arrays it is often the stripe chunk size.
|
||||
Storage devices may report a granularity or preferred
|
||||
minimum I/O size which is the smallest request the
|
||||
device can perform without incurring a performance
|
||||
penalty. For disk drives this is often the physical
|
||||
block size. For RAID arrays it is often the stripe
|
||||
chunk size. A properly aligned multiple of
|
||||
minimum_io_size is the preferred request size for
|
||||
workloads where a high number of I/O operations is
|
||||
desired.
|
||||
|
||||
What: /sys/block/<disk>/queue/optimal_io_size
|
||||
Date: April 2009
|
||||
Contact: Martin K. Petersen <martin.petersen@oracle.com>
|
||||
Description:
|
||||
Storage devices may report an optimal I/O size, which is
|
||||
the device's preferred unit of receiving I/O. This is
|
||||
rarely reported for disk drives. For RAID devices it is
|
||||
usually the stripe width or the internal block size.
|
||||
the device's preferred unit for sustained I/O. This is
|
||||
rarely reported for disk drives. For RAID arrays it is
|
||||
usually the stripe width or the internal track size. A
|
||||
properly aligned multiple of optimal_io_size is the
|
||||
preferred request size for workloads where sustained
|
||||
throughput is desired. If no optimal I/O size is
|
||||
reported this file contains 0.
|
||||
|
|
|
@ -449,8 +449,8 @@ printk(KERN_INFO "i = %u\n", i);
|
|||
</para>
|
||||
|
||||
<programlisting>
|
||||
__u32 ipaddress;
|
||||
printk(KERN_INFO "my ip: %d.%d.%d.%d\n", NIPQUAD(ipaddress));
|
||||
__be32 ipaddress;
|
||||
printk(KERN_INFO "my ip: %pI4\n", &ipaddress);
|
||||
</programlisting>
|
||||
|
||||
<para>
|
||||
|
|
|
@ -21,6 +21,8 @@ ffff8000 ffffffff copy_user_page / clear_user_page use.
|
|||
For SA11xx and Xscale, this is used to
|
||||
setup a minicache mapping.
|
||||
|
||||
ffff4000 ffffffff cache aliasing on ARMv6 and later CPUs.
|
||||
|
||||
ffff1000 ffff7fff Reserved.
|
||||
Platforms must not use this address range.
|
||||
|
||||
|
|
|
@ -123,6 +123,9 @@ available from the same CVS repository.
|
|||
There are user and developer mailing lists available through the v9fs project
|
||||
on sourceforge (http://sourceforge.net/projects/v9fs).
|
||||
|
||||
A stand-alone version of the module (which should build for any 2.6 kernel)
|
||||
is available via (http://github.com/ericvh/9p-sac/tree/master)
|
||||
|
||||
News and other information is maintained on SWiK (http://swik.net/v9fs).
|
||||
|
||||
Bug reports may be issued through the kernel.org bugzilla
|
||||
|
|
|
@ -23,16 +23,14 @@ it does support include:
|
|||
|
||||
(*) Security (currently only AFS kaserver and KerberosIV tickets).
|
||||
|
||||
(*) File reading.
|
||||
(*) File reading and writing.
|
||||
|
||||
(*) Automounting.
|
||||
|
||||
(*) Local caching (via fscache).
|
||||
|
||||
It does not yet support the following AFS features:
|
||||
|
||||
(*) Write support.
|
||||
|
||||
(*) Local caching.
|
||||
|
||||
(*) pioctl() system call.
|
||||
|
||||
|
||||
|
@ -56,7 +54,7 @@ They permit the debugging messages to be turned on dynamically by manipulating
|
|||
the masks in the following files:
|
||||
|
||||
/sys/module/af_rxrpc/parameters/debug
|
||||
/sys/module/afs/parameters/debug
|
||||
/sys/module/kafs/parameters/debug
|
||||
|
||||
|
||||
=====
|
||||
|
@ -66,9 +64,9 @@ USAGE
|
|||
When inserting the driver modules the root cell must be specified along with a
|
||||
list of volume location server IP addresses:
|
||||
|
||||
insmod af_rxrpc.o
|
||||
insmod rxkad.o
|
||||
insmod kafs.o rootcell=cambridge.redhat.com:172.16.18.73:172.16.18.91
|
||||
modprobe af_rxrpc
|
||||
modprobe rxkad
|
||||
modprobe kafs rootcell=cambridge.redhat.com:172.16.18.73:172.16.18.91
|
||||
|
||||
The first module is the AF_RXRPC network protocol driver. This provides the
|
||||
RxRPC remote operation protocol and may also be accessed from userspace. See:
|
||||
|
@ -81,7 +79,7 @@ is the actual filesystem driver for the AFS filesystem.
|
|||
Once the module has been loaded, more modules can be added by the following
|
||||
procedure:
|
||||
|
||||
echo add grand.central.org 18.7.14.88:128.2.191.224 >/proc/fs/afs/cells
|
||||
echo add grand.central.org 18.9.48.14:128.2.203.61:130.237.48.87 >/proc/fs/afs/cells
|
||||
|
||||
Where the parameters to the "add" command are the name of a cell and a list of
|
||||
volume location servers within that cell, with the latter separated by colons.
|
||||
|
@ -101,7 +99,7 @@ The name of the volume can be suffixes with ".backup" or ".readonly" to
|
|||
specify connection to only volumes of those types.
|
||||
|
||||
The name of the cell is optional, and if not given during a mount, then the
|
||||
named volume will be looked up in the cell specified during insmod.
|
||||
named volume will be looked up in the cell specified during modprobe.
|
||||
|
||||
Additional cells can be added through /proc (see later section).
|
||||
|
||||
|
@ -163,14 +161,14 @@ THE CELL DATABASE
|
|||
|
||||
The filesystem maintains an internal database of all the cells it knows and the
|
||||
IP addresses of the volume location servers for those cells. The cell to which
|
||||
the system belongs is added to the database when insmod is performed by the
|
||||
the system belongs is added to the database when modprobe is performed by the
|
||||
"rootcell=" argument or, if compiled in, using a "kafs.rootcell=" argument on
|
||||
the kernel command line.
|
||||
|
||||
Further cells can be added by commands similar to the following:
|
||||
|
||||
echo add CELLNAME VLADDR[:VLADDR][:VLADDR]... >/proc/fs/afs/cells
|
||||
echo add grand.central.org 18.7.14.88:128.2.191.224 >/proc/fs/afs/cells
|
||||
echo add grand.central.org 18.9.48.14:128.2.203.61:130.237.48.87 >/proc/fs/afs/cells
|
||||
|
||||
No other cell database operations are available at this time.
|
||||
|
||||
|
@ -233,7 +231,7 @@ insmod /tmp/kafs.o rootcell=cambridge.redhat.com:172.16.18.91
|
|||
mount -t afs \%root.afs. /afs
|
||||
mount -t afs \%cambridge.redhat.com:root.cell. /afs/cambridge.redhat.com/
|
||||
|
||||
echo add grand.central.org 18.7.14.88:128.2.191.224 > /proc/fs/afs/cells
|
||||
echo add grand.central.org 18.9.48.14:128.2.203.61:130.237.48.87 > /proc/fs/afs/cells
|
||||
mount -t afs "#grand.central.org:root.cell." /afs/grand.central.org/
|
||||
mount -t afs "#grand.central.org:root.archive." /afs/grand.central.org/archive
|
||||
mount -t afs "#grand.central.org:root.contrib." /afs/grand.central.org/contrib
|
||||
|
|
|
@ -1167,13 +1167,11 @@ CHAPTER 3: PER-PROCESS PARAMETERS
|
|||
3.1 /proc/<pid>/oom_adj - Adjust the oom-killer score
|
||||
------------------------------------------------------
|
||||
|
||||
This file can be used to adjust the score used to select which processes should
|
||||
be killed in an out-of-memory situation. The oom_adj value is a characteristic
|
||||
of the task's mm, so all threads that share an mm with pid will have the same
|
||||
oom_adj value. A high value will increase the likelihood of this process being
|
||||
killed by the oom-killer. Valid values are in the range -16 to +15 as
|
||||
explained below and a special value of -17, which disables oom-killing
|
||||
altogether for threads sharing pid's mm.
|
||||
This file can be used to adjust the score used to select which processes
|
||||
should be killed in an out-of-memory situation. Giving it a high score will
|
||||
increase the likelihood of this process being killed by the oom-killer. Valid
|
||||
values are in the range -16 to +15, plus the special value -17, which disables
|
||||
oom-killing altogether for this process.
|
||||
|
||||
The process to be killed in an out-of-memory situation is selected among all others
|
||||
based on its badness score. This value equals the original memory size of the process
|
||||
|
@ -1187,9 +1185,6 @@ the parent's score if they do not share the same memory. Thus forking servers
|
|||
are the prime candidates to be killed. Having only one 'hungry' child will make
|
||||
parent less preferable than the child.
|
||||
|
||||
/proc/<pid>/oom_adj cannot be changed for kthreads since they are immune from
|
||||
oom-killing already.
|
||||
|
||||
/proc/<pid>/oom_score shows process' current badness score.
|
||||
|
||||
The following heuristics are then applied:
|
||||
|
|
|
@ -139,6 +139,7 @@ Code Seq# Include File Comments
|
|||
'm' all linux/synclink.h conflict!
|
||||
'm' 00-1F net/irda/irmod.h conflict!
|
||||
'n' 00-7F linux/ncp_fs.h
|
||||
'n' 80-8F linux/nilfs2_fs.h NILFS2
|
||||
'n' E0-FF video/matrox.h matroxfb
|
||||
'o' 00-1F fs/ocfs2/ocfs2_fs.h OCFS2
|
||||
'o' 00-03 include/mtd/ubi-user.h conflict! (OCFS2 and UBI overlaps)
|
||||
|
|
|
@ -1115,6 +1115,10 @@ and is between 256 and 4096 characters. It is defined in the file
|
|||
libata.dma=4 Compact Flash DMA only
|
||||
Combinations also work, so libata.dma=3 enables DMA
|
||||
for disks and CDROMs, but not CFs.
|
||||
|
||||
libata.ignore_hpa= [LIBATA] Ignore HPA limit
|
||||
libata.ignore_hpa=0 keep BIOS limits (default)
|
||||
libata.ignore_hpa=1 ignore limits, using full disk
|
||||
|
||||
libata.noacpi [LIBATA] Disables use of ACPI in libata suspend/resume
|
||||
when set.
|
||||
|
|
|
@ -36,8 +36,6 @@ detailed description):
|
|||
- Bluetooth enable and disable
|
||||
- video output switching, expansion control
|
||||
- ThinkLight on and off
|
||||
- limited docking and undocking
|
||||
- UltraBay eject
|
||||
- CMOS/UCMS control
|
||||
- LED control
|
||||
- ACPI sounds
|
||||
|
@ -729,131 +727,6 @@ cannot be read or if it is unknown, thinkpad-acpi will report it as "off".
|
|||
It is impossible to know if the status returned through sysfs is valid.
|
||||
|
||||
|
||||
Docking / undocking -- /proc/acpi/ibm/dock
|
||||
------------------------------------------
|
||||
|
||||
Docking and undocking (e.g. with the X4 UltraBase) requires some
|
||||
actions to be taken by the operating system to safely make or break
|
||||
the electrical connections with the dock.
|
||||
|
||||
The docking feature of this driver generates the following ACPI events:
|
||||
|
||||
ibm/dock GDCK 00000003 00000001 -- eject request
|
||||
ibm/dock GDCK 00000003 00000002 -- undocked
|
||||
ibm/dock GDCK 00000000 00000003 -- docked
|
||||
|
||||
NOTE: These events will only be generated if the laptop was docked
|
||||
when originally booted. This is due to the current lack of support for
|
||||
hot plugging of devices in the Linux ACPI framework. If the laptop was
|
||||
booted while not in the dock, the following message is shown in the
|
||||
logs:
|
||||
|
||||
Mar 17 01:42:34 aero kernel: thinkpad_acpi: dock device not present
|
||||
|
||||
In this case, no dock-related events are generated but the dock and
|
||||
undock commands described below still work. They can be executed
|
||||
manually or triggered by Fn key combinations (see the example acpid
|
||||
configuration files included in the driver tarball package available
|
||||
on the web site).
|
||||
|
||||
When the eject request button on the dock is pressed, the first event
|
||||
above is generated. The handler for this event should issue the
|
||||
following command:
|
||||
|
||||
echo undock > /proc/acpi/ibm/dock
|
||||
|
||||
After the LED on the dock goes off, it is safe to eject the laptop.
|
||||
Note: if you pressed this key by mistake, go ahead and eject the
|
||||
laptop, then dock it back in. Otherwise, the dock may not function as
|
||||
expected.
|
||||
|
||||
When the laptop is docked, the third event above is generated. The
|
||||
handler for this event should issue the following command to fully
|
||||
enable the dock:
|
||||
|
||||
echo dock > /proc/acpi/ibm/dock
|
||||
|
||||
The contents of the /proc/acpi/ibm/dock file shows the current status
|
||||
of the dock, as provided by the ACPI framework.
|
||||
|
||||
The docking support in this driver does not take care of enabling or
|
||||
disabling any other devices you may have attached to the dock. For
|
||||
example, a CD drive plugged into the UltraBase needs to be disabled or
|
||||
enabled separately. See the provided example acpid configuration files
|
||||
for how this can be accomplished.
|
||||
|
||||
There is no support yet for PCI devices that may be attached to a
|
||||
docking station, e.g. in the ThinkPad Dock II. The driver currently
|
||||
does not recognize, enable or disable such devices. This means that
|
||||
the only docking stations currently supported are the X-series
|
||||
UltraBase docks and "dumb" port replicators like the Mini Dock (the
|
||||
latter don't need any ACPI support, actually).
|
||||
|
||||
|
||||
UltraBay eject -- /proc/acpi/ibm/bay
|
||||
------------------------------------
|
||||
|
||||
Inserting or ejecting an UltraBay device requires some actions to be
|
||||
taken by the operating system to safely make or break the electrical
|
||||
connections with the device.
|
||||
|
||||
This feature generates the following ACPI events:
|
||||
|
||||
ibm/bay MSTR 00000003 00000000 -- eject request
|
||||
ibm/bay MSTR 00000001 00000000 -- eject lever inserted
|
||||
|
||||
NOTE: These events will only be generated if the UltraBay was present
|
||||
when the laptop was originally booted (on the X series, the UltraBay
|
||||
is in the dock, so it may not be present if the laptop was undocked).
|
||||
This is due to the current lack of support for hot plugging of devices
|
||||
in the Linux ACPI framework. If the laptop was booted without the
|
||||
UltraBay, the following message is shown in the logs:
|
||||
|
||||
Mar 17 01:42:34 aero kernel: thinkpad_acpi: bay device not present
|
||||
|
||||
In this case, no bay-related events are generated but the eject
|
||||
command described below still works. It can be executed manually or
|
||||
triggered by a hot key combination.
|
||||
|
||||
Sliding the eject lever generates the first event shown above. The
|
||||
handler for this event should take whatever actions are necessary to
|
||||
shut down the device in the UltraBay (e.g. call idectl), then issue
|
||||
the following command:
|
||||
|
||||
echo eject > /proc/acpi/ibm/bay
|
||||
|
||||
After the LED on the UltraBay goes off, it is safe to pull out the
|
||||
device.
|
||||
|
||||
When the eject lever is inserted, the second event above is
|
||||
generated. The handler for this event should take whatever actions are
|
||||
necessary to enable the UltraBay device (e.g. call idectl).
|
||||
|
||||
The contents of the /proc/acpi/ibm/bay file shows the current status
|
||||
of the UltraBay, as provided by the ACPI framework.
|
||||
|
||||
EXPERIMENTAL warm eject support on the 600e/x, A22p and A3x (To use
|
||||
this feature, you need to supply the experimental=1 parameter when
|
||||
loading the module):
|
||||
|
||||
These models do not have a button near the UltraBay device to request
|
||||
a hot eject but rather require the laptop to be put to sleep
|
||||
(suspend-to-ram) before the bay device is ejected or inserted).
|
||||
The sequence of steps to eject the device is as follows:
|
||||
|
||||
echo eject > /proc/acpi/ibm/bay
|
||||
put the ThinkPad to sleep
|
||||
remove the drive
|
||||
resume from sleep
|
||||
cat /proc/acpi/ibm/bay should show that the drive was removed
|
||||
|
||||
On the A3x, both the UltraBay 2000 and UltraBay Plus devices are
|
||||
supported. Use "eject2" instead of "eject" for the second bay.
|
||||
|
||||
Note: the UltraBay eject support on the 600e/x, A22p and A3x is
|
||||
EXPERIMENTAL and may not work as expected. USE WITH CAUTION!
|
||||
|
||||
|
||||
CMOS/UCMS control
|
||||
-----------------
|
||||
|
||||
|
|
|
@ -30,9 +30,9 @@ State
|
|||
The validator tracks lock-class usage history into 4n + 1 separate state bits:
|
||||
|
||||
- 'ever held in STATE context'
|
||||
- 'ever head as readlock in STATE context'
|
||||
- 'ever head with STATE enabled'
|
||||
- 'ever head as readlock with STATE enabled'
|
||||
- 'ever held as readlock in STATE context'
|
||||
- 'ever held with STATE enabled'
|
||||
- 'ever held as readlock with STATE enabled'
|
||||
|
||||
Where STATE can be either one of (kernel/lockdep_states.h)
|
||||
- hardirq
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
0 -> Unknown EM2800 video grabber (em2800) [eb1a:2800]
|
||||
1 -> Unknown EM2750/28xx video grabber (em2820/em2840) [eb1a:2820,eb1a:2821,eb1a:2860,eb1a:2861,eb1a:2870,eb1a:2881,eb1a:2883]
|
||||
1 -> Unknown EM2750/28xx video grabber (em2820/em2840) [eb1a:2710,eb1a:2820,eb1a:2821,eb1a:2860,eb1a:2861,eb1a:2870,eb1a:2881,eb1a:2883]
|
||||
2 -> Terratec Cinergy 250 USB (em2820/em2840) [0ccd:0036]
|
||||
3 -> Pinnacle PCTV USB 2 (em2820/em2840) [2304:0208]
|
||||
4 -> Hauppauge WinTV USB 2 (em2820/em2840) [2040:4200,2040:4201]
|
||||
|
|
|
@ -153,8 +153,8 @@
|
|||
152 -> Asus Tiger Rev:1.00 [1043:4857]
|
||||
153 -> Kworld Plus TV Analog Lite PCI [17de:7128]
|
||||
154 -> Avermedia AVerTV GO 007 FM Plus [1461:f31d]
|
||||
155 -> Hauppauge WinTV-HVR1120 ATSC/QAM-Hybrid [0070:6706,0070:6708]
|
||||
156 -> Hauppauge WinTV-HVR1110r3 DVB-T/Hybrid [0070:6707,0070:6709,0070:670a]
|
||||
155 -> Hauppauge WinTV-HVR1150 ATSC/QAM-Hybrid [0070:6706,0070:6708]
|
||||
156 -> Hauppauge WinTV-HVR1120 DVB-T/Hybrid [0070:6707,0070:6709,0070:670a]
|
||||
157 -> Avermedia AVerTV Studio 507UA [1461:a11b]
|
||||
158 -> AVerMedia Cardbus TV/Radio (E501R) [1461:b7e9]
|
||||
159 -> Beholder BeholdTV 505 RDS [0000:505B]
|
||||
|
|
22
MAINTAINERS
22
MAINTAINERS
|
@ -904,7 +904,7 @@ F: drivers/input/misc/ati_remote2.c
|
|||
|
||||
ATLX ETHERNET DRIVERS
|
||||
M: Jay Cliburn <jcliburn@gmail.com>
|
||||
M: Chris Snook <csnook@redhat.com>
|
||||
M: Chris Snook <chris.snook@gmail.com>
|
||||
M: Jie Yang <jie.yang@atheros.com>
|
||||
L: atl1-devel@lists.sourceforge.net
|
||||
W: http://sourceforge.net/projects/atl1
|
||||
|
@ -2238,6 +2238,14 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-2.6.git
|
|||
S: Maintained
|
||||
F: drivers/media/video/gspca/pac207.c
|
||||
|
||||
GSPCA SN9C20X SUBDRIVER
|
||||
P: Brian Johnson
|
||||
M: brijohn@gmail.com
|
||||
L: linux-media@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-2.6.git
|
||||
S: Maintained
|
||||
F: drivers/media/video/gspca/sn9c20x.c
|
||||
|
||||
GSPCA T613 SUBDRIVER
|
||||
M: Leandro Costantino <lcostantino@gmail.com>
|
||||
L: linux-media@vger.kernel.org
|
||||
|
@ -3421,6 +3429,7 @@ F: drivers/mfd/
|
|||
|
||||
MULTIMEDIA CARD (MMC), SECURE DIGITAL (SD) AND SDIO SUBSYSTEM
|
||||
S: Orphan
|
||||
L: linux-mmc@vger.kernel.org
|
||||
F: drivers/mmc/
|
||||
F: include/linux/mmc/
|
||||
|
||||
|
@ -3555,6 +3564,9 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6.git
|
|||
S: Maintained
|
||||
F: net/
|
||||
F: include/net/
|
||||
F: include/linux/in.h
|
||||
F: include/linux/net.h
|
||||
F: include/linux/netdevice.h
|
||||
|
||||
NETWORKING [IPv4/IPv6]
|
||||
M: "David S. Miller" <davem@davemloft.net>
|
||||
|
@ -3590,6 +3602,8 @@ W: http://www.linuxfoundation.org/en/Net
|
|||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6.git
|
||||
S: Odd Fixes
|
||||
F: drivers/net/
|
||||
F: include/linux/if_*
|
||||
F: include/linux/*device.h
|
||||
|
||||
NETXEN (1/10) GbE SUPPORT
|
||||
M: Dhananjay Phadke <dhananjay@netxen.com>
|
||||
|
@ -3796,7 +3810,7 @@ W: http://open-osd.org
|
|||
T: git git://git.open-osd.org/open-osd.git
|
||||
S: Maintained
|
||||
F: drivers/scsi/osd/
|
||||
F: drivers/include/scsi/osd_*
|
||||
F: include/scsi/osd_*
|
||||
F: fs/exofs/
|
||||
|
||||
P54 WIRELESS DRIVER
|
||||
|
@ -4995,7 +5009,9 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial.git
|
|||
S: Maintained
|
||||
|
||||
TTY LAYER
|
||||
S: Orphan
|
||||
M: Greg Kroah-Hartman <gregkh@suse.de>
|
||||
S: Maintained
|
||||
T: quilt kernel.org/pub/linux/kernel/people/gregkh/gregkh-2.6/
|
||||
F: drivers/char/tty_*
|
||||
F: drivers/serial/serial_core.c
|
||||
F: include/linux/serial_core.h
|
||||
|
|
2
Makefile
2
Makefile
|
@ -1,7 +1,7 @@
|
|||
VERSION = 2
|
||||
PATCHLEVEL = 6
|
||||
SUBLEVEL = 31
|
||||
EXTRAVERSION = -rc5
|
||||
EXTRAVERSION = -rc8
|
||||
NAME = Man-Eating Seals of Antiquity
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
@ -15,7 +15,10 @@ worry too much about getting the wrong person. If you are unsure send it
|
|||
to the person responsible for the code relevant to what you were doing.
|
||||
If it occurs repeatably try and describe how to recreate it. That is
|
||||
worth even more than the oops itself. The list of maintainers and
|
||||
mailing lists is in the MAINTAINERS file in this directory.
|
||||
mailing lists is in the MAINTAINERS file in this directory. If you
|
||||
know the file name that causes the problem you can use the following
|
||||
command in this directory to find some of the maintainers of that file:
|
||||
perl scripts/get_maintainer.pl -f <filename>
|
||||
|
||||
If it is a security bug, please copy the Security Contact listed
|
||||
in the MAINTAINERS file. They can help coordinate bugfix and disclosure.
|
||||
|
|
|
@ -29,7 +29,6 @@ unsigned int __machine_arch_type;
|
|||
|
||||
static void putstr(const char *ptr);
|
||||
|
||||
#include <linux/compiler.h>
|
||||
#include <mach/uncompress.h>
|
||||
|
||||
#ifdef CONFIG_DEBUG_ICEDCC
|
||||
|
|
|
@ -17,6 +17,7 @@
|
|||
#include <linux/err.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/clk.h>
|
||||
|
||||
#include <asm/clkdev.h>
|
||||
#include <mach/clkdev.h>
|
||||
|
|
|
@ -629,7 +629,7 @@ CONFIG_SCSI_LOWLEVEL=y
|
|||
CONFIG_ATA=y
|
||||
# CONFIG_ATA_NONSTANDARD is not set
|
||||
CONFIG_SATA_PMP=y
|
||||
# CONFIG_SATA_AHCI is not set
|
||||
CONFIG_SATA_AHCI=y
|
||||
# CONFIG_SATA_SIL24 is not set
|
||||
CONFIG_ATA_SFF=y
|
||||
# CONFIG_SATA_SVW is not set
|
||||
|
|
|
@ -1,15 +1,15 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.30-rc1
|
||||
# Wed Apr 8 10:18:06 2009
|
||||
# Linux kernel version: 2.6.31-rc4
|
||||
# Fri Jul 24 16:08:06 2009
|
||||
#
|
||||
CONFIG_ARM=y
|
||||
CONFIG_HAVE_PWM=y
|
||||
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
|
||||
CONFIG_GENERIC_GPIO=y
|
||||
CONFIG_GENERIC_TIME=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS=y
|
||||
CONFIG_MMU=y
|
||||
# CONFIG_NO_IOPORT is not set
|
||||
CONFIG_GENERIC_HARDIRQS=y
|
||||
CONFIG_STACKTRACE_SUPPORT=y
|
||||
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
|
||||
|
@ -18,14 +18,13 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
|
|||
CONFIG_HARDIRQS_SW_RESEND=y
|
||||
CONFIG_GENERIC_IRQ_PROBE=y
|
||||
CONFIG_RWSEM_GENERIC_SPINLOCK=y
|
||||
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
|
||||
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
|
||||
CONFIG_GENERIC_HWEIGHT=y
|
||||
CONFIG_GENERIC_CALIBRATE_DELAY=y
|
||||
CONFIG_ARCH_MTD_XIP=y
|
||||
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
|
||||
CONFIG_VECTORS_BASE=0xffff0000
|
||||
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
|
||||
CONFIG_CONSTRUCTORS=y
|
||||
|
||||
#
|
||||
# General setup
|
||||
|
@ -85,7 +84,12 @@ CONFIG_TIMERFD=y
|
|||
CONFIG_EVENTFD=y
|
||||
CONFIG_SHMEM=y
|
||||
CONFIG_AIO=y
|
||||
|
||||
#
|
||||
# Performance Counters
|
||||
#
|
||||
CONFIG_VM_EVENT_COUNTERS=y
|
||||
# CONFIG_STRIP_ASM_SYMS is not set
|
||||
# CONFIG_COMPAT_BRK is not set
|
||||
CONFIG_SLAB=y
|
||||
# CONFIG_SLUB is not set
|
||||
|
@ -99,6 +103,12 @@ CONFIG_KPROBES=y
|
|||
CONFIG_KRETPROBES=y
|
||||
CONFIG_HAVE_KPROBES=y
|
||||
CONFIG_HAVE_KRETPROBES=y
|
||||
CONFIG_HAVE_CLK=y
|
||||
|
||||
#
|
||||
# GCOV-based kernel profiling
|
||||
#
|
||||
# CONFIG_GCOV_KERNEL is not set
|
||||
# CONFIG_SLOW_WORK is not set
|
||||
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
|
||||
CONFIG_SLABINFO=y
|
||||
|
@ -111,7 +121,7 @@ CONFIG_MODULE_UNLOAD=y
|
|||
# CONFIG_MODVERSIONS is not set
|
||||
# CONFIG_MODULE_SRCVERSION_ALL is not set
|
||||
CONFIG_BLOCK=y
|
||||
# CONFIG_LBD is not set
|
||||
CONFIG_LBDAF=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_BLK_DEV_INTEGRITY is not set
|
||||
|
||||
|
@ -138,13 +148,14 @@ CONFIG_FREEZER=y
|
|||
# CONFIG_ARCH_VERSATILE is not set
|
||||
# CONFIG_ARCH_AT91 is not set
|
||||
# CONFIG_ARCH_CLPS711X is not set
|
||||
# CONFIG_ARCH_GEMINI is not set
|
||||
# CONFIG_ARCH_EBSA110 is not set
|
||||
# CONFIG_ARCH_EP93XX is not set
|
||||
# CONFIG_ARCH_GEMINI is not set
|
||||
# CONFIG_ARCH_FOOTBRIDGE is not set
|
||||
CONFIG_ARCH_MXC=y
|
||||
# CONFIG_ARCH_STMP3XXX is not set
|
||||
# CONFIG_ARCH_NETX is not set
|
||||
# CONFIG_ARCH_H720X is not set
|
||||
# CONFIG_ARCH_IMX is not set
|
||||
# CONFIG_ARCH_IOP13XX is not set
|
||||
# CONFIG_ARCH_IOP32X is not set
|
||||
# CONFIG_ARCH_IOP33X is not set
|
||||
|
@ -153,25 +164,25 @@ CONFIG_FREEZER=y
|
|||
# CONFIG_ARCH_IXP4XX is not set
|
||||
# CONFIG_ARCH_L7200 is not set
|
||||
# CONFIG_ARCH_KIRKWOOD is not set
|
||||
# CONFIG_ARCH_KS8695 is not set
|
||||
# CONFIG_ARCH_NS9XXX is not set
|
||||
# CONFIG_ARCH_LOKI is not set
|
||||
# CONFIG_ARCH_MV78XX0 is not set
|
||||
CONFIG_ARCH_MXC=y
|
||||
# CONFIG_ARCH_ORION5X is not set
|
||||
# CONFIG_ARCH_MMP is not set
|
||||
# CONFIG_ARCH_KS8695 is not set
|
||||
# CONFIG_ARCH_NS9XXX is not set
|
||||
# CONFIG_ARCH_W90X900 is not set
|
||||
# CONFIG_ARCH_PNX4008 is not set
|
||||
# CONFIG_ARCH_PXA is not set
|
||||
# CONFIG_ARCH_MMP is not set
|
||||
# CONFIG_ARCH_MSM is not set
|
||||
# CONFIG_ARCH_RPC is not set
|
||||
# CONFIG_ARCH_SA1100 is not set
|
||||
# CONFIG_ARCH_S3C2410 is not set
|
||||
# CONFIG_ARCH_S3C64XX is not set
|
||||
# CONFIG_ARCH_SHARK is not set
|
||||
# CONFIG_ARCH_LH7A40X is not set
|
||||
# CONFIG_ARCH_U300 is not set
|
||||
# CONFIG_ARCH_DAVINCI is not set
|
||||
# CONFIG_ARCH_OMAP is not set
|
||||
# CONFIG_ARCH_MSM is not set
|
||||
# CONFIG_ARCH_W90X900 is not set
|
||||
|
||||
#
|
||||
# Freescale MXC Implementations
|
||||
|
@ -188,6 +199,8 @@ CONFIG_MACH_MX27=y
|
|||
CONFIG_MACH_MX27ADS=y
|
||||
CONFIG_MACH_PCM038=y
|
||||
CONFIG_MACH_PCM970_BASEBOARD=y
|
||||
CONFIG_MACH_MX27_3DS=y
|
||||
CONFIG_MACH_MX27LITE=y
|
||||
CONFIG_MXC_IRQ_PRIOR=y
|
||||
CONFIG_MXC_PWM=y
|
||||
|
||||
|
@ -213,7 +226,6 @@ CONFIG_ARM_THUMB=y
|
|||
# CONFIG_CPU_DCACHE_DISABLE is not set
|
||||
# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
|
||||
# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
|
||||
# CONFIG_OUTER_CACHE is not set
|
||||
CONFIG_COMMON_CLKDEV=y
|
||||
|
||||
#
|
||||
|
@ -238,7 +250,6 @@ CONFIG_PREEMPT=y
|
|||
CONFIG_HZ=100
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_OABI_COMPAT=y
|
||||
CONFIG_ARCH_FLATMEM_HAS_HOLES=y
|
||||
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
|
||||
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
|
||||
# CONFIG_HIGHMEM is not set
|
||||
|
@ -253,10 +264,11 @@ CONFIG_SPLIT_PTLOCK_CPUS=4096
|
|||
# CONFIG_PHYS_ADDR_T_64BIT is not set
|
||||
CONFIG_ZONE_DMA_FLAG=0
|
||||
CONFIG_VIRT_TO_BUS=y
|
||||
CONFIG_UNEVICTABLE_LRU=y
|
||||
CONFIG_HAVE_MLOCK=y
|
||||
CONFIG_HAVE_MLOCKED_PAGE_BIT=y
|
||||
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
|
||||
CONFIG_ALIGNMENT_TRAP=y
|
||||
# CONFIG_UACCESS_WITH_MEMCPY is not set
|
||||
|
||||
#
|
||||
# Boot options
|
||||
|
@ -361,6 +373,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
|
|||
# CONFIG_ECONET is not set
|
||||
# CONFIG_WAN_ROUTER is not set
|
||||
# CONFIG_PHONET is not set
|
||||
# CONFIG_IEEE802154 is not set
|
||||
# CONFIG_NET_SCHED is not set
|
||||
# CONFIG_DCB is not set
|
||||
|
||||
|
@ -474,7 +487,16 @@ CONFIG_MTD_PHYSMAP=y
|
|||
# CONFIG_MTD_DOC2000 is not set
|
||||
# CONFIG_MTD_DOC2001 is not set
|
||||
# CONFIG_MTD_DOC2001PLUS is not set
|
||||
# CONFIG_MTD_NAND is not set
|
||||
CONFIG_MTD_NAND=y
|
||||
# CONFIG_MTD_NAND_VERIFY_WRITE is not set
|
||||
# CONFIG_MTD_NAND_ECC_SMC is not set
|
||||
# CONFIG_MTD_NAND_MUSEUM_IDS is not set
|
||||
# CONFIG_MTD_NAND_GPIO is not set
|
||||
CONFIG_MTD_NAND_IDS=y
|
||||
# CONFIG_MTD_NAND_DISKONCHIP is not set
|
||||
# CONFIG_MTD_NAND_NANDSIM is not set
|
||||
# CONFIG_MTD_NAND_PLATFORM is not set
|
||||
CONFIG_MTD_NAND_MXC=y
|
||||
# CONFIG_MTD_ONENAND is not set
|
||||
|
||||
#
|
||||
|
@ -485,7 +507,15 @@ CONFIG_MTD_PHYSMAP=y
|
|||
#
|
||||
# UBI - Unsorted block images
|
||||
#
|
||||
# CONFIG_MTD_UBI is not set
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_WL_THRESHOLD=4096
|
||||
CONFIG_MTD_UBI_BEB_RESERVE=1
|
||||
# CONFIG_MTD_UBI_GLUEBI is not set
|
||||
|
||||
#
|
||||
# UBI debugging options
|
||||
#
|
||||
# CONFIG_MTD_UBI_DEBUG is not set
|
||||
# CONFIG_PARPORT is not set
|
||||
CONFIG_BLK_DEV=y
|
||||
# CONFIG_BLK_DEV_COW_COMMON is not set
|
||||
|
@ -494,7 +524,21 @@ CONFIG_BLK_DEV=y
|
|||
# CONFIG_BLK_DEV_RAM is not set
|
||||
# CONFIG_CDROM_PKTCDVD is not set
|
||||
# CONFIG_ATA_OVER_ETH is not set
|
||||
# CONFIG_MISC_DEVICES is not set
|
||||
# CONFIG_MG_DISK is not set
|
||||
CONFIG_MISC_DEVICES=y
|
||||
# CONFIG_ICS932S401 is not set
|
||||
# CONFIG_ENCLOSURE_SERVICES is not set
|
||||
# CONFIG_ISL29003 is not set
|
||||
# CONFIG_C2PORT is not set
|
||||
|
||||
#
|
||||
# EEPROM support
|
||||
#
|
||||
CONFIG_EEPROM_AT24=y
|
||||
# CONFIG_EEPROM_AT25 is not set
|
||||
# CONFIG_EEPROM_LEGACY is not set
|
||||
# CONFIG_EEPROM_MAX6875 is not set
|
||||
# CONFIG_EEPROM_93CX6 is not set
|
||||
CONFIG_HAVE_IDE=y
|
||||
# CONFIG_IDE is not set
|
||||
|
||||
|
@ -508,7 +552,6 @@ CONFIG_HAVE_IDE=y
|
|||
# CONFIG_ATA is not set
|
||||
# CONFIG_MD is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_COMPAT_NET_DEV_OPS=y
|
||||
# CONFIG_DUMMY is not set
|
||||
# CONFIG_BONDING is not set
|
||||
# CONFIG_MACVLAN is not set
|
||||
|
@ -534,6 +577,8 @@ CONFIG_NET_ETHERNET=y
|
|||
# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
|
||||
# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
|
||||
# CONFIG_B44 is not set
|
||||
# CONFIG_KS8842 is not set
|
||||
# CONFIG_KS8851 is not set
|
||||
CONFIG_FEC=y
|
||||
# CONFIG_FEC2 is not set
|
||||
# CONFIG_NETDEV_1000 is not set
|
||||
|
@ -580,6 +625,11 @@ CONFIG_INPUT_EVDEV=y
|
|||
# CONFIG_INPUT_TABLET is not set
|
||||
CONFIG_INPUT_TOUCHSCREEN=y
|
||||
# CONFIG_TOUCHSCREEN_ADS7846 is not set
|
||||
# CONFIG_TOUCHSCREEN_AD7877 is not set
|
||||
# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
|
||||
# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
|
||||
# CONFIG_TOUCHSCREEN_AD7879 is not set
|
||||
# CONFIG_TOUCHSCREEN_EETI is not set
|
||||
# CONFIG_TOUCHSCREEN_FUJITSU is not set
|
||||
# CONFIG_TOUCHSCREEN_GUNZE is not set
|
||||
# CONFIG_TOUCHSCREEN_ELO is not set
|
||||
|
@ -592,6 +642,7 @@ CONFIG_INPUT_TOUCHSCREEN=y
|
|||
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
|
||||
# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
|
||||
# CONFIG_TOUCHSCREEN_TSC2007 is not set
|
||||
# CONFIG_TOUCHSCREEN_W90X900 is not set
|
||||
# CONFIG_INPUT_MISC is not set
|
||||
|
||||
#
|
||||
|
@ -644,6 +695,7 @@ CONFIG_I2C_HELPER_AUTO=y
|
|||
#
|
||||
# I2C system bus drivers (mostly embedded / system-on-chip)
|
||||
#
|
||||
# CONFIG_I2C_DESIGNWARE is not set
|
||||
# CONFIG_I2C_GPIO is not set
|
||||
CONFIG_I2C_IMX=y
|
||||
# CONFIG_I2C_OCORES is not set
|
||||
|
@ -668,7 +720,6 @@ CONFIG_I2C_IMX=y
|
|||
# CONFIG_SENSORS_PCF8574 is not set
|
||||
# CONFIG_PCF8575 is not set
|
||||
# CONFIG_SENSORS_PCA9539 is not set
|
||||
# CONFIG_SENSORS_MAX6875 is not set
|
||||
# CONFIG_SENSORS_TSL2550 is not set
|
||||
# CONFIG_I2C_DEBUG_CORE is not set
|
||||
# CONFIG_I2C_DEBUG_ALGO is not set
|
||||
|
@ -719,6 +770,7 @@ CONFIG_W1=y
|
|||
#
|
||||
# CONFIG_W1_MASTER_DS2482 is not set
|
||||
CONFIG_W1_MASTER_MXC=y
|
||||
# CONFIG_W1_MASTER_DS1WM is not set
|
||||
# CONFIG_W1_MASTER_GPIO is not set
|
||||
|
||||
#
|
||||
|
@ -753,54 +805,16 @@ CONFIG_SSB_POSSIBLE=y
|
|||
# CONFIG_TPS65010 is not set
|
||||
# CONFIG_TWL4030_CORE is not set
|
||||
# CONFIG_MFD_TMIO is not set
|
||||
# CONFIG_MFD_T7L66XB is not set
|
||||
# CONFIG_MFD_TC6387XB is not set
|
||||
# CONFIG_MFD_TC6393XB is not set
|
||||
# CONFIG_PMIC_DA903X is not set
|
||||
# CONFIG_MFD_WM8400 is not set
|
||||
# CONFIG_MFD_WM8350_I2C is not set
|
||||
# CONFIG_MFD_PCF50633 is not set
|
||||
|
||||
#
|
||||
# Multimedia devices
|
||||
#
|
||||
|
||||
#
|
||||
# Multimedia core support
|
||||
#
|
||||
CONFIG_VIDEO_DEV=y
|
||||
CONFIG_VIDEO_V4L2_COMMON=y
|
||||
CONFIG_VIDEO_ALLOW_V4L1=y
|
||||
CONFIG_VIDEO_V4L1_COMPAT=y
|
||||
# CONFIG_DVB_CORE is not set
|
||||
CONFIG_VIDEO_MEDIA=y
|
||||
|
||||
#
|
||||
# Multimedia drivers
|
||||
#
|
||||
# CONFIG_MEDIA_ATTACH is not set
|
||||
CONFIG_MEDIA_TUNER=y
|
||||
# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
|
||||
CONFIG_MEDIA_TUNER_SIMPLE=y
|
||||
CONFIG_MEDIA_TUNER_TDA8290=y
|
||||
CONFIG_MEDIA_TUNER_TDA9887=y
|
||||
CONFIG_MEDIA_TUNER_TEA5761=y
|
||||
CONFIG_MEDIA_TUNER_TEA5767=y
|
||||
CONFIG_MEDIA_TUNER_MT20XX=y
|
||||
CONFIG_MEDIA_TUNER_XC2028=y
|
||||
CONFIG_MEDIA_TUNER_XC5000=y
|
||||
CONFIG_MEDIA_TUNER_MC44S803=y
|
||||
CONFIG_VIDEO_V4L2=y
|
||||
CONFIG_VIDEO_V4L1=y
|
||||
CONFIG_VIDEO_CAPTURE_DRIVERS=y
|
||||
# CONFIG_VIDEO_ADV_DEBUG is not set
|
||||
# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
|
||||
CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
|
||||
# CONFIG_VIDEO_VIVI is not set
|
||||
# CONFIG_VIDEO_CPIA is not set
|
||||
# CONFIG_VIDEO_SAA5246A is not set
|
||||
# CONFIG_VIDEO_SAA5249 is not set
|
||||
# CONFIG_SOC_CAMERA is not set
|
||||
# CONFIG_RADIO_ADAPTERS is not set
|
||||
# CONFIG_DAB is not set
|
||||
# CONFIG_AB3100_CORE is not set
|
||||
# CONFIG_EZX_PCAP is not set
|
||||
# CONFIG_MEDIA_SUPPORT is not set
|
||||
|
||||
#
|
||||
# Graphics support
|
||||
|
@ -917,6 +931,7 @@ CONFIG_RTC_DRV_PCF8563=y
|
|||
# CONFIG_RTC_DRV_S35390A is not set
|
||||
# CONFIG_RTC_DRV_FM3130 is not set
|
||||
# CONFIG_RTC_DRV_RX8581 is not set
|
||||
# CONFIG_RTC_DRV_RX8025 is not set
|
||||
|
||||
#
|
||||
# SPI RTC drivers
|
||||
|
@ -962,12 +977,15 @@ CONFIG_RTC_DRV_PCF8563=y
|
|||
# CONFIG_REISERFS_FS is not set
|
||||
# CONFIG_JFS_FS is not set
|
||||
# CONFIG_FS_POSIX_ACL is not set
|
||||
CONFIG_FILE_LOCKING=y
|
||||
# CONFIG_XFS_FS is not set
|
||||
# CONFIG_GFS2_FS is not set
|
||||
# CONFIG_OCFS2_FS is not set
|
||||
# CONFIG_BTRFS_FS is not set
|
||||
CONFIG_FILE_LOCKING=y
|
||||
CONFIG_FSNOTIFY=y
|
||||
# CONFIG_DNOTIFY is not set
|
||||
# CONFIG_INOTIFY is not set
|
||||
CONFIG_INOTIFY_USER=y
|
||||
# CONFIG_QUOTA is not set
|
||||
# CONFIG_AUTOFS_FS is not set
|
||||
# CONFIG_AUTOFS4_FS is not set
|
||||
|
@ -1021,6 +1039,12 @@ CONFIG_JFFS2_ZLIB=y
|
|||
# CONFIG_JFFS2_LZO is not set
|
||||
CONFIG_JFFS2_RTIME=y
|
||||
# CONFIG_JFFS2_RUBIN is not set
|
||||
CONFIG_UBIFS_FS=y
|
||||
# CONFIG_UBIFS_FS_XATTR is not set
|
||||
# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
|
||||
CONFIG_UBIFS_FS_LZO=y
|
||||
CONFIG_UBIFS_FS_ZLIB=y
|
||||
# CONFIG_UBIFS_FS_DEBUG is not set
|
||||
# CONFIG_CRAMFS is not set
|
||||
# CONFIG_SQUASHFS is not set
|
||||
# CONFIG_VXFS_FS is not set
|
||||
|
@ -1119,25 +1143,11 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
|
|||
CONFIG_NOP_TRACER=y
|
||||
CONFIG_HAVE_FUNCTION_TRACER=y
|
||||
CONFIG_RING_BUFFER=y
|
||||
CONFIG_EVENT_TRACING=y
|
||||
CONFIG_CONTEXT_SWITCH_TRACER=y
|
||||
CONFIG_TRACING=y
|
||||
CONFIG_TRACING_SUPPORT=y
|
||||
|
||||
#
|
||||
# Tracers
|
||||
#
|
||||
# CONFIG_FUNCTION_TRACER is not set
|
||||
# CONFIG_IRQSOFF_TRACER is not set
|
||||
# CONFIG_PREEMPT_TRACER is not set
|
||||
# CONFIG_SCHED_TRACER is not set
|
||||
# CONFIG_CONTEXT_SWITCH_TRACER is not set
|
||||
# CONFIG_EVENT_TRACER is not set
|
||||
# CONFIG_BOOT_TRACER is not set
|
||||
# CONFIG_TRACE_BRANCH_PROFILING is not set
|
||||
# CONFIG_STACK_TRACER is not set
|
||||
# CONFIG_KMEMTRACE is not set
|
||||
# CONFIG_WORKQUEUE_TRACER is not set
|
||||
# CONFIG_BLK_DEV_IO_TRACE is not set
|
||||
# CONFIG_FTRACE_STARTUP_TEST is not set
|
||||
# CONFIG_FTRACE is not set
|
||||
# CONFIG_DYNAMIC_DEBUG is not set
|
||||
# CONFIG_SAMPLES is not set
|
||||
CONFIG_HAVE_ARCH_KGDB=y
|
||||
|
@ -1151,16 +1161,104 @@ CONFIG_ARM_UNWIND=y
|
|||
# CONFIG_SECURITY is not set
|
||||
# CONFIG_SECURITYFS is not set
|
||||
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
|
||||
# CONFIG_CRYPTO is not set
|
||||
CONFIG_CRYPTO=y
|
||||
|
||||
#
|
||||
# Crypto core or helper
|
||||
#
|
||||
# CONFIG_CRYPTO_FIPS is not set
|
||||
CONFIG_CRYPTO_ALGAPI=y
|
||||
CONFIG_CRYPTO_ALGAPI2=y
|
||||
# CONFIG_CRYPTO_MANAGER is not set
|
||||
# CONFIG_CRYPTO_MANAGER2 is not set
|
||||
# CONFIG_CRYPTO_GF128MUL is not set
|
||||
# CONFIG_CRYPTO_NULL is not set
|
||||
# CONFIG_CRYPTO_CRYPTD is not set
|
||||
# CONFIG_CRYPTO_AUTHENC is not set
|
||||
# CONFIG_CRYPTO_TEST is not set
|
||||
|
||||
#
|
||||
# Authenticated Encryption with Associated Data
|
||||
#
|
||||
# CONFIG_CRYPTO_CCM is not set
|
||||
# CONFIG_CRYPTO_GCM is not set
|
||||
# CONFIG_CRYPTO_SEQIV is not set
|
||||
|
||||
#
|
||||
# Block modes
|
||||
#
|
||||
# CONFIG_CRYPTO_CBC is not set
|
||||
# CONFIG_CRYPTO_CTR is not set
|
||||
# CONFIG_CRYPTO_CTS is not set
|
||||
# CONFIG_CRYPTO_ECB is not set
|
||||
# CONFIG_CRYPTO_LRW is not set
|
||||
# CONFIG_CRYPTO_PCBC is not set
|
||||
# CONFIG_CRYPTO_XTS is not set
|
||||
|
||||
#
|
||||
# Hash modes
|
||||
#
|
||||
# CONFIG_CRYPTO_HMAC is not set
|
||||
# CONFIG_CRYPTO_XCBC is not set
|
||||
|
||||
#
|
||||
# Digest
|
||||
#
|
||||
# CONFIG_CRYPTO_CRC32C is not set
|
||||
# CONFIG_CRYPTO_MD4 is not set
|
||||
# CONFIG_CRYPTO_MD5 is not set
|
||||
# CONFIG_CRYPTO_MICHAEL_MIC is not set
|
||||
# CONFIG_CRYPTO_RMD128 is not set
|
||||
# CONFIG_CRYPTO_RMD160 is not set
|
||||
# CONFIG_CRYPTO_RMD256 is not set
|
||||
# CONFIG_CRYPTO_RMD320 is not set
|
||||
# CONFIG_CRYPTO_SHA1 is not set
|
||||
# CONFIG_CRYPTO_SHA256 is not set
|
||||
# CONFIG_CRYPTO_SHA512 is not set
|
||||
# CONFIG_CRYPTO_TGR192 is not set
|
||||
# CONFIG_CRYPTO_WP512 is not set
|
||||
|
||||
#
|
||||
# Ciphers
|
||||
#
|
||||
# CONFIG_CRYPTO_AES is not set
|
||||
# CONFIG_CRYPTO_ANUBIS is not set
|
||||
# CONFIG_CRYPTO_ARC4 is not set
|
||||
# CONFIG_CRYPTO_BLOWFISH is not set
|
||||
# CONFIG_CRYPTO_CAMELLIA is not set
|
||||
# CONFIG_CRYPTO_CAST5 is not set
|
||||
# CONFIG_CRYPTO_CAST6 is not set
|
||||
# CONFIG_CRYPTO_DES is not set
|
||||
# CONFIG_CRYPTO_FCRYPT is not set
|
||||
# CONFIG_CRYPTO_KHAZAD is not set
|
||||
# CONFIG_CRYPTO_SALSA20 is not set
|
||||
# CONFIG_CRYPTO_SEED is not set
|
||||
# CONFIG_CRYPTO_SERPENT is not set
|
||||
# CONFIG_CRYPTO_TEA is not set
|
||||
# CONFIG_CRYPTO_TWOFISH is not set
|
||||
|
||||
#
|
||||
# Compression
|
||||
#
|
||||
CONFIG_CRYPTO_DEFLATE=y
|
||||
# CONFIG_CRYPTO_ZLIB is not set
|
||||
CONFIG_CRYPTO_LZO=y
|
||||
|
||||
#
|
||||
# Random Number Generation
|
||||
#
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
CONFIG_CRYPTO_HW=y
|
||||
CONFIG_BINARY_PRINTF=y
|
||||
|
||||
#
|
||||
# Library routines
|
||||
#
|
||||
CONFIG_BITREVERSE=y
|
||||
CONFIG_RATIONAL=y
|
||||
CONFIG_GENERIC_FIND_LAST_BIT=y
|
||||
# CONFIG_CRC_CCITT is not set
|
||||
# CONFIG_CRC16 is not set
|
||||
CONFIG_CRC16=y
|
||||
# CONFIG_CRC_T10DIF is not set
|
||||
# CONFIG_CRC_ITU_T is not set
|
||||
CONFIG_CRC32=y
|
||||
|
@ -1168,6 +1266,8 @@ CONFIG_CRC32=y
|
|||
# CONFIG_LIBCRC32C is not set
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_LZO_COMPRESS=y
|
||||
CONFIG_LZO_DECOMPRESS=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT=y
|
||||
CONFIG_HAS_DMA=y
|
||||
|
|
|
@ -1,15 +1,15 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.30-rc1
|
||||
# Wed Apr 8 11:06:37 2009
|
||||
# Linux kernel version: 2.6.31-rc4
|
||||
# Tue Jul 28 14:11:34 2009
|
||||
#
|
||||
CONFIG_ARM=y
|
||||
CONFIG_HAVE_PWM=y
|
||||
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
|
||||
CONFIG_GENERIC_GPIO=y
|
||||
CONFIG_GENERIC_TIME=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS=y
|
||||
CONFIG_MMU=y
|
||||
# CONFIG_NO_IOPORT is not set
|
||||
CONFIG_GENERIC_HARDIRQS=y
|
||||
CONFIG_STACKTRACE_SUPPORT=y
|
||||
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
|
||||
|
@ -18,14 +18,13 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
|
|||
CONFIG_HARDIRQS_SW_RESEND=y
|
||||
CONFIG_GENERIC_IRQ_PROBE=y
|
||||
CONFIG_RWSEM_GENERIC_SPINLOCK=y
|
||||
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
|
||||
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
|
||||
CONFIG_GENERIC_HWEIGHT=y
|
||||
CONFIG_GENERIC_CALIBRATE_DELAY=y
|
||||
CONFIG_ARCH_MTD_XIP=y
|
||||
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
|
||||
CONFIG_VECTORS_BASE=0xffff0000
|
||||
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
|
||||
CONFIG_CONSTRUCTORS=y
|
||||
|
||||
#
|
||||
# General setup
|
||||
|
@ -86,7 +85,12 @@ CONFIG_TIMERFD=y
|
|||
CONFIG_EVENTFD=y
|
||||
CONFIG_SHMEM=y
|
||||
CONFIG_AIO=y
|
||||
|
||||
#
|
||||
# Performance Counters
|
||||
#
|
||||
CONFIG_VM_EVENT_COUNTERS=y
|
||||
# CONFIG_STRIP_ASM_SYMS is not set
|
||||
CONFIG_COMPAT_BRK=y
|
||||
CONFIG_SLAB=y
|
||||
# CONFIG_SLUB is not set
|
||||
|
@ -97,6 +101,11 @@ CONFIG_HAVE_OPROFILE=y
|
|||
# CONFIG_KPROBES is not set
|
||||
CONFIG_HAVE_KPROBES=y
|
||||
CONFIG_HAVE_KRETPROBES=y
|
||||
CONFIG_HAVE_CLK=y
|
||||
|
||||
#
|
||||
# GCOV-based kernel profiling
|
||||
#
|
||||
# CONFIG_SLOW_WORK is not set
|
||||
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
|
||||
CONFIG_SLABINFO=y
|
||||
|
@ -109,7 +118,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y
|
|||
CONFIG_MODVERSIONS=y
|
||||
# CONFIG_MODULE_SRCVERSION_ALL is not set
|
||||
CONFIG_BLOCK=y
|
||||
# CONFIG_LBD is not set
|
||||
CONFIG_LBDAF=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_BLK_DEV_INTEGRITY is not set
|
||||
|
||||
|
@ -136,13 +145,14 @@ CONFIG_FREEZER=y
|
|||
# CONFIG_ARCH_VERSATILE is not set
|
||||
# CONFIG_ARCH_AT91 is not set
|
||||
# CONFIG_ARCH_CLPS711X is not set
|
||||
# CONFIG_ARCH_GEMINI is not set
|
||||
# CONFIG_ARCH_EBSA110 is not set
|
||||
# CONFIG_ARCH_EP93XX is not set
|
||||
# CONFIG_ARCH_GEMINI is not set
|
||||
# CONFIG_ARCH_FOOTBRIDGE is not set
|
||||
CONFIG_ARCH_MXC=y
|
||||
# CONFIG_ARCH_STMP3XXX is not set
|
||||
# CONFIG_ARCH_NETX is not set
|
||||
# CONFIG_ARCH_H720X is not set
|
||||
# CONFIG_ARCH_IMX is not set
|
||||
# CONFIG_ARCH_IOP13XX is not set
|
||||
# CONFIG_ARCH_IOP32X is not set
|
||||
# CONFIG_ARCH_IOP33X is not set
|
||||
|
@ -151,25 +161,25 @@ CONFIG_FREEZER=y
|
|||
# CONFIG_ARCH_IXP4XX is not set
|
||||
# CONFIG_ARCH_L7200 is not set
|
||||
# CONFIG_ARCH_KIRKWOOD is not set
|
||||
# CONFIG_ARCH_KS8695 is not set
|
||||
# CONFIG_ARCH_NS9XXX is not set
|
||||
# CONFIG_ARCH_LOKI is not set
|
||||
# CONFIG_ARCH_MV78XX0 is not set
|
||||
CONFIG_ARCH_MXC=y
|
||||
# CONFIG_ARCH_ORION5X is not set
|
||||
# CONFIG_ARCH_MMP is not set
|
||||
# CONFIG_ARCH_KS8695 is not set
|
||||
# CONFIG_ARCH_NS9XXX is not set
|
||||
# CONFIG_ARCH_W90X900 is not set
|
||||
# CONFIG_ARCH_PNX4008 is not set
|
||||
# CONFIG_ARCH_PXA is not set
|
||||
# CONFIG_ARCH_MMP is not set
|
||||
# CONFIG_ARCH_MSM is not set
|
||||
# CONFIG_ARCH_RPC is not set
|
||||
# CONFIG_ARCH_SA1100 is not set
|
||||
# CONFIG_ARCH_S3C2410 is not set
|
||||
# CONFIG_ARCH_S3C64XX is not set
|
||||
# CONFIG_ARCH_SHARK is not set
|
||||
# CONFIG_ARCH_LH7A40X is not set
|
||||
# CONFIG_ARCH_U300 is not set
|
||||
# CONFIG_ARCH_DAVINCI is not set
|
||||
# CONFIG_ARCH_OMAP is not set
|
||||
# CONFIG_ARCH_MSM is not set
|
||||
# CONFIG_ARCH_W90X900 is not set
|
||||
|
||||
#
|
||||
# Freescale MXC Implementations
|
||||
|
@ -178,6 +188,7 @@ CONFIG_ARCH_MXC=y
|
|||
# CONFIG_ARCH_MX2 is not set
|
||||
CONFIG_ARCH_MX3=y
|
||||
CONFIG_ARCH_MX31=y
|
||||
CONFIG_ARCH_MX35=y
|
||||
|
||||
#
|
||||
# MX3 platforms:
|
||||
|
@ -185,12 +196,19 @@ CONFIG_ARCH_MX31=y
|
|||
CONFIG_MACH_MX31ADS=y
|
||||
CONFIG_MACH_MX31ADS_WM1133_EV1=y
|
||||
CONFIG_MACH_PCM037=y
|
||||
CONFIG_MACH_PCM037_EET=y
|
||||
CONFIG_MACH_MX31LITE=y
|
||||
CONFIG_MACH_MX31_3DS=y
|
||||
CONFIG_MACH_MX31MOBOARD=y
|
||||
CONFIG_MACH_MX31LILLY=y
|
||||
CONFIG_MACH_QONG=y
|
||||
CONFIG_MACH_PCM043=y
|
||||
CONFIG_MACH_ARMADILLO5X0=y
|
||||
CONFIG_MACH_MX35_3DS=y
|
||||
CONFIG_MXC_IRQ_PRIOR=y
|
||||
CONFIG_MXC_PWM=y
|
||||
CONFIG_ARCH_HAS_RNGA=y
|
||||
CONFIG_ARCH_MXC_IOMUX_V3=y
|
||||
|
||||
#
|
||||
# Processor Type
|
||||
|
@ -218,6 +236,7 @@ CONFIG_ARM_THUMB=y
|
|||
# CONFIG_CPU_BPREDICT_DISABLE is not set
|
||||
CONFIG_OUTER_CACHE=y
|
||||
CONFIG_CACHE_L2X0=y
|
||||
# CONFIG_ARM_ERRATA_411920 is not set
|
||||
CONFIG_COMMON_CLKDEV=y
|
||||
|
||||
#
|
||||
|
@ -242,7 +261,6 @@ CONFIG_PREEMPT=y
|
|||
CONFIG_HZ=100
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_OABI_COMPAT=y
|
||||
CONFIG_ARCH_FLATMEM_HAS_HOLES=y
|
||||
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
|
||||
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
|
||||
# CONFIG_HIGHMEM is not set
|
||||
|
@ -257,10 +275,11 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
|
|||
# CONFIG_PHYS_ADDR_T_64BIT is not set
|
||||
CONFIG_ZONE_DMA_FLAG=0
|
||||
CONFIG_VIRT_TO_BUS=y
|
||||
CONFIG_UNEVICTABLE_LRU=y
|
||||
CONFIG_HAVE_MLOCK=y
|
||||
CONFIG_HAVE_MLOCKED_PAGE_BIT=y
|
||||
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
|
||||
CONFIG_ALIGNMENT_TRAP=y
|
||||
# CONFIG_UACCESS_WITH_MEMCPY is not set
|
||||
|
||||
#
|
||||
# Boot options
|
||||
|
@ -362,6 +381,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
|
|||
# CONFIG_ECONET is not set
|
||||
# CONFIG_WAN_ROUTER is not set
|
||||
# CONFIG_PHONET is not set
|
||||
# CONFIG_IEEE802154 is not set
|
||||
# CONFIG_NET_SCHED is not set
|
||||
# CONFIG_DCB is not set
|
||||
|
||||
|
@ -465,7 +485,16 @@ CONFIG_MTD_PHYSMAP=y
|
|||
# CONFIG_MTD_DOC2000 is not set
|
||||
# CONFIG_MTD_DOC2001 is not set
|
||||
# CONFIG_MTD_DOC2001PLUS is not set
|
||||
# CONFIG_MTD_NAND is not set
|
||||
CONFIG_MTD_NAND=y
|
||||
# CONFIG_MTD_NAND_VERIFY_WRITE is not set
|
||||
# CONFIG_MTD_NAND_ECC_SMC is not set
|
||||
# CONFIG_MTD_NAND_MUSEUM_IDS is not set
|
||||
# CONFIG_MTD_NAND_GPIO is not set
|
||||
CONFIG_MTD_NAND_IDS=y
|
||||
# CONFIG_MTD_NAND_DISKONCHIP is not set
|
||||
# CONFIG_MTD_NAND_NANDSIM is not set
|
||||
# CONFIG_MTD_NAND_PLATFORM is not set
|
||||
CONFIG_MTD_NAND_MXC=y
|
||||
# CONFIG_MTD_ONENAND is not set
|
||||
|
||||
#
|
||||
|
@ -476,10 +505,30 @@ CONFIG_MTD_PHYSMAP=y
|
|||
#
|
||||
# UBI - Unsorted block images
|
||||
#
|
||||
# CONFIG_MTD_UBI is not set
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_WL_THRESHOLD=4096
|
||||
CONFIG_MTD_UBI_BEB_RESERVE=1
|
||||
# CONFIG_MTD_UBI_GLUEBI is not set
|
||||
|
||||
#
|
||||
# UBI debugging options
|
||||
#
|
||||
# CONFIG_MTD_UBI_DEBUG is not set
|
||||
# CONFIG_PARPORT is not set
|
||||
# CONFIG_BLK_DEV is not set
|
||||
# CONFIG_MISC_DEVICES is not set
|
||||
CONFIG_MISC_DEVICES=y
|
||||
# CONFIG_ICS932S401 is not set
|
||||
# CONFIG_ENCLOSURE_SERVICES is not set
|
||||
# CONFIG_ISL29003 is not set
|
||||
# CONFIG_C2PORT is not set
|
||||
|
||||
#
|
||||
# EEPROM support
|
||||
#
|
||||
CONFIG_EEPROM_AT24=y
|
||||
# CONFIG_EEPROM_LEGACY is not set
|
||||
# CONFIG_EEPROM_MAX6875 is not set
|
||||
# CONFIG_EEPROM_93CX6 is not set
|
||||
CONFIG_HAVE_IDE=y
|
||||
# CONFIG_IDE is not set
|
||||
|
||||
|
@ -493,7 +542,6 @@ CONFIG_HAVE_IDE=y
|
|||
# CONFIG_ATA is not set
|
||||
# CONFIG_MD is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_COMPAT_NET_DEV_OPS=y
|
||||
# CONFIG_DUMMY is not set
|
||||
# CONFIG_BONDING is not set
|
||||
# CONFIG_MACVLAN is not set
|
||||
|
@ -528,7 +576,7 @@ CONFIG_MII=y
|
|||
# CONFIG_ETHOC is not set
|
||||
# CONFIG_SMC911X is not set
|
||||
CONFIG_SMSC911X=y
|
||||
# CONFIG_DNET is not set
|
||||
CONFIG_DNET=y
|
||||
# CONFIG_IBM_NEW_EMAC_ZMII is not set
|
||||
# CONFIG_IBM_NEW_EMAC_RGMII is not set
|
||||
# CONFIG_IBM_NEW_EMAC_TAH is not set
|
||||
|
@ -537,8 +585,10 @@ CONFIG_SMSC911X=y
|
|||
# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
|
||||
# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
|
||||
# CONFIG_B44 is not set
|
||||
CONFIG_CS89x0=y
|
||||
CONFIG_CS89x0_NONISA_IRQ=y
|
||||
# CONFIG_CS89x0 is not set
|
||||
# CONFIG_KS8842 is not set
|
||||
CONFIG_FEC=y
|
||||
# CONFIG_FEC2 is not set
|
||||
# CONFIG_NETDEV_1000 is not set
|
||||
# CONFIG_NETDEV_10000 is not set
|
||||
|
||||
|
@ -609,6 +659,7 @@ CONFIG_I2C_HELPER_AUTO=y
|
|||
#
|
||||
# I2C system bus drivers (mostly embedded / system-on-chip)
|
||||
#
|
||||
# CONFIG_I2C_DESIGNWARE is not set
|
||||
# CONFIG_I2C_GPIO is not set
|
||||
CONFIG_I2C_IMX=y
|
||||
# CONFIG_I2C_OCORES is not set
|
||||
|
@ -633,7 +684,6 @@ CONFIG_I2C_IMX=y
|
|||
# CONFIG_SENSORS_PCF8574 is not set
|
||||
# CONFIG_PCF8575 is not set
|
||||
# CONFIG_SENSORS_PCA9539 is not set
|
||||
# CONFIG_SENSORS_MAX6875 is not set
|
||||
# CONFIG_SENSORS_TSL2550 is not set
|
||||
# CONFIG_I2C_DEBUG_CORE is not set
|
||||
# CONFIG_I2C_DEBUG_ALGO is not set
|
||||
|
@ -669,6 +719,7 @@ CONFIG_W1=y
|
|||
#
|
||||
# CONFIG_W1_MASTER_DS2482 is not set
|
||||
CONFIG_W1_MASTER_MXC=y
|
||||
# CONFIG_W1_MASTER_DS1WM is not set
|
||||
# CONFIG_W1_MASTER_GPIO is not set
|
||||
|
||||
#
|
||||
|
@ -703,6 +754,8 @@ CONFIG_SSB_POSSIBLE=y
|
|||
# CONFIG_TPS65010 is not set
|
||||
# CONFIG_TWL4030_CORE is not set
|
||||
# CONFIG_MFD_TMIO is not set
|
||||
# CONFIG_MFD_T7L66XB is not set
|
||||
# CONFIG_MFD_TC6387XB is not set
|
||||
# CONFIG_MFD_TC6393XB is not set
|
||||
# CONFIG_PMIC_DA903X is not set
|
||||
# CONFIG_MFD_WM8400 is not set
|
||||
|
@ -711,10 +764,8 @@ CONFIG_MFD_WM8350_CONFIG_MODE_0=y
|
|||
CONFIG_MFD_WM8352_CONFIG_MODE_0=y
|
||||
CONFIG_MFD_WM8350_I2C=y
|
||||
# CONFIG_MFD_PCF50633 is not set
|
||||
|
||||
#
|
||||
# Multimedia devices
|
||||
#
|
||||
# CONFIG_AB3100_CORE is not set
|
||||
CONFIG_MEDIA_SUPPORT=y
|
||||
|
||||
#
|
||||
# Multimedia core support
|
||||
|
@ -758,8 +809,10 @@ CONFIG_SOC_CAMERA_MT9T031=y
|
|||
CONFIG_SOC_CAMERA_MT9V022=y
|
||||
CONFIG_SOC_CAMERA_TW9910=y
|
||||
# CONFIG_SOC_CAMERA_PLATFORM is not set
|
||||
# CONFIG_SOC_CAMERA_OV772X is not set
|
||||
CONFIG_SOC_CAMERA_OV772X=y
|
||||
CONFIG_MX3_VIDEO=y
|
||||
CONFIG_VIDEO_MX3=y
|
||||
# CONFIG_VIDEO_SH_MOBILE_CEU is not set
|
||||
# CONFIG_RADIO_ADAPTERS is not set
|
||||
# CONFIG_DAB is not set
|
||||
|
||||
|
@ -847,8 +900,11 @@ CONFIG_REGULATOR=y
|
|||
# CONFIG_REGULATOR_DEBUG is not set
|
||||
# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
|
||||
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
|
||||
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
|
||||
# CONFIG_REGULATOR_BQ24022 is not set
|
||||
# CONFIG_REGULATOR_MAX1586 is not set
|
||||
CONFIG_REGULATOR_WM8350=y
|
||||
# CONFIG_REGULATOR_LP3971 is not set
|
||||
# CONFIG_UIO is not set
|
||||
# CONFIG_STAGING is not set
|
||||
|
||||
|
@ -861,10 +917,12 @@ CONFIG_REGULATOR_WM8350=y
|
|||
# CONFIG_REISERFS_FS is not set
|
||||
# CONFIG_JFS_FS is not set
|
||||
# CONFIG_FS_POSIX_ACL is not set
|
||||
CONFIG_FILE_LOCKING=y
|
||||
# CONFIG_XFS_FS is not set
|
||||
# CONFIG_GFS2_FS is not set
|
||||
# CONFIG_OCFS2_FS is not set
|
||||
# CONFIG_BTRFS_FS is not set
|
||||
CONFIG_FILE_LOCKING=y
|
||||
CONFIG_FSNOTIFY=y
|
||||
# CONFIG_DNOTIFY is not set
|
||||
CONFIG_INOTIFY=y
|
||||
CONFIG_INOTIFY_USER=y
|
||||
|
@ -921,6 +979,12 @@ CONFIG_JFFS2_ZLIB=y
|
|||
# CONFIG_JFFS2_LZO is not set
|
||||
CONFIG_JFFS2_RTIME=y
|
||||
# CONFIG_JFFS2_RUBIN is not set
|
||||
CONFIG_UBIFS_FS=y
|
||||
# CONFIG_UBIFS_FS_XATTR is not set
|
||||
# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
|
||||
CONFIG_UBIFS_FS_LZO=y
|
||||
CONFIG_UBIFS_FS_ZLIB=y
|
||||
# CONFIG_UBIFS_FS_DEBUG is not set
|
||||
# CONFIG_CRAMFS is not set
|
||||
# CONFIG_SQUASHFS is not set
|
||||
# CONFIG_VXFS_FS is not set
|
||||
|
@ -937,6 +1001,7 @@ CONFIG_NFS_FS=y
|
|||
CONFIG_NFS_V3=y
|
||||
# CONFIG_NFS_V3_ACL is not set
|
||||
CONFIG_NFS_V4=y
|
||||
# CONFIG_NFS_V4_1 is not set
|
||||
CONFIG_ROOT_NFS=y
|
||||
# CONFIG_NFSD is not set
|
||||
CONFIG_LOCKD=y
|
||||
|
@ -979,22 +1044,7 @@ CONFIG_FRAME_WARN=1024
|
|||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
CONFIG_HAVE_FUNCTION_TRACER=y
|
||||
CONFIG_TRACING_SUPPORT=y
|
||||
|
||||
#
|
||||
# Tracers
|
||||
#
|
||||
# CONFIG_FUNCTION_TRACER is not set
|
||||
# CONFIG_IRQSOFF_TRACER is not set
|
||||
# CONFIG_PREEMPT_TRACER is not set
|
||||
# CONFIG_SCHED_TRACER is not set
|
||||
# CONFIG_CONTEXT_SWITCH_TRACER is not set
|
||||
# CONFIG_EVENT_TRACER is not set
|
||||
# CONFIG_BOOT_TRACER is not set
|
||||
# CONFIG_TRACE_BRANCH_PROFILING is not set
|
||||
# CONFIG_STACK_TRACER is not set
|
||||
# CONFIG_KMEMTRACE is not set
|
||||
# CONFIG_WORKQUEUE_TRACER is not set
|
||||
# CONFIG_BLK_DEV_IO_TRACE is not set
|
||||
# CONFIG_FTRACE is not set
|
||||
# CONFIG_SAMPLES is not set
|
||||
CONFIG_HAVE_ARCH_KGDB=y
|
||||
CONFIG_ARM_UNWIND=y
|
||||
|
@ -1094,9 +1144,9 @@ CONFIG_CRYPTO_DES=y
|
|||
#
|
||||
# Compression
|
||||
#
|
||||
# CONFIG_CRYPTO_DEFLATE is not set
|
||||
CONFIG_CRYPTO_DEFLATE=y
|
||||
# CONFIG_CRYPTO_ZLIB is not set
|
||||
# CONFIG_CRYPTO_LZO is not set
|
||||
CONFIG_CRYPTO_LZO=y
|
||||
|
||||
#
|
||||
# Random Number Generation
|
||||
|
@ -1109,9 +1159,10 @@ CONFIG_CRYPTO_HW=y
|
|||
# Library routines
|
||||
#
|
||||
CONFIG_BITREVERSE=y
|
||||
CONFIG_RATIONAL=y
|
||||
CONFIG_GENERIC_FIND_LAST_BIT=y
|
||||
# CONFIG_CRC_CCITT is not set
|
||||
# CONFIG_CRC16 is not set
|
||||
CONFIG_CRC16=y
|
||||
# CONFIG_CRC_T10DIF is not set
|
||||
# CONFIG_CRC_ITU_T is not set
|
||||
CONFIG_CRC32=y
|
||||
|
@ -1119,6 +1170,8 @@ CONFIG_CRC32=y
|
|||
# CONFIG_LIBCRC32C is not set
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_LZO_COMPRESS=y
|
||||
CONFIG_LZO_DECOMPRESS=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT=y
|
||||
CONFIG_HAS_DMA=y
|
||||
|
|
|
@ -1107,7 +1107,7 @@ CONFIG_USB_ZERO=m
|
|||
CONFIG_USB_OTG_UTILS=y
|
||||
# CONFIG_USB_GPIO_VBUS is not set
|
||||
# CONFIG_ISP1301_OMAP is not set
|
||||
CONFIG_TWL4030_USB=y
|
||||
# CONFIG_TWL4030_USB is not set
|
||||
# CONFIG_NOP_USB_XCEIV is not set
|
||||
CONFIG_MMC=y
|
||||
# CONFIG_MMC_DEBUG is not set
|
||||
|
|
|
@ -282,7 +282,7 @@ CONFIG_ALIGNMENT_TRAP=y
|
|||
#
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_CMDLINE="init=/sbin/preinit ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs rootflags=bulk_read,no_chk_data_crc rw console=ttyMTD,log console=tty0"
|
||||
CONFIG_CMDLINE="init=/sbin/preinit ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs rootflags=bulk_read,no_chk_data_crc rw console=ttyMTD,log console=tty0 console=ttyS2,115200n8"
|
||||
# CONFIG_XIP_KERNEL is not set
|
||||
# CONFIG_KEXEC is not set
|
||||
|
||||
|
@ -1354,7 +1354,7 @@ CONFIG_USB_OTG_UTILS=y
|
|||
# CONFIG_USB_GPIO_VBUS is not set
|
||||
# CONFIG_ISP1301_OMAP is not set
|
||||
CONFIG_TWL4030_USB=y
|
||||
CONFIG_MMC=m
|
||||
CONFIG_MMC=y
|
||||
# CONFIG_MMC_DEBUG is not set
|
||||
# CONFIG_MMC_UNSAFE_RESUME is not set
|
||||
|
||||
|
@ -1449,7 +1449,8 @@ CONFIG_RTC_DRV_TWL4030=m
|
|||
# on-CPU RTC drivers
|
||||
#
|
||||
# CONFIG_DMADEVICES is not set
|
||||
# CONFIG_REGULATOR is not set
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_TWL4030=y
|
||||
# CONFIG_UIO is not set
|
||||
# CONFIG_STAGING is not set
|
||||
|
||||
|
|
|
@ -159,8 +159,6 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
|
|||
|
||||
#else /* ARM_ARCH_6 */
|
||||
|
||||
#include <asm/system.h>
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
#error SMP not supported on pre-ARMv6 CPUs
|
||||
#endif
|
||||
|
|
|
@ -201,7 +201,8 @@ static struct tagtable __tagtable_##fn __tag = { tag, fn }
|
|||
struct membank {
|
||||
unsigned long start;
|
||||
unsigned long size;
|
||||
int node;
|
||||
unsigned short node;
|
||||
unsigned short highmem;
|
||||
};
|
||||
|
||||
struct meminfo {
|
||||
|
|
|
@ -148,7 +148,7 @@ trace:
|
|||
sub r0, r0, #MCOUNT_INSN_SIZE
|
||||
mov lr, pc
|
||||
mov pc, r2
|
||||
mov lr, r1 @ restore lr
|
||||
ldr lr, [fp, #-4] @ restore lr
|
||||
ldmia sp!, {r0-r3, pc}
|
||||
|
||||
#endif /* CONFIG_DYNAMIC_FTRACE */
|
||||
|
|
|
@ -133,7 +133,7 @@ sys_sigaction(int sig, const struct old_sigaction __user *act,
|
|||
}
|
||||
|
||||
#ifdef CONFIG_CRUNCH
|
||||
static int preserve_crunch_context(struct crunch_sigframe *frame)
|
||||
static int preserve_crunch_context(struct crunch_sigframe __user *frame)
|
||||
{
|
||||
char kbuf[sizeof(*frame) + 8];
|
||||
struct crunch_sigframe *kframe;
|
||||
|
@ -146,7 +146,7 @@ static int preserve_crunch_context(struct crunch_sigframe *frame)
|
|||
return __copy_to_user(frame, kframe, sizeof(*frame));
|
||||
}
|
||||
|
||||
static int restore_crunch_context(struct crunch_sigframe *frame)
|
||||
static int restore_crunch_context(struct crunch_sigframe __user *frame)
|
||||
{
|
||||
char kbuf[sizeof(*frame) + 8];
|
||||
struct crunch_sigframe *kframe;
|
||||
|
|
|
@ -37,7 +37,6 @@
|
|||
#include <mach/serial.h>
|
||||
#include <mach/nand.h>
|
||||
#include <mach/mmc.h>
|
||||
#include <mach/common.h>
|
||||
|
||||
#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000
|
||||
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
|
||||
|
|
|
@ -36,7 +36,6 @@
|
|||
#include <mach/serial.h>
|
||||
#include <mach/nand.h>
|
||||
#include <mach/mmc.h>
|
||||
#include <mach/common.h>
|
||||
|
||||
#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000
|
||||
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
|
||||
|
|
|
@ -45,7 +45,6 @@
|
|||
#include <mach/nand.h>
|
||||
#include <mach/mmc.h>
|
||||
#include <mach/emac.h>
|
||||
#include <mach/common.h>
|
||||
|
||||
#define DM644X_EVM_PHY_MASK (0x2)
|
||||
#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
|
||||
|
|
|
@ -47,7 +47,6 @@
|
|||
#include <mach/i2c.h>
|
||||
#include <mach/mmc.h>
|
||||
#include <mach/emac.h>
|
||||
#include <mach/common.h>
|
||||
|
||||
#define DM646X_EVM_PHY_MASK (0x2)
|
||||
#define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
|
||||
|
|
|
@ -52,7 +52,6 @@
|
|||
#include <mach/serial.h>
|
||||
#include <mach/psc.h>
|
||||
#include <mach/mux.h>
|
||||
#include <mach/common.h>
|
||||
|
||||
#define SFFSDR_PHY_MASK (0x2)
|
||||
#define SFFSDR_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
|
||||
|
|
|
@ -41,9 +41,6 @@
|
|||
#define TS72XX_OPTIONS2_TS9420_BOOT 0x02
|
||||
|
||||
|
||||
#define TS72XX_NOR_PHYS_BASE 0x60000000
|
||||
#define TS72XX_NOR2_PHYS_BASE 0x62000000
|
||||
|
||||
#define TS72XX_NAND1_DATA_PHYS_BASE 0x60000000
|
||||
#define TS72XX_NAND2_DATA_PHYS_BASE 0x70000000
|
||||
#define TS72XX_NAND_DATA_VIRT_BASE 0xfebfc000
|
||||
|
|
|
@ -112,13 +112,16 @@ static void __init ts72xx_map_io(void)
|
|||
}
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* NOR flash (TS-7200 only)
|
||||
*************************************************************************/
|
||||
static struct physmap_flash_data ts72xx_flash_data = {
|
||||
.width = 1,
|
||||
.width = 2,
|
||||
};
|
||||
|
||||
static struct resource ts72xx_flash_resource = {
|
||||
.start = TS72XX_NOR_PHYS_BASE,
|
||||
.end = TS72XX_NOR_PHYS_BASE + SZ_16M - 1,
|
||||
.start = EP93XX_CS6_PHYS_BASE,
|
||||
.end = EP93XX_CS6_PHYS_BASE + SZ_16M - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
|
||||
|
@ -132,6 +135,12 @@ static struct platform_device ts72xx_flash = {
|
|||
.resource = &ts72xx_flash_resource,
|
||||
};
|
||||
|
||||
static void __init ts72xx_register_flash(void)
|
||||
{
|
||||
if (board_is_ts7200())
|
||||
platform_device_register(&ts72xx_flash);
|
||||
}
|
||||
|
||||
static unsigned char ts72xx_rtc_readbyte(unsigned long addr)
|
||||
{
|
||||
__raw_writeb(addr, TS72XX_RTC_INDEX_VIRT_BASE);
|
||||
|
@ -165,8 +174,7 @@ static struct ep93xx_eth_data ts72xx_eth_data = {
|
|||
static void __init ts72xx_init_machine(void)
|
||||
{
|
||||
ep93xx_init_devices();
|
||||
if (board_is_ts7200())
|
||||
platform_device_register(&ts72xx_flash);
|
||||
ts72xx_register_flash();
|
||||
platform_device_register(&ts72xx_rtc_device);
|
||||
|
||||
ep93xx_register_eth(&ts72xx_eth_data, 1);
|
||||
|
|
|
@ -17,7 +17,7 @@
|
|||
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffff0000
|
||||
#define IO_SPACE_LIMIT 0x0000ffff
|
||||
|
||||
extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
|
||||
extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
|
||||
|
|
|
@ -206,6 +206,15 @@ static void __init qnap_ts219_init(void)
|
|||
|
||||
}
|
||||
|
||||
static int __init ts219_pci_init(void)
|
||||
{
|
||||
if (machine_is_ts219())
|
||||
kirkwood_pcie_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
subsys_initcall(ts219_pci_init);
|
||||
|
||||
MACHINE_START(TS219, "QNAP TS-119/TS-219")
|
||||
/* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
|
||||
.phys_io = KIRKWOOD_REGS_PHYS_BASE,
|
||||
|
|
|
@ -16,6 +16,11 @@
|
|||
|
||||
#include <asm/sizes.h>
|
||||
|
||||
/*
|
||||
* Clocks are derived from MCLK, which is 25Mhz
|
||||
*/
|
||||
#define KS8695_CLOCK_RATE 25000000
|
||||
|
||||
/*
|
||||
* Physical RAM address.
|
||||
*/
|
||||
|
|
|
@ -14,7 +14,8 @@
|
|||
#ifndef __ASM_ARCH_TIMEX_H
|
||||
#define __ASM_ARCH_TIMEX_H
|
||||
|
||||
/* timers are derived from MCLK, which is 25MHz */
|
||||
#define CLOCK_TICK_RATE 25000000
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#define CLOCK_TICK_RATE KS8695_CLOCK_RATE
|
||||
|
||||
#endif
|
||||
|
|
|
@ -245,6 +245,9 @@ static int ks8695_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs
|
|||
|
||||
static void __init ks8695_pci_preinit(void)
|
||||
{
|
||||
/* make software reset to avoid freeze if PCI bus was messed up */
|
||||
__raw_writel(0x80000000, KS8695_PCI_VA + KS8695_PBCS);
|
||||
|
||||
/* stage 1 initialization, subid, subdevice = 0x0001 */
|
||||
__raw_writel(0x00010001, KS8695_PCI_VA + KS8695_CRCSID);
|
||||
|
||||
|
|
|
@ -63,7 +63,7 @@ static struct imxuart_platform_data uart_pdata = {
|
|||
|
||||
static int devboard_sdhc2_get_ro(struct device *dev)
|
||||
{
|
||||
return gpio_get_value(SDHC2_WP);
|
||||
return !gpio_get_value(SDHC2_WP);
|
||||
}
|
||||
|
||||
static int devboard_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
|
||||
|
|
|
@ -67,7 +67,7 @@ static unsigned int marxbot_pins[] = {
|
|||
|
||||
static int marxbot_sdhc2_get_ro(struct device *dev)
|
||||
{
|
||||
return gpio_get_value(SDHC2_WP);
|
||||
return !gpio_get_value(SDHC2_WP);
|
||||
}
|
||||
|
||||
static int marxbot_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
|
||||
|
|
|
@ -94,7 +94,7 @@ static struct imxi2c_platform_data moboard_i2c1_pdata = {
|
|||
|
||||
static int moboard_sdhc1_get_ro(struct device *dev)
|
||||
{
|
||||
return gpio_get_value(SDHC1_WP);
|
||||
return !gpio_get_value(SDHC1_WP);
|
||||
}
|
||||
|
||||
static int moboard_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
|
||||
|
|
|
@ -24,15 +24,6 @@
|
|||
#include "devices.h"
|
||||
|
||||
static unsigned int pcm037_eet_pins[] = {
|
||||
/* SPI #1 */
|
||||
MX31_PIN_CSPI1_MISO__MISO,
|
||||
MX31_PIN_CSPI1_MOSI__MOSI,
|
||||
MX31_PIN_CSPI1_SCLK__SCLK,
|
||||
MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
|
||||
MX31_PIN_CSPI1_SS0__SS0,
|
||||
MX31_PIN_CSPI1_SS1__SS1,
|
||||
MX31_PIN_CSPI1_SS2__SS2,
|
||||
|
||||
/* Reserve and hardwire GPIO 57 high - S6E63D6 chipselect */
|
||||
IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_GPIO),
|
||||
/* GPIO keys */
|
||||
|
|
|
@ -19,7 +19,6 @@
|
|||
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/dma.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/mux.h>
|
||||
#include <mach/cpu.h>
|
||||
#include <mach/mcbsp.h>
|
||||
|
|
|
@ -141,7 +141,7 @@ static inline void board_smc91x_init(void)
|
|||
|
||||
static void __init omap_2430sdp_init_irq(void)
|
||||
{
|
||||
omap2_init_common_hw(NULL);
|
||||
omap2_init_common_hw(NULL, NULL);
|
||||
omap_init_irq();
|
||||
omap_gpio_init();
|
||||
}
|
||||
|
|
|
@ -169,7 +169,7 @@ static struct platform_device *sdp3430_devices[] __initdata = {
|
|||
|
||||
static void __init omap_3430sdp_init_irq(void)
|
||||
{
|
||||
omap2_init_common_hw(hyb18m512160af6_sdrc_params);
|
||||
omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL);
|
||||
omap_init_irq();
|
||||
omap_gpio_init();
|
||||
}
|
||||
|
|
|
@ -59,7 +59,7 @@ static void __init gic_init_irq(void)
|
|||
|
||||
static void __init omap_4430sdp_init_irq(void)
|
||||
{
|
||||
omap2_init_common_hw(NULL);
|
||||
omap2_init_common_hw(NULL, NULL);
|
||||
#ifdef CONFIG_OMAP_32K_TIMER
|
||||
omap2_gp_clockevent_set_gptimer(1);
|
||||
#endif
|
||||
|
|
|
@ -250,7 +250,7 @@ out:
|
|||
|
||||
static void __init omap_apollon_init_irq(void)
|
||||
{
|
||||
omap2_init_common_hw(NULL);
|
||||
omap2_init_common_hw(NULL, NULL);
|
||||
omap_init_irq();
|
||||
omap_gpio_init();
|
||||
apollon_init_smc91x();
|
||||
|
|
|
@ -33,7 +33,7 @@
|
|||
|
||||
static void __init omap_generic_init_irq(void)
|
||||
{
|
||||
omap2_init_common_hw(NULL);
|
||||
omap2_init_common_hw(NULL, NULL);
|
||||
omap_init_irq();
|
||||
}
|
||||
|
||||
|
|
|
@ -270,7 +270,7 @@ static void __init h4_init_flash(void)
|
|||
|
||||
static void __init omap_h4_init_irq(void)
|
||||
{
|
||||
omap2_init_common_hw(NULL);
|
||||
omap2_init_common_hw(NULL, NULL);
|
||||
omap_init_irq();
|
||||
omap_gpio_init();
|
||||
h4_init_flash();
|
||||
|
|
|
@ -270,7 +270,7 @@ static inline void __init ldp_init_smsc911x(void)
|
|||
|
||||
static void __init omap_ldp_init_irq(void)
|
||||
{
|
||||
omap2_init_common_hw(NULL);
|
||||
omap2_init_common_hw(NULL, NULL);
|
||||
omap_init_irq();
|
||||
omap_gpio_init();
|
||||
ldp_init_smsc911x();
|
||||
|
|
|
@ -282,7 +282,8 @@ static int __init omap3_beagle_i2c_init(void)
|
|||
|
||||
static void __init omap3_beagle_init_irq(void)
|
||||
{
|
||||
omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
|
||||
omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
|
||||
mt46h32m32lf6_sdrc_params);
|
||||
omap_init_irq();
|
||||
#ifdef CONFIG_OMAP_32K_TIMER
|
||||
omap2_gp_clockevent_set_gptimer(12);
|
||||
|
@ -408,6 +409,10 @@ static void __init omap3_beagle_init(void)
|
|||
|
||||
usb_musb_init();
|
||||
omap3beagle_flash_init();
|
||||
|
||||
/* Ensure SDRC pins are mux'd for self-refresh */
|
||||
omap_cfg_reg(H16_34XX_SDRC_CKE0);
|
||||
omap_cfg_reg(H17_34XX_SDRC_CKE1);
|
||||
}
|
||||
|
||||
static void __init omap3_beagle_map_io(void)
|
||||
|
|
|
@ -25,6 +25,7 @@
|
|||
#include <linux/spi/spi.h>
|
||||
#include <linux/spi/ads7846.h>
|
||||
#include <linux/i2c/twl4030.h>
|
||||
#include <linux/usb/otg.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
@ -279,7 +280,7 @@ struct spi_board_info omap3evm_spi_board_info[] = {
|
|||
|
||||
static void __init omap3_evm_init_irq(void)
|
||||
{
|
||||
omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
|
||||
omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL);
|
||||
omap_init_irq();
|
||||
omap_gpio_init();
|
||||
omap3evm_init_smc911x();
|
||||
|
@ -307,6 +308,10 @@ static void __init omap3_evm_init(void)
|
|||
ARRAY_SIZE(omap3evm_spi_board_info));
|
||||
|
||||
omap_serial_init();
|
||||
#ifdef CONFIG_NOP_USB_XCEIV
|
||||
/* OMAP3EVM uses ISP1504 phy and so register nop transceiver */
|
||||
usb_nop_xceiv_register();
|
||||
#endif
|
||||
usb_musb_init();
|
||||
ads7846_dev_init();
|
||||
}
|
||||
|
|
|
@ -40,6 +40,7 @@
|
|||
#include <mach/mcspi.h>
|
||||
#include <mach/usb.h>
|
||||
#include <mach/keypad.h>
|
||||
#include <mach/mux.h>
|
||||
|
||||
#include "sdram-micron-mt46h32m32lf-6.h"
|
||||
#include "mmc-twl4030.h"
|
||||
|
@ -310,7 +311,8 @@ static int __init omap3pandora_i2c_init(void)
|
|||
|
||||
static void __init omap3pandora_init_irq(void)
|
||||
{
|
||||
omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
|
||||
omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
|
||||
mt46h32m32lf6_sdrc_params);
|
||||
omap_init_irq();
|
||||
omap_gpio_init();
|
||||
}
|
||||
|
@ -397,6 +399,10 @@ static void __init omap3pandora_init(void)
|
|||
omap3pandora_ads7846_init();
|
||||
pandora_keys_gpio_init();
|
||||
usb_musb_init();
|
||||
|
||||
/* Ensure SDRC pins are mux'd for self-refresh */
|
||||
omap_cfg_reg(H16_34XX_SDRC_CKE0);
|
||||
omap_cfg_reg(H17_34XX_SDRC_CKE1);
|
||||
}
|
||||
|
||||
static void __init omap3pandora_map_io(void)
|
||||
|
|
|
@ -44,6 +44,7 @@
|
|||
#include <mach/gpmc.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/nand.h>
|
||||
#include <mach/mux.h>
|
||||
#include <mach/usb.h>
|
||||
|
||||
#include "sdram-micron-mt46h32m32lf-6.h"
|
||||
|
@ -51,6 +52,7 @@
|
|||
|
||||
#define OVERO_GPIO_BT_XGATE 15
|
||||
#define OVERO_GPIO_W2W_NRESET 16
|
||||
#define OVERO_GPIO_PENDOWN 114
|
||||
#define OVERO_GPIO_BT_NRESET 164
|
||||
#define OVERO_GPIO_USBH_CPEN 168
|
||||
#define OVERO_GPIO_USBH_NRESET 183
|
||||
|
@ -146,7 +148,7 @@ static struct platform_device overo_smsc911x_device = {
|
|||
.name = "smsc911x",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(overo_smsc911x_resources),
|
||||
.resource = &overo_smsc911x_resources,
|
||||
.resource = overo_smsc911x_resources,
|
||||
.dev = {
|
||||
.platform_data = &overo_smsc911x_config,
|
||||
},
|
||||
|
@ -360,7 +362,8 @@ static int __init overo_i2c_init(void)
|
|||
|
||||
static void __init overo_init_irq(void)
|
||||
{
|
||||
omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
|
||||
omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
|
||||
mt46h32m32lf6_sdrc_params);
|
||||
omap_init_irq();
|
||||
omap_gpio_init();
|
||||
}
|
||||
|
@ -395,6 +398,10 @@ static void __init overo_init(void)
|
|||
overo_ads7846_init();
|
||||
overo_init_smsc911x();
|
||||
|
||||
/* Ensure SDRC pins are mux'd for self-refresh */
|
||||
omap_cfg_reg(H16_34XX_SDRC_CKE0);
|
||||
omap_cfg_reg(H17_34XX_SDRC_CKE1);
|
||||
|
||||
if ((gpio_request(OVERO_GPIO_W2W_NRESET,
|
||||
"OVERO_GPIO_W2W_NRESET") == 0) &&
|
||||
(gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) == 0)) {
|
||||
|
|
|
@ -278,6 +278,10 @@ static struct twl4030_gpio_platform_data rx51_gpio_data = {
|
|||
.setup = rx51_twlgpio_setup,
|
||||
};
|
||||
|
||||
static struct twl4030_usb_data rx51_usb_data = {
|
||||
.usb_mode = T2_USB_MODE_ULPI,
|
||||
};
|
||||
|
||||
static struct twl4030_platform_data rx51_twldata = {
|
||||
.irq_base = TWL4030_IRQ_BASE,
|
||||
.irq_end = TWL4030_IRQ_END,
|
||||
|
@ -286,6 +290,7 @@ static struct twl4030_platform_data rx51_twldata = {
|
|||
.gpio = &rx51_gpio_data,
|
||||
.keypad = &rx51_kp_data,
|
||||
.madc = &rx51_madc_data,
|
||||
.usb = &rx51_usb_data,
|
||||
|
||||
.vaux1 = &rx51_vaux1,
|
||||
.vaux2 = &rx51_vaux2,
|
||||
|
|
|
@ -61,7 +61,7 @@ static struct omap_board_config_kernel rx51_config[] = {
|
|||
|
||||
static void __init rx51_init_irq(void)
|
||||
{
|
||||
omap2_init_common_hw(NULL);
|
||||
omap2_init_common_hw(NULL, NULL);
|
||||
omap_init_irq();
|
||||
omap_gpio_init();
|
||||
}
|
||||
|
@ -75,6 +75,10 @@ static void __init rx51_init(void)
|
|||
omap_serial_init();
|
||||
usb_musb_init();
|
||||
rx51_peripherals_init();
|
||||
|
||||
/* Ensure SDRC pins are mux'd for self-refresh */
|
||||
omap_cfg_reg(H16_34XX_SDRC_CKE0);
|
||||
omap_cfg_reg(H17_34XX_SDRC_CKE1);
|
||||
}
|
||||
|
||||
static void __init rx51_map_io(void)
|
||||
|
|
|
@ -25,7 +25,7 @@
|
|||
|
||||
static void __init omap_zoom2_init_irq(void)
|
||||
{
|
||||
omap2_init_common_hw(NULL);
|
||||
omap2_init_common_hw(NULL, NULL);
|
||||
omap_init_irq();
|
||||
omap_gpio_init();
|
||||
}
|
||||
|
|
|
@ -27,6 +27,7 @@
|
|||
#include <mach/clock.h>
|
||||
#include <mach/clockdomain.h>
|
||||
#include <mach/cpu.h>
|
||||
#include <mach/prcm.h>
|
||||
#include <asm/div64.h>
|
||||
|
||||
#include <mach/sdrc.h>
|
||||
|
@ -38,8 +39,6 @@
|
|||
#include "cm-regbits-24xx.h"
|
||||
#include "cm-regbits-34xx.h"
|
||||
|
||||
#define MAX_CLOCK_ENABLE_WAIT 100000
|
||||
|
||||
/* DPLL rate rounding: minimum DPLL multiplier, divider values */
|
||||
#define DPLL_MIN_MULTIPLIER 1
|
||||
#define DPLL_MIN_DIVIDER 1
|
||||
|
@ -274,83 +273,97 @@ unsigned long omap2_fixed_divisor_recalc(struct clk *clk)
|
|||
}
|
||||
|
||||
/**
|
||||
* omap2_wait_clock_ready - wait for clock to enable
|
||||
* @reg: physical address of clock IDLEST register
|
||||
* @mask: value to mask against to determine if the clock is active
|
||||
* @name: name of the clock (for printk)
|
||||
* omap2_clk_dflt_find_companion - find companion clock to @clk
|
||||
* @clk: struct clk * to find the companion clock of
|
||||
* @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
|
||||
* @other_bit: u8 ** to return the companion clock bit shift in
|
||||
*
|
||||
* Returns 1 if the clock enabled in time, or 0 if it failed to enable
|
||||
* in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
|
||||
*/
|
||||
int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
|
||||
{
|
||||
int i = 0;
|
||||
int ena = 0;
|
||||
|
||||
/*
|
||||
* 24xx uses 0 to indicate not ready, and 1 to indicate ready.
|
||||
* 34xx reverses this, just to keep us on our toes
|
||||
*/
|
||||
if (cpu_mask & (RATE_IN_242X | RATE_IN_243X))
|
||||
ena = mask;
|
||||
else if (cpu_mask & RATE_IN_343X)
|
||||
ena = 0;
|
||||
|
||||
/* Wait for lock */
|
||||
while (((__raw_readl(reg) & mask) != ena) &&
|
||||
(i++ < MAX_CLOCK_ENABLE_WAIT)) {
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
if (i <= MAX_CLOCK_ENABLE_WAIT)
|
||||
pr_debug("Clock %s stable after %d loops\n", name, i);
|
||||
else
|
||||
printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
|
||||
name, MAX_CLOCK_ENABLE_WAIT);
|
||||
|
||||
|
||||
return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Note: We don't need special code here for INVERT_ENABLE
|
||||
* for the time being since INVERT_ENABLE only applies to clocks enabled by
|
||||
* Note: We don't need special code here for INVERT_ENABLE for the
|
||||
* time being since INVERT_ENABLE only applies to clocks enabled by
|
||||
* CM_CLKEN_PLL
|
||||
*
|
||||
* Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's
|
||||
* just a matter of XORing the bits.
|
||||
*
|
||||
* Some clocks don't have companion clocks. For example, modules with
|
||||
* only an interface clock (such as MAILBOXES) don't have a companion
|
||||
* clock. Right now, this code relies on the hardware exporting a bit
|
||||
* in the correct companion register that indicates that the
|
||||
* nonexistent 'companion clock' is active. Future patches will
|
||||
* associate this type of code with per-module data structures to
|
||||
* avoid this issue, and remove the casts. No return value.
|
||||
*/
|
||||
static void omap2_clk_wait_ready(struct clk *clk)
|
||||
void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
|
||||
u8 *other_bit)
|
||||
{
|
||||
void __iomem *reg, *other_reg, *st_reg;
|
||||
u32 bit;
|
||||
|
||||
/*
|
||||
* REVISIT: This code is pretty ugly. It would be nice to generalize
|
||||
* it and pull it into struct clk itself somehow.
|
||||
*/
|
||||
reg = clk->enable_reg;
|
||||
u32 r;
|
||||
|
||||
/*
|
||||
* Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes
|
||||
* it's just a matter of XORing the bits.
|
||||
*/
|
||||
other_reg = (void __iomem *)((u32)reg ^ (CM_FCLKEN ^ CM_ICLKEN));
|
||||
r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN));
|
||||
|
||||
/* Check if both functional and interface clocks
|
||||
* are running. */
|
||||
bit = 1 << clk->enable_bit;
|
||||
if (!(__raw_readl(other_reg) & bit))
|
||||
return;
|
||||
st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
|
||||
|
||||
omap2_wait_clock_ready(st_reg, bit, clk->name);
|
||||
*other_reg = (__force void __iomem *)r;
|
||||
*other_bit = clk->enable_bit;
|
||||
}
|
||||
|
||||
static int omap2_dflt_clk_enable(struct clk *clk)
|
||||
/**
|
||||
* omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk
|
||||
* @clk: struct clk * to find IDLEST info for
|
||||
* @idlest_reg: void __iomem ** to return the CM_IDLEST va in
|
||||
* @idlest_bit: u8 ** to return the CM_IDLEST bit shift in
|
||||
*
|
||||
* Return the CM_IDLEST register address and bit shift corresponding
|
||||
* to the module that "owns" this clock. This default code assumes
|
||||
* that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that
|
||||
* the IDLEST register address ID corresponds to the CM_*CLKEN
|
||||
* register address ID (e.g., that CM_FCLKEN2 corresponds to
|
||||
* CM_IDLEST2). This is not true for all modules. No return value.
|
||||
*/
|
||||
void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
|
||||
u8 *idlest_bit)
|
||||
{
|
||||
u32 r;
|
||||
|
||||
r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
|
||||
*idlest_reg = (__force void __iomem *)r;
|
||||
*idlest_bit = clk->enable_bit;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap2_module_wait_ready - wait for an OMAP module to leave IDLE
|
||||
* @clk: struct clk * belonging to the module
|
||||
*
|
||||
* If the necessary clocks for the OMAP hardware IP block that
|
||||
* corresponds to clock @clk are enabled, then wait for the module to
|
||||
* indicate readiness (i.e., to leave IDLE). This code does not
|
||||
* belong in the clock code and will be moved in the medium term to
|
||||
* module-dependent code. No return value.
|
||||
*/
|
||||
static void omap2_module_wait_ready(struct clk *clk)
|
||||
{
|
||||
void __iomem *companion_reg, *idlest_reg;
|
||||
u8 other_bit, idlest_bit;
|
||||
|
||||
/* Not all modules have multiple clocks that their IDLEST depends on */
|
||||
if (clk->ops->find_companion) {
|
||||
clk->ops->find_companion(clk, &companion_reg, &other_bit);
|
||||
if (!(__raw_readl(companion_reg) & (1 << other_bit)))
|
||||
return;
|
||||
}
|
||||
|
||||
clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit);
|
||||
|
||||
omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name);
|
||||
}
|
||||
|
||||
int omap2_dflt_clk_enable(struct clk *clk)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
if (unlikely(clk->enable_reg == NULL)) {
|
||||
printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
|
||||
pr_err("clock.c: Enable for %s without enable code\n",
|
||||
clk->name);
|
||||
return 0; /* REVISIT: -EINVAL */
|
||||
}
|
||||
|
@ -363,26 +376,13 @@ static int omap2_dflt_clk_enable(struct clk *clk)
|
|||
__raw_writel(v, clk->enable_reg);
|
||||
v = __raw_readl(clk->enable_reg); /* OCP barrier */
|
||||
|
||||
if (clk->ops->find_idlest)
|
||||
omap2_module_wait_ready(clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int omap2_dflt_clk_enable_wait(struct clk *clk)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (!clk->enable_reg) {
|
||||
printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
|
||||
clk->name);
|
||||
return 0; /* REVISIT: -EINVAL */
|
||||
}
|
||||
|
||||
ret = omap2_dflt_clk_enable(clk);
|
||||
if (ret == 0)
|
||||
omap2_clk_wait_ready(clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void omap2_dflt_clk_disable(struct clk *clk)
|
||||
void omap2_dflt_clk_disable(struct clk *clk)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
|
@ -406,8 +406,10 @@ static void omap2_dflt_clk_disable(struct clk *clk)
|
|||
}
|
||||
|
||||
const struct clkops clkops_omap2_dflt_wait = {
|
||||
.enable = omap2_dflt_clk_enable_wait,
|
||||
.enable = omap2_dflt_clk_enable,
|
||||
.disable = omap2_dflt_clk_disable,
|
||||
.find_companion = omap2_clk_dflt_find_companion,
|
||||
.find_idlest = omap2_clk_dflt_find_idlest,
|
||||
};
|
||||
|
||||
const struct clkops clkops_omap2_dflt = {
|
||||
|
|
|
@ -65,6 +65,12 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
|
|||
u32 omap2_get_dpll_rate(struct clk *clk);
|
||||
int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
|
||||
void omap2_clk_prepare_for_reboot(void);
|
||||
int omap2_dflt_clk_enable(struct clk *clk);
|
||||
void omap2_dflt_clk_disable(struct clk *clk);
|
||||
void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
|
||||
u8 *other_bit);
|
||||
void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
|
||||
u8 *idlest_bit);
|
||||
|
||||
extern const struct clkops clkops_omap2_dflt_wait;
|
||||
extern const struct clkops clkops_omap2_dflt;
|
||||
|
|
|
@ -30,6 +30,7 @@
|
|||
|
||||
#include <mach/clock.h>
|
||||
#include <mach/sram.h>
|
||||
#include <mach/prcm.h>
|
||||
#include <asm/div64.h>
|
||||
#include <asm/clkdev.h>
|
||||
|
||||
|
@ -43,6 +44,18 @@
|
|||
static const struct clkops clkops_oscck;
|
||||
static const struct clkops clkops_fixed;
|
||||
|
||||
static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
|
||||
void __iomem **idlest_reg,
|
||||
u8 *idlest_bit);
|
||||
|
||||
/* 2430 I2CHS has non-standard IDLEST register */
|
||||
static const struct clkops clkops_omap2430_i2chs_wait = {
|
||||
.enable = omap2_dflt_clk_enable,
|
||||
.disable = omap2_dflt_clk_disable,
|
||||
.find_idlest = omap2430_clk_i2chs_find_idlest,
|
||||
.find_companion = omap2_clk_dflt_find_companion,
|
||||
};
|
||||
|
||||
#include "clock24xx.h"
|
||||
|
||||
struct omap_clk {
|
||||
|
@ -239,6 +252,26 @@ static void __iomem *prcm_clksrc_ctrl;
|
|||
* Omap24xx specific clock functions
|
||||
*-------------------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS
|
||||
* @clk: struct clk * being enabled
|
||||
* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
|
||||
* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
|
||||
*
|
||||
* OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the
|
||||
* CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function
|
||||
* passes back the correct CM_IDLEST register address for I2CHS
|
||||
* modules. No return value.
|
||||
*/
|
||||
static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
|
||||
void __iomem **idlest_reg,
|
||||
u8 *idlest_bit)
|
||||
{
|
||||
*idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST);
|
||||
*idlest_bit = clk->enable_bit;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* omap2xxx_clk_get_core_rate - return the CORE_CLK rate
|
||||
* @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
|
||||
|
@ -325,8 +358,8 @@ static int omap2_clk_fixed_enable(struct clk *clk)
|
|||
else if (clk == &apll54_ck)
|
||||
cval = OMAP24XX_ST_54M_APLL;
|
||||
|
||||
omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
|
||||
clk->name);
|
||||
omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
|
||||
clk->name);
|
||||
|
||||
/*
|
||||
* REVISIT: Should we return an error code if omap2_wait_clock_ready()
|
||||
|
|
|
@ -2337,7 +2337,7 @@ static struct clk i2c2_fck = {
|
|||
|
||||
static struct clk i2chs2_fck = {
|
||||
.name = "i2c_fck",
|
||||
.ops = &clkops_omap2_dflt_wait,
|
||||
.ops = &clkops_omap2430_i2chs_wait,
|
||||
.id = 2,
|
||||
.parent = &func_96m_ck,
|
||||
.clkdm_name = "core_l4_clkdm",
|
||||
|
@ -2370,7 +2370,7 @@ static struct clk i2c1_fck = {
|
|||
|
||||
static struct clk i2chs1_fck = {
|
||||
.name = "i2c_fck",
|
||||
.ops = &clkops_omap2_dflt_wait,
|
||||
.ops = &clkops_omap2430_i2chs_wait,
|
||||
.id = 1,
|
||||
.parent = &func_96m_ck,
|
||||
.clkdm_name = "core_l4_clkdm",
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
* OMAP3-specific clock framework functions
|
||||
*
|
||||
* Copyright (C) 2007-2008 Texas Instruments, Inc.
|
||||
* Copyright (C) 2007-2008 Nokia Corporation
|
||||
* Copyright (C) 2007-2009 Nokia Corporation
|
||||
*
|
||||
* Written by Paul Walmsley
|
||||
* Testing and integration fixes by Jouni Högander
|
||||
|
@ -41,6 +41,37 @@
|
|||
|
||||
static const struct clkops clkops_noncore_dpll_ops;
|
||||
|
||||
static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
|
||||
void __iomem **idlest_reg,
|
||||
u8 *idlest_bit);
|
||||
static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
|
||||
void __iomem **idlest_reg,
|
||||
u8 *idlest_bit);
|
||||
static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
|
||||
void __iomem **idlest_reg,
|
||||
u8 *idlest_bit);
|
||||
|
||||
static const struct clkops clkops_omap3430es2_ssi_wait = {
|
||||
.enable = omap2_dflt_clk_enable,
|
||||
.disable = omap2_dflt_clk_disable,
|
||||
.find_idlest = omap3430es2_clk_ssi_find_idlest,
|
||||
.find_companion = omap2_clk_dflt_find_companion,
|
||||
};
|
||||
|
||||
static const struct clkops clkops_omap3430es2_hsotgusb_wait = {
|
||||
.enable = omap2_dflt_clk_enable,
|
||||
.disable = omap2_dflt_clk_disable,
|
||||
.find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
|
||||
.find_companion = omap2_clk_dflt_find_companion,
|
||||
};
|
||||
|
||||
static const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
|
||||
.enable = omap2_dflt_clk_enable,
|
||||
.disable = omap2_dflt_clk_disable,
|
||||
.find_idlest = omap3430es2_clk_dss_usbhost_find_idlest,
|
||||
.find_companion = omap2_clk_dflt_find_companion,
|
||||
};
|
||||
|
||||
#include "clock34xx.h"
|
||||
|
||||
struct omap_clk {
|
||||
|
@ -157,10 +188,13 @@ static struct omap_clk omap34xx_clks[] = {
|
|||
CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
|
||||
CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X),
|
||||
CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X),
|
||||
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X),
|
||||
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X),
|
||||
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
|
||||
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2),
|
||||
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
|
||||
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2),
|
||||
CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X),
|
||||
CLK("musb_hdrc", "ick", &hsotgusb_ick, CK_343X),
|
||||
CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
|
||||
CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2),
|
||||
CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X),
|
||||
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X),
|
||||
CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
|
||||
|
@ -193,18 +227,21 @@ static struct omap_clk omap34xx_clks[] = {
|
|||
CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
|
||||
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X),
|
||||
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
|
||||
CLK(NULL, "ssi_ick", &ssi_ick, CK_343X),
|
||||
CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
|
||||
CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2),
|
||||
CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
|
||||
CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
|
||||
CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
|
||||
CLK("omap_rng", "ick", &rng_ick, CK_343X),
|
||||
CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
|
||||
CLK(NULL, "des1_ick", &des1_ick, CK_343X),
|
||||
CLK("omapfb", "dss1_fck", &dss1_alwon_fck, CK_343X),
|
||||
CLK("omapfb", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
|
||||
CLK("omapfb", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2),
|
||||
CLK("omapfb", "tv_fck", &dss_tv_fck, CK_343X),
|
||||
CLK("omapfb", "video_fck", &dss_96m_fck, CK_343X),
|
||||
CLK("omapfb", "dss2_fck", &dss2_alwon_fck, CK_343X),
|
||||
CLK("omapfb", "ick", &dss_ick, CK_343X),
|
||||
CLK("omapfb", "ick", &dss_ick_3430es1, CK_3430ES1),
|
||||
CLK("omapfb", "ick", &dss_ick_3430es2, CK_3430ES2),
|
||||
CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
|
||||
CLK(NULL, "cam_ick", &cam_ick, CK_343X),
|
||||
CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
|
||||
|
@ -300,6 +337,73 @@ static struct omap_clk omap34xx_clks[] = {
|
|||
*/
|
||||
#define SDRC_MPURATE_LOOPS 96
|
||||
|
||||
/**
|
||||
* omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
|
||||
* @clk: struct clk * being enabled
|
||||
* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
|
||||
* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
|
||||
*
|
||||
* The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
|
||||
* from the CM_{I,F}CLKEN bit. Pass back the correct info via
|
||||
* @idlest_reg and @idlest_bit. No return value.
|
||||
*/
|
||||
static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
|
||||
void __iomem **idlest_reg,
|
||||
u8 *idlest_bit)
|
||||
{
|
||||
u32 r;
|
||||
|
||||
r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
|
||||
*idlest_reg = (__force void __iomem *)r;
|
||||
*idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
|
||||
* @clk: struct clk * being enabled
|
||||
* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
|
||||
* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
|
||||
*
|
||||
* Some OMAP modules on OMAP3 ES2+ chips have both initiator and
|
||||
* target IDLEST bits. For our purposes, we are concerned with the
|
||||
* target IDLEST bits, which exist at a different bit position than
|
||||
* the *CLKEN bit position for these modules (DSS and USBHOST) (The
|
||||
* default find_idlest code assumes that they are at the same
|
||||
* position.) No return value.
|
||||
*/
|
||||
static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
|
||||
void __iomem **idlest_reg,
|
||||
u8 *idlest_bit)
|
||||
{
|
||||
u32 r;
|
||||
|
||||
r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
|
||||
*idlest_reg = (__force void __iomem *)r;
|
||||
/* USBHOST_IDLE has same shift */
|
||||
*idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
|
||||
* @clk: struct clk * being enabled
|
||||
* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
|
||||
* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
|
||||
*
|
||||
* The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different
|
||||
* shift from the CM_{I,F}CLKEN bit. Pass back the correct info via
|
||||
* @idlest_reg and @idlest_bit. No return value.
|
||||
*/
|
||||
static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
|
||||
void __iomem **idlest_reg,
|
||||
u8 *idlest_bit)
|
||||
{
|
||||
u32 r;
|
||||
|
||||
r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
|
||||
*idlest_reg = (__force void __iomem *)r;
|
||||
*idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap3_dpll_recalc - recalculate DPLL rate
|
||||
* @clk: DPLL struct clk
|
||||
|
@ -725,7 +829,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
|
|||
u32 unlock_dll = 0;
|
||||
u32 c;
|
||||
unsigned long validrate, sdrcrate, mpurate;
|
||||
struct omap_sdrc_params *sp;
|
||||
struct omap_sdrc_params *sdrc_cs0;
|
||||
struct omap_sdrc_params *sdrc_cs1;
|
||||
int ret;
|
||||
|
||||
if (!clk || !rate)
|
||||
return -EINVAL;
|
||||
|
@ -743,8 +849,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
|
|||
else
|
||||
sdrcrate >>= ((clk->rate / rate) >> 1);
|
||||
|
||||
sp = omap2_sdrc_get_params(sdrcrate);
|
||||
if (!sp)
|
||||
ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
|
||||
if (ret)
|
||||
return -EINVAL;
|
||||
|
||||
if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
|
||||
|
@ -765,12 +871,29 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
|
|||
|
||||
pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
|
||||
validrate);
|
||||
pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
|
||||
sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
|
||||
pr_debug("clock: SDRC CS0 timing params used:"
|
||||
" RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
|
||||
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
|
||||
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
|
||||
if (sdrc_cs1)
|
||||
pr_debug("clock: SDRC CS1 timing params used: "
|
||||
" RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
|
||||
sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
|
||||
sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
|
||||
|
||||
omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
|
||||
sp->actim_ctrlb, new_div, unlock_dll, c,
|
||||
sp->mr, rate > clk->rate);
|
||||
if (sdrc_cs1)
|
||||
omap3_configure_core_dpll(
|
||||
new_div, unlock_dll, c, rate > clk->rate,
|
||||
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
|
||||
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
|
||||
sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
|
||||
sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
|
||||
else
|
||||
omap3_configure_core_dpll(
|
||||
new_div, unlock_dll, c, rate > clk->rate,
|
||||
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
|
||||
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
|
||||
0, 0, 0, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -1568,7 +1568,7 @@ static const struct clksel ssi_ssr_clksel[] = {
|
|||
{ .parent = NULL }
|
||||
};
|
||||
|
||||
static struct clk ssi_ssr_fck = {
|
||||
static struct clk ssi_ssr_fck_3430es1 = {
|
||||
.name = "ssi_ssr_fck",
|
||||
.ops = &clkops_omap2_dflt,
|
||||
.init = &omap2_init_clksel_parent,
|
||||
|
@ -1581,10 +1581,31 @@ static struct clk ssi_ssr_fck = {
|
|||
.recalc = &omap2_clksel_recalc,
|
||||
};
|
||||
|
||||
static struct clk ssi_sst_fck = {
|
||||
static struct clk ssi_ssr_fck_3430es2 = {
|
||||
.name = "ssi_ssr_fck",
|
||||
.ops = &clkops_omap3430es2_ssi_wait,
|
||||
.init = &omap2_init_clksel_parent,
|
||||
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
||||
.enable_bit = OMAP3430_EN_SSI_SHIFT,
|
||||
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
|
||||
.clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
|
||||
.clksel = ssi_ssr_clksel,
|
||||
.clkdm_name = "core_l4_clkdm",
|
||||
.recalc = &omap2_clksel_recalc,
|
||||
};
|
||||
|
||||
static struct clk ssi_sst_fck_3430es1 = {
|
||||
.name = "ssi_sst_fck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &ssi_ssr_fck,
|
||||
.parent = &ssi_ssr_fck_3430es1,
|
||||
.fixed_div = 2,
|
||||
.recalc = &omap2_fixed_divisor_recalc,
|
||||
};
|
||||
|
||||
static struct clk ssi_sst_fck_3430es2 = {
|
||||
.name = "ssi_sst_fck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &ssi_ssr_fck_3430es2,
|
||||
.fixed_div = 2,
|
||||
.recalc = &omap2_fixed_divisor_recalc,
|
||||
};
|
||||
|
@ -1606,9 +1627,19 @@ static struct clk core_l3_ick = {
|
|||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk hsotgusb_ick = {
|
||||
static struct clk hsotgusb_ick_3430es1 = {
|
||||
.name = "hsotgusb_ick",
|
||||
.ops = &clkops_omap2_dflt_wait,
|
||||
.ops = &clkops_omap2_dflt,
|
||||
.parent = &core_l3_ick,
|
||||
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
||||
.enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
|
||||
.clkdm_name = "core_l3_clkdm",
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk hsotgusb_ick_3430es2 = {
|
||||
.name = "hsotgusb_ick",
|
||||
.ops = &clkops_omap3430es2_hsotgusb_wait,
|
||||
.parent = &core_l3_ick,
|
||||
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
||||
.enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
|
||||
|
@ -1947,7 +1978,7 @@ static struct clk ssi_l4_ick = {
|
|||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk ssi_ick = {
|
||||
static struct clk ssi_ick_3430es1 = {
|
||||
.name = "ssi_ick",
|
||||
.ops = &clkops_omap2_dflt,
|
||||
.parent = &ssi_l4_ick,
|
||||
|
@ -1957,6 +1988,16 @@ static struct clk ssi_ick = {
|
|||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk ssi_ick_3430es2 = {
|
||||
.name = "ssi_ick",
|
||||
.ops = &clkops_omap3430es2_ssi_wait,
|
||||
.parent = &ssi_l4_ick,
|
||||
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
||||
.enable_bit = OMAP3430_EN_SSI_SHIFT,
|
||||
.clkdm_name = "core_l4_clkdm",
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
|
||||
* but l4_ick makes more sense to me */
|
||||
|
||||
|
@ -2024,7 +2065,7 @@ static struct clk des1_ick = {
|
|||
};
|
||||
|
||||
/* DSS */
|
||||
static struct clk dss1_alwon_fck = {
|
||||
static struct clk dss1_alwon_fck_3430es1 = {
|
||||
.name = "dss1_alwon_fck",
|
||||
.ops = &clkops_omap2_dflt,
|
||||
.parent = &dpll4_m4x2_ck,
|
||||
|
@ -2034,6 +2075,16 @@ static struct clk dss1_alwon_fck = {
|
|||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk dss1_alwon_fck_3430es2 = {
|
||||
.name = "dss1_alwon_fck",
|
||||
.ops = &clkops_omap3430es2_dss_usbhost_wait,
|
||||
.parent = &dpll4_m4x2_ck,
|
||||
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
|
||||
.enable_bit = OMAP3430_EN_DSS1_SHIFT,
|
||||
.clkdm_name = "dss_clkdm",
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk dss_tv_fck = {
|
||||
.name = "dss_tv_fck",
|
||||
.ops = &clkops_omap2_dflt,
|
||||
|
@ -2067,7 +2118,7 @@ static struct clk dss2_alwon_fck = {
|
|||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk dss_ick = {
|
||||
static struct clk dss_ick_3430es1 = {
|
||||
/* Handles both L3 and L4 clocks */
|
||||
.name = "dss_ick",
|
||||
.ops = &clkops_omap2_dflt,
|
||||
|
@ -2079,6 +2130,18 @@ static struct clk dss_ick = {
|
|||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk dss_ick_3430es2 = {
|
||||
/* Handles both L3 and L4 clocks */
|
||||
.name = "dss_ick",
|
||||
.ops = &clkops_omap3430es2_dss_usbhost_wait,
|
||||
.parent = &l4_ick,
|
||||
.init = &omap2_init_clk_clkdm,
|
||||
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
|
||||
.enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
|
||||
.clkdm_name = "dss_clkdm",
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
/* CAM */
|
||||
|
||||
static struct clk cam_mclk = {
|
||||
|
@ -2118,7 +2181,7 @@ static struct clk csi2_96m_fck = {
|
|||
|
||||
static struct clk usbhost_120m_fck = {
|
||||
.name = "usbhost_120m_fck",
|
||||
.ops = &clkops_omap2_dflt_wait,
|
||||
.ops = &clkops_omap2_dflt,
|
||||
.parent = &dpll5_m2_ck,
|
||||
.init = &omap2_init_clk_clkdm,
|
||||
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
|
||||
|
@ -2129,7 +2192,7 @@ static struct clk usbhost_120m_fck = {
|
|||
|
||||
static struct clk usbhost_48m_fck = {
|
||||
.name = "usbhost_48m_fck",
|
||||
.ops = &clkops_omap2_dflt_wait,
|
||||
.ops = &clkops_omap3430es2_dss_usbhost_wait,
|
||||
.parent = &omap_48m_fck,
|
||||
.init = &omap2_init_clk_clkdm,
|
||||
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
|
||||
|
@ -2141,7 +2204,7 @@ static struct clk usbhost_48m_fck = {
|
|||
static struct clk usbhost_ick = {
|
||||
/* Handles both L3 and L4 clocks */
|
||||
.name = "usbhost_ick",
|
||||
.ops = &clkops_omap2_dflt_wait,
|
||||
.ops = &clkops_omap3430es2_dss_usbhost_wait,
|
||||
.parent = &l4_ick,
|
||||
.init = &omap2_init_clk_clkdm,
|
||||
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
|
||||
|
|
|
@ -29,9 +29,9 @@
|
|||
* These registers appear once per CM module.
|
||||
*/
|
||||
|
||||
#define OMAP3430_CM_REVISION OMAP_CM_REGADDR(OCP_MOD, 0x0000)
|
||||
#define OMAP3430_CM_SYSCONFIG OMAP_CM_REGADDR(OCP_MOD, 0x0010)
|
||||
#define OMAP3430_CM_POLCTRL OMAP_CM_REGADDR(OCP_MOD, 0x009c)
|
||||
#define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
|
||||
#define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
|
||||
#define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
|
||||
|
||||
#define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070
|
||||
#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
|
||||
|
|
|
@ -276,14 +276,15 @@ static int __init _omap2_init_reprogram_sdrc(void)
|
|||
return v;
|
||||
}
|
||||
|
||||
void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
|
||||
void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
|
||||
struct omap_sdrc_params *sdrc_cs1)
|
||||
{
|
||||
omap2_mux_init();
|
||||
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
|
||||
pwrdm_init(powerdomains_omap);
|
||||
clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
|
||||
omap2_clk_init();
|
||||
omap2_sdrc_init(sp);
|
||||
omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
|
||||
_omap2_init_reprogram_sdrc();
|
||||
#endif
|
||||
gpmc_init();
|
||||
|
|
|
@ -19,7 +19,6 @@
|
|||
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/dma.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/mux.h>
|
||||
#include <mach/cpu.h>
|
||||
#include <mach/mcbsp.h>
|
||||
|
|
|
@ -119,6 +119,7 @@ static int twl_mmc_late_init(struct device *dev)
|
|||
if (i != 0)
|
||||
break;
|
||||
ret = PTR_ERR(reg);
|
||||
hsmmc[i].vcc = NULL;
|
||||
goto err;
|
||||
}
|
||||
hsmmc[i].vcc = reg;
|
||||
|
@ -165,8 +166,13 @@ done:
|
|||
static void twl_mmc_cleanup(struct device *dev)
|
||||
{
|
||||
struct omap_mmc_platform_data *mmc = dev->platform_data;
|
||||
int i;
|
||||
|
||||
gpio_free(mmc->slots[0].switch_pin);
|
||||
for(i = 0; i < ARRAY_SIZE(hsmmc); i++) {
|
||||
regulator_put(hsmmc[i].vcc);
|
||||
regulator_put(hsmmc[i].vcc_aux);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
|
|
@ -486,6 +486,12 @@ MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c,
|
|||
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
|
||||
MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
|
||||
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
|
||||
|
||||
/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
|
||||
MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262,
|
||||
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
|
||||
MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264,
|
||||
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
|
||||
};
|
||||
|
||||
#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins)
|
||||
|
|
|
@ -11,9 +11,6 @@
|
|||
#ifndef __ARCH_ARM_MACH_OMAP2_PM_H
|
||||
#define __ARCH_ARM_MACH_OMAP2_PM_H
|
||||
|
||||
extern int omap2_pm_init(void);
|
||||
extern int omap3_pm_init(void);
|
||||
|
||||
#ifdef CONFIG_PM_DEBUG
|
||||
extern void omap2_pm_dump(int mode, int resume, unsigned int us);
|
||||
extern int omap2_pm_debug;
|
||||
|
|
|
@ -470,7 +470,7 @@ static void __init prcm_setup_regs(void)
|
|||
WKUP_MOD, PM_WKEN);
|
||||
}
|
||||
|
||||
int __init omap2_pm_init(void)
|
||||
static int __init omap2_pm_init(void)
|
||||
{
|
||||
u32 l;
|
||||
|
||||
|
|
|
@ -39,7 +39,9 @@
|
|||
struct power_state {
|
||||
struct powerdomain *pwrdm;
|
||||
u32 next_state;
|
||||
#ifdef CONFIG_SUSPEND
|
||||
u32 saved_state;
|
||||
#endif
|
||||
struct list_head node;
|
||||
};
|
||||
|
||||
|
@ -293,6 +295,9 @@ out:
|
|||
local_irq_enable();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SUSPEND
|
||||
static suspend_state_t suspend_state;
|
||||
|
||||
static int omap3_pm_prepare(void)
|
||||
{
|
||||
disable_hlt();
|
||||
|
@ -321,7 +326,6 @@ static int omap3_pm_suspend(void)
|
|||
restore:
|
||||
/* Restore next_pwrsts */
|
||||
list_for_each_entry(pwrst, &pwrst_list, node) {
|
||||
set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
|
||||
state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
|
||||
if (state > pwrst->next_state) {
|
||||
printk(KERN_INFO "Powerdomain (%s) didn't enter "
|
||||
|
@ -329,6 +333,7 @@ restore:
|
|||
pwrst->pwrdm->name, pwrst->next_state);
|
||||
ret = -1;
|
||||
}
|
||||
set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
|
||||
}
|
||||
if (ret)
|
||||
printk(KERN_ERR "Could not enter target state in pm_suspend\n");
|
||||
|
@ -339,11 +344,11 @@ restore:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int omap3_pm_enter(suspend_state_t state)
|
||||
static int omap3_pm_enter(suspend_state_t unused)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
switch (state) {
|
||||
switch (suspend_state) {
|
||||
case PM_SUSPEND_STANDBY:
|
||||
case PM_SUSPEND_MEM:
|
||||
ret = omap3_pm_suspend();
|
||||
|
@ -360,12 +365,30 @@ static void omap3_pm_finish(void)
|
|||
enable_hlt();
|
||||
}
|
||||
|
||||
/* Hooks to enable / disable UART interrupts during suspend */
|
||||
static int omap3_pm_begin(suspend_state_t state)
|
||||
{
|
||||
suspend_state = state;
|
||||
omap_uart_enable_irqs(0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void omap3_pm_end(void)
|
||||
{
|
||||
suspend_state = PM_SUSPEND_ON;
|
||||
omap_uart_enable_irqs(1);
|
||||
return;
|
||||
}
|
||||
|
||||
static struct platform_suspend_ops omap_pm_ops = {
|
||||
.begin = omap3_pm_begin,
|
||||
.end = omap3_pm_end,
|
||||
.prepare = omap3_pm_prepare,
|
||||
.enter = omap3_pm_enter,
|
||||
.finish = omap3_pm_finish,
|
||||
.valid = suspend_valid_only_mem,
|
||||
};
|
||||
#endif /* CONFIG_SUSPEND */
|
||||
|
||||
|
||||
/**
|
||||
|
@ -613,6 +636,24 @@ static void __init prcm_setup_regs(void)
|
|||
/* Clear any pending PRCM interrupts */
|
||||
prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
|
||||
|
||||
/* Don't attach IVA interrupts */
|
||||
prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
|
||||
prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
|
||||
prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
|
||||
prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
|
||||
|
||||
/* Clear any pending 'reset' flags */
|
||||
prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
|
||||
prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
|
||||
prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
|
||||
prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
|
||||
prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
|
||||
prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
|
||||
prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
|
||||
|
||||
/* Clear any pending PRCM interrupts */
|
||||
prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
|
||||
|
||||
omap3_iva_idle();
|
||||
omap3_d2d_idle();
|
||||
}
|
||||
|
@ -652,7 +693,7 @@ static int __init clkdms_setup(struct clockdomain *clkdm)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int __init omap3_pm_init(void)
|
||||
static int __init omap3_pm_init(void)
|
||||
{
|
||||
struct power_state *pwrst, *tmp;
|
||||
int ret;
|
||||
|
@ -692,7 +733,9 @@ int __init omap3_pm_init(void)
|
|||
_omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
|
||||
omap34xx_cpu_suspend_sz);
|
||||
|
||||
#ifdef CONFIG_SUSPEND
|
||||
suspend_set_ops(&omap_pm_ops);
|
||||
#endif /* CONFIG_SUSPEND */
|
||||
|
||||
pm_idle = omap3_pm_idle;
|
||||
|
||||
|
|
|
@ -17,6 +17,7 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include <mach/common.h>
|
||||
#include <mach/prcm.h>
|
||||
|
@ -28,6 +29,8 @@
|
|||
static void __iomem *prm_base;
|
||||
static void __iomem *cm_base;
|
||||
|
||||
#define MAX_MODULE_ENABLE_WAIT 100000
|
||||
|
||||
u32 omap_prcm_get_reset_sources(void)
|
||||
{
|
||||
/* XXX This presumably needs modification for 34XX */
|
||||
|
@ -120,6 +123,46 @@ u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
|
|||
}
|
||||
EXPORT_SYMBOL(cm_rmw_mod_reg_bits);
|
||||
|
||||
/**
|
||||
* omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
|
||||
* @reg: physical address of module IDLEST register
|
||||
* @mask: value to mask against to determine if the module is active
|
||||
* @name: name of the clock (for printk)
|
||||
*
|
||||
* Returns 1 if the module indicated readiness in time, or 0 if it
|
||||
* failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
|
||||
*/
|
||||
int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name)
|
||||
{
|
||||
int i = 0;
|
||||
int ena = 0;
|
||||
|
||||
/*
|
||||
* 24xx uses 0 to indicate not ready, and 1 to indicate ready.
|
||||
* 34xx reverses this, just to keep us on our toes
|
||||
*/
|
||||
if (cpu_is_omap24xx())
|
||||
ena = mask;
|
||||
else if (cpu_is_omap34xx())
|
||||
ena = 0;
|
||||
else
|
||||
BUG();
|
||||
|
||||
/* Wait for lock */
|
||||
while (((__raw_readl(reg) & mask) != ena) &&
|
||||
(i++ < MAX_MODULE_ENABLE_WAIT))
|
||||
udelay(1);
|
||||
|
||||
if (i < MAX_MODULE_ENABLE_WAIT)
|
||||
pr_debug("cm: Module associated with clock %s ready after %d "
|
||||
"loops\n", name, i);
|
||||
else
|
||||
pr_err("cm: Module associated with clock %s didn't enable in "
|
||||
"%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
|
||||
|
||||
return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
|
||||
};
|
||||
|
||||
void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
|
||||
{
|
||||
prm_base = omap2_globals->prm;
|
||||
|
|
|
@ -32,7 +32,7 @@
|
|||
#include <mach/sdrc.h>
|
||||
#include "sdrc.h"
|
||||
|
||||
static struct omap_sdrc_params *sdrc_init_params;
|
||||
static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
|
||||
|
||||
void __iomem *omap2_sdrc_base;
|
||||
void __iomem *omap2_sms_base;
|
||||
|
@ -45,33 +45,49 @@ void __iomem *omap2_sms_base;
|
|||
/**
|
||||
* omap2_sdrc_get_params - return SDRC register values for a given clock rate
|
||||
* @r: SDRC clock rate (in Hz)
|
||||
* @sdrc_cs0: chip select 0 ram timings **
|
||||
* @sdrc_cs1: chip select 1 ram timings **
|
||||
*
|
||||
* Return pre-calculated values for the SDRC_ACTIM_CTRLA,
|
||||
* SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a given
|
||||
* SDRC clock rate 'r'. These parameters control various timing
|
||||
* delays in the SDRAM controller that are expressed in terms of the
|
||||
* number of SDRC clock cycles to wait; hence the clock rate
|
||||
* dependency. Note that sdrc_init_params must be sorted rate
|
||||
* descending. Also assumes that both chip-selects use the same
|
||||
* timing parameters. Returns a struct omap_sdrc_params * upon
|
||||
* success, or NULL upon failure.
|
||||
* SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
|
||||
* structs,for a given SDRC clock rate 'r'.
|
||||
* These parameters control various timing delays in the SDRAM controller
|
||||
* that are expressed in terms of the number of SDRC clock cycles to
|
||||
* wait; hence the clock rate dependency.
|
||||
*
|
||||
* Supports 2 different timing parameters for both chip selects.
|
||||
*
|
||||
* Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
|
||||
* Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
|
||||
* as sdrc_init_params_cs_0.
|
||||
*
|
||||
* Fills in the struct omap_sdrc_params * for each chip select.
|
||||
* Returns 0 upon success or -1 upon failure.
|
||||
*/
|
||||
struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r)
|
||||
int omap2_sdrc_get_params(unsigned long r,
|
||||
struct omap_sdrc_params **sdrc_cs0,
|
||||
struct omap_sdrc_params **sdrc_cs1)
|
||||
{
|
||||
struct omap_sdrc_params *sp;
|
||||
struct omap_sdrc_params *sp0, *sp1;
|
||||
|
||||
if (!sdrc_init_params)
|
||||
return NULL;
|
||||
if (!sdrc_init_params_cs0)
|
||||
return -1;
|
||||
|
||||
sp = sdrc_init_params;
|
||||
sp0 = sdrc_init_params_cs0;
|
||||
sp1 = sdrc_init_params_cs1;
|
||||
|
||||
while (sp->rate && sp->rate != r)
|
||||
sp++;
|
||||
while (sp0->rate && sp0->rate != r) {
|
||||
sp0++;
|
||||
if (sdrc_init_params_cs1)
|
||||
sp1++;
|
||||
}
|
||||
|
||||
if (!sp->rate)
|
||||
return NULL;
|
||||
if (!sp0->rate)
|
||||
return -1;
|
||||
|
||||
return sp;
|
||||
*sdrc_cs0 = sp0;
|
||||
*sdrc_cs1 = sp1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
@ -83,13 +99,15 @@ void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
|
|||
|
||||
/**
|
||||
* omap2_sdrc_init - initialize SMS, SDRC devices on boot
|
||||
* @sp: pointer to a null-terminated list of struct omap_sdrc_params
|
||||
* @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params
|
||||
* Support for 2 chip selects timings
|
||||
*
|
||||
* Turn on smart idle modes for SDRAM scheduler and controller.
|
||||
* Program a known-good configuration for the SDRC to deal with buggy
|
||||
* bootloaders.
|
||||
*/
|
||||
void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
|
||||
void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
|
||||
struct omap_sdrc_params *sdrc_cs1)
|
||||
{
|
||||
u32 l;
|
||||
|
||||
|
@ -103,11 +121,15 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
|
|||
l |= (0x2 << 3);
|
||||
sdrc_write_reg(l, SDRC_SYSCONFIG);
|
||||
|
||||
sdrc_init_params = sp;
|
||||
sdrc_init_params_cs0 = sdrc_cs0;
|
||||
sdrc_init_params_cs1 = sdrc_cs1;
|
||||
|
||||
/* XXX Enable SRFRONIDLEREQ here also? */
|
||||
/*
|
||||
* PWDENA should not be set due to 34xx erratum 1.150 - PWDENA
|
||||
* can cause random memory corruption
|
||||
*/
|
||||
l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
|
||||
(1 << SDRC_POWER_PWDENA_SHIFT) |
|
||||
(1 << SDRC_POWER_PAGEPOLICY_SHIFT);
|
||||
sdrc_write_reg(l, SDRC_POWER);
|
||||
}
|
||||
|
|
|
@ -54,6 +54,7 @@ struct omap_uart_state {
|
|||
|
||||
struct plat_serial8250_port *p;
|
||||
struct list_head node;
|
||||
struct platform_device pdev;
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
|
||||
int context_valid;
|
||||
|
@ -68,10 +69,9 @@ struct omap_uart_state {
|
|||
#endif
|
||||
};
|
||||
|
||||
static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS];
|
||||
static LIST_HEAD(uart_list);
|
||||
|
||||
static struct plat_serial8250_port serial_platform_data[] = {
|
||||
static struct plat_serial8250_port serial_platform_data0[] = {
|
||||
{
|
||||
.membase = IO_ADDRESS(OMAP_UART1_BASE),
|
||||
.mapbase = OMAP_UART1_BASE,
|
||||
|
@ -81,6 +81,12 @@ static struct plat_serial8250_port serial_platform_data[] = {
|
|||
.regshift = 2,
|
||||
.uartclk = OMAP24XX_BASE_BAUD * 16,
|
||||
}, {
|
||||
.flags = 0
|
||||
}
|
||||
};
|
||||
|
||||
static struct plat_serial8250_port serial_platform_data1[] = {
|
||||
{
|
||||
.membase = IO_ADDRESS(OMAP_UART2_BASE),
|
||||
.mapbase = OMAP_UART2_BASE,
|
||||
.irq = 73,
|
||||
|
@ -89,6 +95,12 @@ static struct plat_serial8250_port serial_platform_data[] = {
|
|||
.regshift = 2,
|
||||
.uartclk = OMAP24XX_BASE_BAUD * 16,
|
||||
}, {
|
||||
.flags = 0
|
||||
}
|
||||
};
|
||||
|
||||
static struct plat_serial8250_port serial_platform_data2[] = {
|
||||
{
|
||||
.membase = IO_ADDRESS(OMAP_UART3_BASE),
|
||||
.mapbase = OMAP_UART3_BASE,
|
||||
.irq = 74,
|
||||
|
@ -217,6 +229,40 @@ static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
|
|||
clk_disable(uart->fck);
|
||||
}
|
||||
|
||||
static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
|
||||
{
|
||||
/* Set wake-enable bit */
|
||||
if (uart->wk_en && uart->wk_mask) {
|
||||
u32 v = __raw_readl(uart->wk_en);
|
||||
v |= uart->wk_mask;
|
||||
__raw_writel(v, uart->wk_en);
|
||||
}
|
||||
|
||||
/* Ensure IOPAD wake-enables are set */
|
||||
if (cpu_is_omap34xx() && uart->padconf) {
|
||||
u16 v = omap_ctrl_readw(uart->padconf);
|
||||
v |= OMAP3_PADCONF_WAKEUPENABLE0;
|
||||
omap_ctrl_writew(v, uart->padconf);
|
||||
}
|
||||
}
|
||||
|
||||
static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
|
||||
{
|
||||
/* Clear wake-enable bit */
|
||||
if (uart->wk_en && uart->wk_mask) {
|
||||
u32 v = __raw_readl(uart->wk_en);
|
||||
v &= ~uart->wk_mask;
|
||||
__raw_writel(v, uart->wk_en);
|
||||
}
|
||||
|
||||
/* Ensure IOPAD wake-enables are cleared */
|
||||
if (cpu_is_omap34xx() && uart->padconf) {
|
||||
u16 v = omap_ctrl_readw(uart->padconf);
|
||||
v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
|
||||
omap_ctrl_writew(v, uart->padconf);
|
||||
}
|
||||
}
|
||||
|
||||
static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
|
||||
int enable)
|
||||
{
|
||||
|
@ -246,6 +292,11 @@ static void omap_uart_block_sleep(struct omap_uart_state *uart)
|
|||
|
||||
static void omap_uart_allow_sleep(struct omap_uart_state *uart)
|
||||
{
|
||||
if (device_may_wakeup(&uart->pdev.dev))
|
||||
omap_uart_enable_wakeup(uart);
|
||||
else
|
||||
omap_uart_disable_wakeup(uart);
|
||||
|
||||
if (!uart->clocked)
|
||||
return;
|
||||
|
||||
|
@ -292,7 +343,6 @@ void omap_uart_resume_idle(int num)
|
|||
/* Check for normal UART wakeup */
|
||||
if (__raw_readl(uart->wk_st) & uart->wk_mask)
|
||||
omap_uart_block_sleep(uart);
|
||||
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
@ -346,16 +396,13 @@ static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
|
|||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
static u32 sleep_timeout = DEFAULT_TIMEOUT;
|
||||
|
||||
static void omap_uart_idle_init(struct omap_uart_state *uart)
|
||||
{
|
||||
u32 v;
|
||||
struct plat_serial8250_port *p = uart->p;
|
||||
int ret;
|
||||
|
||||
uart->can_sleep = 0;
|
||||
uart->timeout = sleep_timeout;
|
||||
uart->timeout = DEFAULT_TIMEOUT;
|
||||
setup_timer(&uart->timer, omap_uart_idle_timer,
|
||||
(unsigned long) uart);
|
||||
mod_timer(&uart->timer, jiffies + uart->timeout);
|
||||
|
@ -413,76 +460,101 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
|
|||
uart->padconf = 0;
|
||||
}
|
||||
|
||||
/* Set wake-enable bit */
|
||||
if (uart->wk_en && uart->wk_mask) {
|
||||
v = __raw_readl(uart->wk_en);
|
||||
v |= uart->wk_mask;
|
||||
__raw_writel(v, uart->wk_en);
|
||||
}
|
||||
|
||||
/* Ensure IOPAD wake-enables are set */
|
||||
if (cpu_is_omap34xx() && uart->padconf) {
|
||||
u16 v;
|
||||
|
||||
v = omap_ctrl_readw(uart->padconf);
|
||||
v |= OMAP3_PADCONF_WAKEUPENABLE0;
|
||||
omap_ctrl_writew(v, uart->padconf);
|
||||
}
|
||||
|
||||
p->flags |= UPF_SHARE_IRQ;
|
||||
ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
|
||||
"serial idle", (void *)uart);
|
||||
WARN_ON(ret);
|
||||
}
|
||||
|
||||
static ssize_t sleep_timeout_show(struct kobject *kobj,
|
||||
struct kobj_attribute *attr,
|
||||
char *buf)
|
||||
void omap_uart_enable_irqs(int enable)
|
||||
{
|
||||
return sprintf(buf, "%u\n", sleep_timeout / HZ);
|
||||
int ret;
|
||||
struct omap_uart_state *uart;
|
||||
|
||||
list_for_each_entry(uart, &uart_list, node) {
|
||||
if (enable)
|
||||
ret = request_irq(uart->p->irq, omap_uart_interrupt,
|
||||
IRQF_SHARED, "serial idle", (void *)uart);
|
||||
else
|
||||
free_irq(uart->p->irq, (void *)uart);
|
||||
}
|
||||
}
|
||||
|
||||
static ssize_t sleep_timeout_store(struct kobject *kobj,
|
||||
struct kobj_attribute *attr,
|
||||
static ssize_t sleep_timeout_show(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
struct platform_device *pdev = container_of(dev,
|
||||
struct platform_device, dev);
|
||||
struct omap_uart_state *uart = container_of(pdev,
|
||||
struct omap_uart_state, pdev);
|
||||
|
||||
return sprintf(buf, "%u\n", uart->timeout / HZ);
|
||||
}
|
||||
|
||||
static ssize_t sleep_timeout_store(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
const char *buf, size_t n)
|
||||
{
|
||||
struct omap_uart_state *uart;
|
||||
struct platform_device *pdev = container_of(dev,
|
||||
struct platform_device, dev);
|
||||
struct omap_uart_state *uart = container_of(pdev,
|
||||
struct omap_uart_state, pdev);
|
||||
unsigned int value;
|
||||
|
||||
if (sscanf(buf, "%u", &value) != 1) {
|
||||
printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
sleep_timeout = value * HZ;
|
||||
list_for_each_entry(uart, &uart_list, node) {
|
||||
uart->timeout = sleep_timeout;
|
||||
if (uart->timeout)
|
||||
mod_timer(&uart->timer, jiffies + uart->timeout);
|
||||
else
|
||||
/* A zero value means disable timeout feature */
|
||||
omap_uart_block_sleep(uart);
|
||||
}
|
||||
|
||||
uart->timeout = value * HZ;
|
||||
if (uart->timeout)
|
||||
mod_timer(&uart->timer, jiffies + uart->timeout);
|
||||
else
|
||||
/* A zero value means disable timeout feature */
|
||||
omap_uart_block_sleep(uart);
|
||||
|
||||
return n;
|
||||
}
|
||||
|
||||
static struct kobj_attribute sleep_timeout_attr =
|
||||
__ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
|
||||
|
||||
DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
|
||||
#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
|
||||
#else
|
||||
static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
|
||||
#define DEV_CREATE_FILE(dev, attr)
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
static struct platform_device serial_device = {
|
||||
.name = "serial8250",
|
||||
.id = PLAT8250_DEV_PLATFORM,
|
||||
.dev = {
|
||||
.platform_data = serial_platform_data,
|
||||
static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = {
|
||||
{
|
||||
.pdev = {
|
||||
.name = "serial8250",
|
||||
.id = PLAT8250_DEV_PLATFORM,
|
||||
.dev = {
|
||||
.platform_data = serial_platform_data0,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.pdev = {
|
||||
.name = "serial8250",
|
||||
.id = PLAT8250_DEV_PLATFORM1,
|
||||
.dev = {
|
||||
.platform_data = serial_platform_data1,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.pdev = {
|
||||
.name = "serial8250",
|
||||
.id = PLAT8250_DEV_PLATFORM2,
|
||||
.dev = {
|
||||
.platform_data = serial_platform_data2,
|
||||
},
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
void __init omap_serial_init(void)
|
||||
{
|
||||
int i, err;
|
||||
int i;
|
||||
const struct omap_uart_config *info;
|
||||
char name[16];
|
||||
|
||||
|
@ -496,14 +568,12 @@ void __init omap_serial_init(void)
|
|||
|
||||
if (info == NULL)
|
||||
return;
|
||||
if (cpu_is_omap44xx()) {
|
||||
for (i = 0; i < OMAP_MAX_NR_PORTS; i++)
|
||||
serial_platform_data[i].irq += 32;
|
||||
}
|
||||
|
||||
for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
|
||||
struct plat_serial8250_port *p = serial_platform_data + i;
|
||||
struct omap_uart_state *uart = &omap_uart[i];
|
||||
struct platform_device *pdev = &uart->pdev;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct plat_serial8250_port *p = dev->platform_data;
|
||||
|
||||
if (!(info->enabled_uarts & (1 << i))) {
|
||||
p->membase = NULL;
|
||||
|
@ -531,20 +601,21 @@ void __init omap_serial_init(void)
|
|||
uart->num = i;
|
||||
p->private_data = uart;
|
||||
uart->p = p;
|
||||
list_add(&uart->node, &uart_list);
|
||||
list_add_tail(&uart->node, &uart_list);
|
||||
|
||||
if (cpu_is_omap44xx())
|
||||
p->irq += 32;
|
||||
|
||||
omap_uart_enable_clocks(uart);
|
||||
omap_uart_reset(uart);
|
||||
omap_uart_idle_init(uart);
|
||||
|
||||
if (WARN_ON(platform_device_register(pdev)))
|
||||
continue;
|
||||
if ((cpu_is_omap34xx() && uart->padconf) ||
|
||||
(uart->wk_en && uart->wk_mask)) {
|
||||
device_init_wakeup(dev, true);
|
||||
DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
|
||||
}
|
||||
}
|
||||
|
||||
err = platform_device_register(&serial_device);
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
if (!err)
|
||||
err = sysfs_create_file(&serial_device.dev.kobj,
|
||||
&sleep_timeout_attr.attr);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
|
|
@ -36,7 +36,7 @@
|
|||
|
||||
.text
|
||||
|
||||
/* r4 parameters */
|
||||
/* r1 parameters */
|
||||
#define SDRC_NO_UNLOCK_DLL 0x0
|
||||
#define SDRC_UNLOCK_DLL 0x1
|
||||
|
||||
|
@ -58,7 +58,6 @@
|
|||
|
||||
/* SDRC_POWER bit settings */
|
||||
#define SRFRONIDLEREQ_MASK 0x40
|
||||
#define PWDENA_MASK 0x4
|
||||
|
||||
/* CM_IDLEST1_CORE bit settings */
|
||||
#define ST_SDRC_MASK 0x2
|
||||
|
@ -71,41 +70,72 @@
|
|||
|
||||
/*
|
||||
* omap3_sram_configure_core_dpll - change DPLL3 M2 divider
|
||||
* r0 = new SDRC_RFR_CTRL register contents
|
||||
* r1 = new SDRC_ACTIM_CTRLA register contents
|
||||
* r2 = new SDRC_ACTIM_CTRLB register contents
|
||||
* r3 = new M2 divider setting (only 1 and 2 supported right now)
|
||||
* r4 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
|
||||
* SDRC rates < 83MHz
|
||||
* r5 = number of MPU cycles to wait for SDRC to stabilize after
|
||||
* reprogramming the SDRC when switching to a slower MPU speed
|
||||
* r6 = new SDRC_MR_0 register value
|
||||
* r7 = increasing SDRC rate? (1 = yes, 0 = no)
|
||||
*
|
||||
* Params passed in registers:
|
||||
* r0 = new M2 divider setting (only 1 and 2 supported right now)
|
||||
* r1 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
|
||||
* SDRC rates < 83MHz
|
||||
* r2 = number of MPU cycles to wait for SDRC to stabilize after
|
||||
* reprogramming the SDRC when switching to a slower MPU speed
|
||||
* r3 = increasing SDRC rate? (1 = yes, 0 = no)
|
||||
*
|
||||
* Params passed via the stack. The needed params will be copied in SRAM
|
||||
* before use by the code in SRAM (SDRAM is not accessible during SDRC
|
||||
* reconfiguration):
|
||||
* new SDRC_RFR_CTRL_0 register contents
|
||||
* new SDRC_ACTIM_CTRL_A_0 register contents
|
||||
* new SDRC_ACTIM_CTRL_B_0 register contents
|
||||
* new SDRC_MR_0 register value
|
||||
* new SDRC_RFR_CTRL_1 register contents
|
||||
* new SDRC_ACTIM_CTRL_A_1 register contents
|
||||
* new SDRC_ACTIM_CTRL_B_1 register contents
|
||||
* new SDRC_MR_1 register value
|
||||
*
|
||||
* If the param SDRC_RFR_CTRL_1 is 0, the parameters
|
||||
* are not programmed into the SDRC CS1 registers
|
||||
*/
|
||||
ENTRY(omap3_sram_configure_core_dpll)
|
||||
stmfd sp!, {r1-r12, lr} @ store regs to stack
|
||||
ldr r4, [sp, #52] @ pull extra args off the stack
|
||||
ldr r5, [sp, #56] @ load extra args from the stack
|
||||
ldr r6, [sp, #60] @ load extra args from the stack
|
||||
ldr r7, [sp, #64] @ load extra args from the stack
|
||||
|
||||
@ pull the extra args off the stack
|
||||
@ and store them in SRAM
|
||||
ldr r4, [sp, #52]
|
||||
str r4, omap_sdrc_rfr_ctrl_0_val
|
||||
ldr r4, [sp, #56]
|
||||
str r4, omap_sdrc_actim_ctrl_a_0_val
|
||||
ldr r4, [sp, #60]
|
||||
str r4, omap_sdrc_actim_ctrl_b_0_val
|
||||
ldr r4, [sp, #64]
|
||||
str r4, omap_sdrc_mr_0_val
|
||||
ldr r4, [sp, #68]
|
||||
str r4, omap_sdrc_rfr_ctrl_1_val
|
||||
cmp r4, #0 @ if SDRC_RFR_CTRL_1 is 0,
|
||||
beq skip_cs1_params @ do not use cs1 params
|
||||
ldr r4, [sp, #72]
|
||||
str r4, omap_sdrc_actim_ctrl_a_1_val
|
||||
ldr r4, [sp, #76]
|
||||
str r4, omap_sdrc_actim_ctrl_b_1_val
|
||||
ldr r4, [sp, #80]
|
||||
str r4, omap_sdrc_mr_1_val
|
||||
skip_cs1_params:
|
||||
dsb @ flush buffered writes to interconnect
|
||||
cmp r7, #1 @ if increasing SDRC clk rate,
|
||||
|
||||
cmp r3, #1 @ if increasing SDRC clk rate,
|
||||
bleq configure_sdrc @ program the SDRC regs early (for RFR)
|
||||
cmp r4, #SDRC_UNLOCK_DLL @ set the intended DLL state
|
||||
cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state
|
||||
bleq unlock_dll
|
||||
blne lock_dll
|
||||
bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
|
||||
bl configure_core_dpll @ change the DPLL3 M2 divider
|
||||
mov r12, r2
|
||||
bl wait_clk_stable @ wait for SDRC to stabilize
|
||||
bl enable_sdrc @ take SDRC out of idle
|
||||
cmp r4, #SDRC_UNLOCK_DLL @ wait for DLL status to change
|
||||
cmp r1, #SDRC_UNLOCK_DLL @ wait for DLL status to change
|
||||
bleq wait_dll_unlock
|
||||
blne wait_dll_lock
|
||||
cmp r7, #1 @ if increasing SDRC clk rate,
|
||||
cmp r3, #1 @ if increasing SDRC clk rate,
|
||||
beq return_to_sdram @ return to SDRAM code, otherwise,
|
||||
bl configure_sdrc @ reprogram SDRC regs now
|
||||
mov r12, r5
|
||||
bl wait_clk_stable @ wait for SDRC to stabilize
|
||||
return_to_sdram:
|
||||
isb @ prevent speculative exec past here
|
||||
mov r0, #0 @ return value
|
||||
|
@ -113,7 +143,7 @@ return_to_sdram:
|
|||
unlock_dll:
|
||||
ldr r11, omap3_sdrc_dlla_ctrl
|
||||
ldr r12, [r11]
|
||||
and r12, r12, #FIXEDDELAY_MASK
|
||||
bic r12, r12, #FIXEDDELAY_MASK
|
||||
orr r12, r12, #FIXEDDELAY_DEFAULT
|
||||
orr r12, r12, #DLLIDLE_MASK
|
||||
str r12, [r11] @ (no OCP barrier needed)
|
||||
|
@ -129,7 +159,6 @@ sdram_in_selfrefresh:
|
|||
ldr r12, [r11] @ read the contents of SDRC_POWER
|
||||
mov r9, r12 @ keep a copy of SDRC_POWER bits
|
||||
orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
|
||||
bic r12, r12, #PWDENA_MASK @ clear PWDENA
|
||||
str r12, [r11] @ write back to SDRC_POWER register
|
||||
ldr r12, [r11] @ posted-write barrier for SDRC
|
||||
idle_sdrc:
|
||||
|
@ -149,7 +178,7 @@ configure_core_dpll:
|
|||
ldr r12, [r11]
|
||||
ldr r10, core_m2_mask_val @ modify m2 for core dpll
|
||||
and r12, r12, r10
|
||||
orr r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
|
||||
orr r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
|
||||
str r12, [r11]
|
||||
ldr r12, [r11] @ posted-write barrier for CM
|
||||
bx lr
|
||||
|
@ -187,15 +216,34 @@ wait_dll_unlock:
|
|||
bne wait_dll_unlock
|
||||
bx lr
|
||||
configure_sdrc:
|
||||
ldr r11, omap3_sdrc_rfr_ctrl
|
||||
str r0, [r11]
|
||||
ldr r11, omap3_sdrc_actim_ctrla
|
||||
str r1, [r11]
|
||||
ldr r11, omap3_sdrc_actim_ctrlb
|
||||
str r2, [r11]
|
||||
ldr r12, omap_sdrc_rfr_ctrl_0_val @ fetch value from SRAM
|
||||
ldr r11, omap3_sdrc_rfr_ctrl_0 @ fetch addr from SRAM
|
||||
str r12, [r11] @ store
|
||||
ldr r12, omap_sdrc_actim_ctrl_a_0_val
|
||||
ldr r11, omap3_sdrc_actim_ctrl_a_0
|
||||
str r12, [r11]
|
||||
ldr r12, omap_sdrc_actim_ctrl_b_0_val
|
||||
ldr r11, omap3_sdrc_actim_ctrl_b_0
|
||||
str r12, [r11]
|
||||
ldr r12, omap_sdrc_mr_0_val
|
||||
ldr r11, omap3_sdrc_mr_0
|
||||
str r6, [r11]
|
||||
ldr r6, [r11] @ posted-write barrier for SDRC
|
||||
str r12, [r11]
|
||||
ldr r12, omap_sdrc_rfr_ctrl_1_val
|
||||
cmp r12, #0 @ if SDRC_RFR_CTRL_1 is 0,
|
||||
beq skip_cs1_prog @ do not program cs1 params
|
||||
ldr r11, omap3_sdrc_rfr_ctrl_1
|
||||
str r12, [r11]
|
||||
ldr r12, omap_sdrc_actim_ctrl_a_1_val
|
||||
ldr r11, omap3_sdrc_actim_ctrl_a_1
|
||||
str r12, [r11]
|
||||
ldr r12, omap_sdrc_actim_ctrl_b_1_val
|
||||
ldr r11, omap3_sdrc_actim_ctrl_b_1
|
||||
str r12, [r11]
|
||||
ldr r12, omap_sdrc_mr_1_val
|
||||
ldr r11, omap3_sdrc_mr_1
|
||||
str r12, [r11]
|
||||
skip_cs1_prog:
|
||||
ldr r12, [r11] @ posted-write barrier for SDRC
|
||||
bx lr
|
||||
|
||||
omap3_sdrc_power:
|
||||
|
@ -206,14 +254,40 @@ omap3_cm_idlest1_core:
|
|||
.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
|
||||
omap3_cm_iclken1_core:
|
||||
.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
|
||||
omap3_sdrc_rfr_ctrl:
|
||||
|
||||
omap3_sdrc_rfr_ctrl_0:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
|
||||
omap3_sdrc_actim_ctrla:
|
||||
omap3_sdrc_rfr_ctrl_1:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
|
||||
omap3_sdrc_actim_ctrl_a_0:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
|
||||
omap3_sdrc_actim_ctrlb:
|
||||
omap3_sdrc_actim_ctrl_a_1:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
|
||||
omap3_sdrc_actim_ctrl_b_0:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
|
||||
omap3_sdrc_actim_ctrl_b_1:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
|
||||
omap3_sdrc_mr_0:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
|
||||
omap3_sdrc_mr_1:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
|
||||
omap_sdrc_rfr_ctrl_0_val:
|
||||
.word 0xDEADBEEF
|
||||
omap_sdrc_rfr_ctrl_1_val:
|
||||
.word 0xDEADBEEF
|
||||
omap_sdrc_actim_ctrl_a_0_val:
|
||||
.word 0xDEADBEEF
|
||||
omap_sdrc_actim_ctrl_a_1_val:
|
||||
.word 0xDEADBEEF
|
||||
omap_sdrc_actim_ctrl_b_0_val:
|
||||
.word 0xDEADBEEF
|
||||
omap_sdrc_actim_ctrl_b_1_val:
|
||||
.word 0xDEADBEEF
|
||||
omap_sdrc_mr_0_val:
|
||||
.word 0xDEADBEEF
|
||||
omap_sdrc_mr_1_val:
|
||||
.word 0xDEADBEEF
|
||||
|
||||
omap3_sdrc_dlla_status:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
|
||||
omap3_sdrc_dlla_ctrl:
|
||||
|
@ -223,3 +297,4 @@ core_m2_mask_val:
|
|||
|
||||
ENTRY(omap3_sram_configure_core_dpll_sz)
|
||||
.word . - omap3_sram_configure_core_dpll
|
||||
|
||||
|
|
|
@ -155,20 +155,6 @@ static struct platform_device musb_device = {
|
|||
.resource = musb_resources,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_NOP_USB_XCEIV
|
||||
static u64 nop_xceiv_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
static struct platform_device nop_xceiv_device = {
|
||||
.name = "nop_usb_xceiv",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.dma_mask = &nop_xceiv_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
.platform_data = NULL,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
void __init usb_musb_init(void)
|
||||
{
|
||||
if (cpu_is_omap243x())
|
||||
|
@ -183,13 +169,6 @@ void __init usb_musb_init(void)
|
|||
*/
|
||||
musb_plat.clock = "ick";
|
||||
|
||||
#ifdef CONFIG_NOP_USB_XCEIV
|
||||
if (platform_device_register(&nop_xceiv_device) < 0) {
|
||||
printk(KERN_ERR "Unable to register NOP-XCEIV device\n");
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (platform_device_register(&musb_device) < 0) {
|
||||
printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n");
|
||||
return;
|
||||
|
|
|
@ -1141,12 +1141,16 @@ struct power_supply_info em_x270_psy_info = {
|
|||
|
||||
static void em_x270_battery_low(void)
|
||||
{
|
||||
#if defined(CONFIG_APM_EMULATION)
|
||||
apm_queue_event(APM_LOW_BATTERY);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void em_x270_battery_critical(void)
|
||||
{
|
||||
#if defined(CONFIG_APM_EMULATION)
|
||||
apm_queue_event(APM_CRITICAL_SUSPEND);
|
||||
#endif
|
||||
}
|
||||
|
||||
struct da9030_battery_info em_x270_batterty_info = {
|
||||
|
|
|
@ -128,6 +128,10 @@ static unsigned long palmld_pin_config[] __initdata = {
|
|||
GPIO38_GPIO, /* wifi ready */
|
||||
GPIO81_GPIO, /* wifi reset */
|
||||
|
||||
/* FFUART */
|
||||
GPIO34_FFUART_RXD,
|
||||
GPIO39_FFUART_TXD,
|
||||
|
||||
/* HDD */
|
||||
GPIO98_GPIO, /* HDD reset */
|
||||
GPIO115_GPIO, /* HDD power */
|
||||
|
|
|
@ -111,6 +111,10 @@ static unsigned long palmt5_pin_config[] __initdata = {
|
|||
/* PWM */
|
||||
GPIO16_PWM0_OUT,
|
||||
|
||||
/* FFUART */
|
||||
GPIO34_FFUART_RXD,
|
||||
GPIO39_FFUART_TXD,
|
||||
|
||||
/* MISC */
|
||||
GPIO10_GPIO, /* hotsync button */
|
||||
GPIO90_GPIO, /* power detect */
|
||||
|
|
|
@ -127,6 +127,10 @@ static unsigned long palmtx_pin_config[] __initdata = {
|
|||
GPIO76_LCD_PCLK,
|
||||
GPIO77_LCD_BIAS,
|
||||
|
||||
/* FFUART */
|
||||
GPIO34_FFUART_RXD,
|
||||
GPIO39_FFUART_TXD,
|
||||
|
||||
/* MISC. */
|
||||
GPIO10_GPIO, /* hotsync button */
|
||||
GPIO12_GPIO, /* power detect */
|
||||
|
|
|
@ -409,7 +409,7 @@ err1:
|
|||
|
||||
static void treo680_irda_shutdown(struct device *dev)
|
||||
{
|
||||
gpio_free(GPIO_NR_TREO680_AMP_EN);
|
||||
gpio_free(GPIO_NR_TREO680_IR_EN);
|
||||
}
|
||||
|
||||
static struct pxaficp_platform_data treo680_ficp_info = {
|
||||
|
|
|
@ -197,10 +197,12 @@ static void __init zylonite_detect_lcd_panel(void)
|
|||
for (i = 0; i < NUM_LCD_DETECT_PINS; i++) {
|
||||
id = id << 1;
|
||||
gpio = mfp_to_gpio(lcd_detect_pins[i]);
|
||||
gpio_request(gpio, "LCD_ID_PINS");
|
||||
gpio_direction_input(gpio);
|
||||
|
||||
if (gpio_get_value(gpio))
|
||||
id = id | 0x1;
|
||||
gpio_free(gpio);
|
||||
}
|
||||
|
||||
/* lcd id, flush out bit 1 */
|
||||
|
|
|
@ -176,10 +176,12 @@ static void __init zylonite_detect_lcd_panel(void)
|
|||
for (i = 0; i < NUM_LCD_DETECT_PINS; i++) {
|
||||
id = id << 1;
|
||||
gpio = mfp_to_gpio(lcd_detect_pins[i]);
|
||||
gpio_request(gpio, "LCD_ID_PINS");
|
||||
gpio_direction_input(gpio);
|
||||
|
||||
if (gpio_get_value(gpio))
|
||||
id = id | 0x1;
|
||||
gpio_free(gpio);
|
||||
}
|
||||
|
||||
/* lcd id, flush out bit 1 */
|
||||
|
|
|
@ -28,7 +28,7 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin)
|
|||
return NULL;
|
||||
|
||||
chip = &s3c24xx_gpios[pin/32];
|
||||
return (S3C2410_GPIO_OFFSET(pin) > chip->chip.ngpio) ? chip : NULL;
|
||||
return (S3C2410_GPIO_OFFSET(pin) < chip->chip.ngpio) ? chip : NULL;
|
||||
}
|
||||
|
||||
#endif /* __ASM_ARCH_GPIO_CORE_H */
|
||||
|
|
|
@ -510,7 +510,7 @@ static struct db_chip db_chips[] __initdata = {
|
|||
}
|
||||
};
|
||||
|
||||
static void u300_init_check_chip(void)
|
||||
static void __init u300_init_check_chip(void)
|
||||
{
|
||||
|
||||
u16 val;
|
||||
|
|
|
@ -120,6 +120,32 @@ void show_mem(void)
|
|||
printk("%d pages swap cached\n", cached);
|
||||
}
|
||||
|
||||
static void __init find_node_limits(int node, struct meminfo *mi,
|
||||
unsigned long *min, unsigned long *max_low, unsigned long *max_high)
|
||||
{
|
||||
int i;
|
||||
|
||||
*min = -1UL;
|
||||
*max_low = *max_high = 0;
|
||||
|
||||
for_each_nodebank(i, mi, node) {
|
||||
struct membank *bank = &mi->bank[i];
|
||||
unsigned long start, end;
|
||||
|
||||
start = bank_pfn_start(bank);
|
||||
end = bank_pfn_end(bank);
|
||||
|
||||
if (*min > start)
|
||||
*min = start;
|
||||
if (*max_high < end)
|
||||
*max_high = end;
|
||||
if (bank->highmem)
|
||||
continue;
|
||||
if (*max_low < end)
|
||||
*max_low = end;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* FIXME: We really want to avoid allocating the bootmap bitmap
|
||||
* over the top of the initrd. Hopefully, this is located towards
|
||||
|
@ -210,40 +236,24 @@ static inline void map_memory_bank(struct membank *bank)
|
|||
#endif
|
||||
}
|
||||
|
||||
static unsigned long __init bootmem_init_node(int node, struct meminfo *mi)
|
||||
static void __init bootmem_init_node(int node, struct meminfo *mi,
|
||||
unsigned long start_pfn, unsigned long end_pfn)
|
||||
{
|
||||
unsigned long start_pfn, end_pfn, boot_pfn;
|
||||
unsigned long boot_pfn;
|
||||
unsigned int boot_pages;
|
||||
pg_data_t *pgdat;
|
||||
int i;
|
||||
|
||||
start_pfn = -1UL;
|
||||
end_pfn = 0;
|
||||
|
||||
/*
|
||||
* Calculate the pfn range, and map the memory banks for this node.
|
||||
* Map the memory banks for this node.
|
||||
*/
|
||||
for_each_nodebank(i, mi, node) {
|
||||
struct membank *bank = &mi->bank[i];
|
||||
unsigned long start, end;
|
||||
|
||||
start = bank_pfn_start(bank);
|
||||
end = bank_pfn_end(bank);
|
||||
|
||||
if (start_pfn > start)
|
||||
start_pfn = start;
|
||||
if (end_pfn < end)
|
||||
end_pfn = end;
|
||||
|
||||
map_memory_bank(bank);
|
||||
if (!bank->highmem)
|
||||
map_memory_bank(bank);
|
||||
}
|
||||
|
||||
/*
|
||||
* If there is no memory in this node, ignore it.
|
||||
*/
|
||||
if (end_pfn == 0)
|
||||
return end_pfn;
|
||||
|
||||
/*
|
||||
* Allocate the bootmem bitmap page.
|
||||
*/
|
||||
|
@ -260,7 +270,8 @@ static unsigned long __init bootmem_init_node(int node, struct meminfo *mi)
|
|||
|
||||
for_each_nodebank(i, mi, node) {
|
||||
struct membank *bank = &mi->bank[i];
|
||||
free_bootmem_node(pgdat, bank_phys_start(bank), bank_phys_size(bank));
|
||||
if (!bank->highmem)
|
||||
free_bootmem_node(pgdat, bank_phys_start(bank), bank_phys_size(bank));
|
||||
memory_present(node, bank_pfn_start(bank), bank_pfn_end(bank));
|
||||
}
|
||||
|
||||
|
@ -269,8 +280,6 @@ static unsigned long __init bootmem_init_node(int node, struct meminfo *mi)
|
|||
*/
|
||||
reserve_bootmem_node(pgdat, boot_pfn << PAGE_SHIFT,
|
||||
boot_pages << PAGE_SHIFT, BOOTMEM_DEFAULT);
|
||||
|
||||
return end_pfn;
|
||||
}
|
||||
|
||||
static void __init bootmem_reserve_initrd(int node)
|
||||
|
@ -297,33 +306,39 @@ static void __init bootmem_reserve_initrd(int node)
|
|||
static void __init bootmem_free_node(int node, struct meminfo *mi)
|
||||
{
|
||||
unsigned long zone_size[MAX_NR_ZONES], zhole_size[MAX_NR_ZONES];
|
||||
unsigned long start_pfn, end_pfn;
|
||||
pg_data_t *pgdat = NODE_DATA(node);
|
||||
unsigned long min, max_low, max_high;
|
||||
int i;
|
||||
|
||||
start_pfn = pgdat->bdata->node_min_pfn;
|
||||
end_pfn = pgdat->bdata->node_low_pfn;
|
||||
find_node_limits(node, mi, &min, &max_low, &max_high);
|
||||
|
||||
/*
|
||||
* initialise the zones within this node.
|
||||
*/
|
||||
memset(zone_size, 0, sizeof(zone_size));
|
||||
memset(zhole_size, 0, sizeof(zhole_size));
|
||||
|
||||
/*
|
||||
* The size of this node has already been determined. If we need
|
||||
* to do anything fancy with the allocation of this memory to the
|
||||
* zones, now is the time to do it.
|
||||
*/
|
||||
zone_size[0] = end_pfn - start_pfn;
|
||||
zone_size[0] = max_low - min;
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
zone_size[ZONE_HIGHMEM] = max_high - max_low;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* For each bank in this node, calculate the size of the holes.
|
||||
* holes = node_size - sum(bank_sizes_in_node)
|
||||
*/
|
||||
zhole_size[0] = zone_size[0];
|
||||
for_each_nodebank(i, mi, node)
|
||||
zhole_size[0] -= bank_pfn_size(&mi->bank[i]);
|
||||
memcpy(zhole_size, zone_size, sizeof(zhole_size));
|
||||
for_each_nodebank(i, mi, node) {
|
||||
int idx = 0;
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
if (mi->bank[i].highmem)
|
||||
idx = ZONE_HIGHMEM;
|
||||
#endif
|
||||
zhole_size[idx] -= bank_pfn_size(&mi->bank[i]);
|
||||
}
|
||||
|
||||
/*
|
||||
* Adjust the sizes according to any special requirements for
|
||||
|
@ -331,13 +346,13 @@ static void __init bootmem_free_node(int node, struct meminfo *mi)
|
|||
*/
|
||||
arch_adjust_zones(node, zone_size, zhole_size);
|
||||
|
||||
free_area_init_node(node, zone_size, start_pfn, zhole_size);
|
||||
free_area_init_node(node, zone_size, min, zhole_size);
|
||||
}
|
||||
|
||||
void __init bootmem_init(void)
|
||||
{
|
||||
struct meminfo *mi = &meminfo;
|
||||
unsigned long memend_pfn = 0;
|
||||
unsigned long min, max_low, max_high;
|
||||
int node, initrd_node;
|
||||
|
||||
/*
|
||||
|
@ -345,11 +360,29 @@ void __init bootmem_init(void)
|
|||
*/
|
||||
initrd_node = check_initrd(mi);
|
||||
|
||||
max_low = max_high = 0;
|
||||
|
||||
/*
|
||||
* Run through each node initialising the bootmem allocator.
|
||||
*/
|
||||
for_each_node(node) {
|
||||
unsigned long end_pfn = bootmem_init_node(node, mi);
|
||||
unsigned long node_low, node_high;
|
||||
|
||||
find_node_limits(node, mi, &min, &node_low, &node_high);
|
||||
|
||||
if (node_low > max_low)
|
||||
max_low = node_low;
|
||||
if (node_high > max_high)
|
||||
max_high = node_high;
|
||||
|
||||
/*
|
||||
* If there is no memory in this node, ignore it.
|
||||
* (We can't have nodes which have no lowmem)
|
||||
*/
|
||||
if (node_low == 0)
|
||||
continue;
|
||||
|
||||
bootmem_init_node(node, mi, min, node_low);
|
||||
|
||||
/*
|
||||
* Reserve any special node zero regions.
|
||||
|
@ -362,12 +395,6 @@ void __init bootmem_init(void)
|
|||
*/
|
||||
if (node == initrd_node)
|
||||
bootmem_reserve_initrd(node);
|
||||
|
||||
/*
|
||||
* Remember the highest memory PFN.
|
||||
*/
|
||||
if (end_pfn > memend_pfn)
|
||||
memend_pfn = end_pfn;
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -383,7 +410,7 @@ void __init bootmem_init(void)
|
|||
for_each_node(node)
|
||||
bootmem_free_node(node, mi);
|
||||
|
||||
high_memory = __va((memend_pfn << PAGE_SHIFT) - 1) + 1;
|
||||
high_memory = __va((max_low << PAGE_SHIFT) - 1) + 1;
|
||||
|
||||
/*
|
||||
* This doesn't seem to be used by the Linux memory manager any
|
||||
|
@ -393,7 +420,8 @@ void __init bootmem_init(void)
|
|||
* Note: max_low_pfn and max_pfn reflect the number of _pages_ in
|
||||
* the system, not the maximum PFN.
|
||||
*/
|
||||
max_pfn = max_low_pfn = memend_pfn - PHYS_PFN_OFFSET;
|
||||
max_low_pfn = max_low - PHYS_PFN_OFFSET;
|
||||
max_pfn = max_high - PHYS_PFN_OFFSET;
|
||||
}
|
||||
|
||||
static inline int free_area(unsigned long pfn, unsigned long end, char *s)
|
||||
|
|
|
@ -687,13 +687,19 @@ __early_param("vmalloc=", early_vmalloc);
|
|||
|
||||
static void __init sanity_check_meminfo(void)
|
||||
{
|
||||
int i, j;
|
||||
int i, j, highmem = 0;
|
||||
|
||||
for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
|
||||
struct membank *bank = &meminfo.bank[j];
|
||||
*bank = meminfo.bank[i];
|
||||
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
if (__va(bank->start) > VMALLOC_MIN ||
|
||||
__va(bank->start) < (void *)PAGE_OFFSET)
|
||||
highmem = 1;
|
||||
|
||||
bank->highmem = highmem;
|
||||
|
||||
/*
|
||||
* Split those memory banks which are partially overlapping
|
||||
* the vmalloc area greatly simplifying things later.
|
||||
|
@ -714,6 +720,7 @@ static void __init sanity_check_meminfo(void)
|
|||
i++;
|
||||
bank[1].size -= VMALLOC_MIN - __va(bank->start);
|
||||
bank[1].start = __pa(VMALLOC_MIN - 1) + 1;
|
||||
bank[1].highmem = highmem = 1;
|
||||
j++;
|
||||
}
|
||||
bank->size = VMALLOC_MIN - __va(bank->start);
|
||||
|
|
|
@ -78,10 +78,10 @@ static int omap_target(struct cpufreq_policy *policy,
|
|||
|
||||
/* Ensure desired rate is within allowed range. Some govenors
|
||||
* (ondemand) will just pass target_freq=0 to get the minimum. */
|
||||
if (target_freq < policy->cpuinfo.min_freq)
|
||||
target_freq = policy->cpuinfo.min_freq;
|
||||
if (target_freq > policy->cpuinfo.max_freq)
|
||||
target_freq = policy->cpuinfo.max_freq;
|
||||
if (target_freq < policy->min)
|
||||
target_freq = policy->min;
|
||||
if (target_freq > policy->max)
|
||||
target_freq = policy->max;
|
||||
|
||||
freqs.old = omap_getspeed(0);
|
||||
freqs.new = clk_round_rate(mpu_clk, target_freq * 1000) / 1000;
|
||||
|
|
|
@ -946,7 +946,9 @@ void omap_start_dma(int lch)
|
|||
|
||||
cur_lch = next_lch;
|
||||
} while (next_lch != -1);
|
||||
} else if (cpu_class_is_omap2()) {
|
||||
} else if (cpu_is_omap242x() ||
|
||||
(cpu_is_omap243x() && omap_type() <= OMAP2430_REV_ES1_0)) {
|
||||
|
||||
/* Errata: Need to write lch even if not using chaining */
|
||||
dma_write(lch, CLNK_CTRL(lch));
|
||||
}
|
||||
|
|
|
@ -476,14 +476,12 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
|
|||
__raw_writel(l, reg);
|
||||
}
|
||||
|
||||
static int __omap_get_gpio_datain(int gpio)
|
||||
static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
|
||||
{
|
||||
struct gpio_bank *bank;
|
||||
void __iomem *reg;
|
||||
|
||||
if (check_gpio(gpio) < 0)
|
||||
return -EINVAL;
|
||||
bank = get_gpio_bank(gpio);
|
||||
reg = bank->base;
|
||||
switch (bank->method) {
|
||||
#ifdef CONFIG_ARCH_OMAP1
|
||||
|
@ -524,6 +522,53 @@ static int __omap_get_gpio_datain(int gpio)
|
|||
& (1 << get_gpio_index(gpio))) != 0;
|
||||
}
|
||||
|
||||
static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
|
||||
{
|
||||
void __iomem *reg;
|
||||
|
||||
if (check_gpio(gpio) < 0)
|
||||
return -EINVAL;
|
||||
reg = bank->base;
|
||||
|
||||
switch (bank->method) {
|
||||
#ifdef CONFIG_ARCH_OMAP1
|
||||
case METHOD_MPUIO:
|
||||
reg += OMAP_MPUIO_OUTPUT;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_OMAP15XX
|
||||
case METHOD_GPIO_1510:
|
||||
reg += OMAP1510_GPIO_DATA_OUTPUT;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_OMAP16XX
|
||||
case METHOD_GPIO_1610:
|
||||
reg += OMAP1610_GPIO_DATAOUT;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_OMAP730
|
||||
case METHOD_GPIO_730:
|
||||
reg += OMAP730_GPIO_DATA_OUTPUT;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_OMAP850
|
||||
case METHOD_GPIO_850:
|
||||
reg += OMAP850_GPIO_DATA_OUTPUT;
|
||||
break;
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
|
||||
defined(CONFIG_ARCH_OMAP4)
|
||||
case METHOD_GPIO_24XX:
|
||||
reg += OMAP24XX_GPIO_DATAOUT;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
|
||||
}
|
||||
|
||||
#define MOD_REG_BIT(reg, bit_mask, set) \
|
||||
do { \
|
||||
int l = __raw_readl(base + reg); \
|
||||
|
@ -1189,6 +1234,7 @@ static void gpio_mask_irq(unsigned int irq)
|
|||
struct gpio_bank *bank = get_irq_chip_data(irq);
|
||||
|
||||
_set_gpio_irqenable(bank, gpio, 0);
|
||||
_set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
|
||||
}
|
||||
|
||||
static void gpio_unmask_irq(unsigned int irq)
|
||||
|
@ -1196,6 +1242,11 @@ static void gpio_unmask_irq(unsigned int irq)
|
|||
unsigned int gpio = irq - IH_GPIO_BASE;
|
||||
struct gpio_bank *bank = get_irq_chip_data(irq);
|
||||
unsigned int irq_mask = 1 << get_gpio_index(gpio);
|
||||
struct irq_desc *desc = irq_to_desc(irq);
|
||||
u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
|
||||
|
||||
if (trigger)
|
||||
_set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
|
||||
|
||||
/* For level-triggered GPIOs, the clearing must be done after
|
||||
* the HW source is cleared, thus after the handler has run */
|
||||
|
@ -1350,9 +1401,49 @@ static int gpio_input(struct gpio_chip *chip, unsigned offset)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int gpio_is_input(struct gpio_bank *bank, int mask)
|
||||
{
|
||||
void __iomem *reg = bank->base;
|
||||
|
||||
switch (bank->method) {
|
||||
case METHOD_MPUIO:
|
||||
reg += OMAP_MPUIO_IO_CNTL;
|
||||
break;
|
||||
case METHOD_GPIO_1510:
|
||||
reg += OMAP1510_GPIO_DIR_CONTROL;
|
||||
break;
|
||||
case METHOD_GPIO_1610:
|
||||
reg += OMAP1610_GPIO_DIRECTION;
|
||||
break;
|
||||
case METHOD_GPIO_730:
|
||||
reg += OMAP730_GPIO_DIR_CONTROL;
|
||||
break;
|
||||
case METHOD_GPIO_850:
|
||||
reg += OMAP850_GPIO_DIR_CONTROL;
|
||||
break;
|
||||
case METHOD_GPIO_24XX:
|
||||
reg += OMAP24XX_GPIO_OE;
|
||||
break;
|
||||
}
|
||||
return __raw_readl(reg) & mask;
|
||||
}
|
||||
|
||||
static int gpio_get(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
return __omap_get_gpio_datain(chip->base + offset);
|
||||
struct gpio_bank *bank;
|
||||
void __iomem *reg;
|
||||
int gpio;
|
||||
u32 mask;
|
||||
|
||||
gpio = chip->base + offset;
|
||||
bank = get_gpio_bank(gpio);
|
||||
reg = bank->base;
|
||||
mask = 1 << get_gpio_index(gpio);
|
||||
|
||||
if (gpio_is_input(bank, mask))
|
||||
return _get_gpio_datain(bank, gpio);
|
||||
else
|
||||
return _get_gpio_dataout(bank, gpio);
|
||||
}
|
||||
|
||||
static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
|
||||
|
@ -1886,34 +1977,6 @@ arch_initcall(omap_gpio_sysinit);
|
|||
#include <linux/debugfs.h>
|
||||
#include <linux/seq_file.h>
|
||||
|
||||
static int gpio_is_input(struct gpio_bank *bank, int mask)
|
||||
{
|
||||
void __iomem *reg = bank->base;
|
||||
|
||||
switch (bank->method) {
|
||||
case METHOD_MPUIO:
|
||||
reg += OMAP_MPUIO_IO_CNTL;
|
||||
break;
|
||||
case METHOD_GPIO_1510:
|
||||
reg += OMAP1510_GPIO_DIR_CONTROL;
|
||||
break;
|
||||
case METHOD_GPIO_1610:
|
||||
reg += OMAP1610_GPIO_DIRECTION;
|
||||
break;
|
||||
case METHOD_GPIO_730:
|
||||
reg += OMAP730_GPIO_DIR_CONTROL;
|
||||
break;
|
||||
case METHOD_GPIO_850:
|
||||
reg += OMAP850_GPIO_DIR_CONTROL;
|
||||
break;
|
||||
case METHOD_GPIO_24XX:
|
||||
reg += OMAP24XX_GPIO_OE;
|
||||
break;
|
||||
}
|
||||
return __raw_readl(reg) & mask;
|
||||
}
|
||||
|
||||
|
||||
static int dbg_gpio_show(struct seq_file *s, void *unused)
|
||||
{
|
||||
unsigned i, j, gpio;
|
||||
|
|
|
@ -20,6 +20,8 @@ struct clockdomain;
|
|||
struct clkops {
|
||||
int (*enable)(struct clk *);
|
||||
void (*disable)(struct clk *);
|
||||
void (*find_idlest)(struct clk *, void __iomem **, u8 *);
|
||||
void (*find_companion)(struct clk *, void __iomem **, u8 *);
|
||||
};
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
|
||||
|
|
|
@ -378,9 +378,6 @@ IS_OMAP_TYPE(3430, 0x3430)
|
|||
#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \
|
||||
cpu_is_omap44xx())
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
|
||||
defined(CONFIG_ARCH_OMAP4)
|
||||
|
||||
/* Various silicon revisions for omap2 */
|
||||
#define OMAP242X_CLASS 0x24200024
|
||||
#define OMAP2420_REV_ES1_0 0x24200024
|
||||
|
@ -436,5 +433,3 @@ IS_OMAP_TYPE(3430, 0x3430)
|
|||
|
||||
int omap_chip_is(struct omap_chip_id oci);
|
||||
void omap2_check_revision(void);
|
||||
|
||||
#endif /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */
|
||||
|
|
|
@ -228,7 +228,8 @@ extern void omap1_map_common_io(void);
|
|||
extern void omap1_init_common_hw(void);
|
||||
|
||||
extern void omap2_map_common_io(void);
|
||||
extern void omap2_init_common_hw(struct omap_sdrc_params *sp);
|
||||
extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
|
||||
struct omap_sdrc_params *sdrc_cs1);
|
||||
|
||||
#define __arch_ioremap(p,s,t) omap_ioremap(p,s,t)
|
||||
#define __arch_iounmap(v) omap_iounmap(v)
|
||||
|
|
|
@ -853,6 +853,10 @@ enum omap34xx_index {
|
|||
AE5_34XX_GPIO143,
|
||||
H19_34XX_GPIO164_OUT,
|
||||
J25_34XX_GPIO170,
|
||||
|
||||
/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
|
||||
H16_34XX_SDRC_CKE0,
|
||||
H17_34XX_SDRC_CKE1,
|
||||
};
|
||||
|
||||
struct omap_mux_cfg {
|
||||
|
|
|
@ -25,6 +25,7 @@
|
|||
|
||||
u32 omap_prcm_get_reset_sources(void);
|
||||
void omap_prcm_arch_reset(char mode);
|
||||
int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name);
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
@ -30,6 +30,10 @@
|
|||
#define SDRC_ACTIM_CTRL_A_0 0x09c
|
||||
#define SDRC_ACTIM_CTRL_B_0 0x0a0
|
||||
#define SDRC_RFR_CTRL_0 0x0a4
|
||||
#define SDRC_MR_1 0x0B4
|
||||
#define SDRC_ACTIM_CTRL_A_1 0x0C4
|
||||
#define SDRC_ACTIM_CTRL_B_1 0x0C8
|
||||
#define SDRC_RFR_CTRL_1 0x0D4
|
||||
|
||||
/*
|
||||
* These values represent the number of memory clock cycles between
|
||||
|
@ -102,8 +106,11 @@ struct omap_sdrc_params {
|
|||
u32 mr;
|
||||
};
|
||||
|
||||
void __init omap2_sdrc_init(struct omap_sdrc_params *sp);
|
||||
struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r);
|
||||
void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
|
||||
struct omap_sdrc_params *sdrc_cs1);
|
||||
int omap2_sdrc_get_params(unsigned long r,
|
||||
struct omap_sdrc_params **sdrc_cs0,
|
||||
struct omap_sdrc_params **sdrc_cs1);
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP2
|
||||
|
||||
|
|
|
@ -59,6 +59,7 @@ extern void omap_uart_check_wakeup(void);
|
|||
extern void omap_uart_prepare_suspend(void);
|
||||
extern void omap_uart_prepare_idle(int num);
|
||||
extern void omap_uart_resume_idle(int num);
|
||||
extern void omap_uart_enable_irqs(int enable);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
@ -21,11 +21,12 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
|
|||
u32 mem_type);
|
||||
extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
|
||||
|
||||
extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
|
||||
u32 sdrc_actim_ctrla,
|
||||
u32 sdrc_actim_ctrlb, u32 m2,
|
||||
u32 unlock_dll, u32 f, u32 sdrc_mr,
|
||||
u32 inc);
|
||||
extern u32 omap3_configure_core_dpll(
|
||||
u32 m2, u32 unlock_dll, u32 f, u32 inc,
|
||||
u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
|
||||
u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
|
||||
u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
|
||||
u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
|
||||
|
||||
/* Do not use these */
|
||||
extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
|
||||
|
@ -59,12 +60,12 @@ extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
|
|||
u32 mem_type);
|
||||
extern unsigned long omap243x_sram_reprogram_sdrc_sz;
|
||||
|
||||
|
||||
extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
|
||||
u32 sdrc_actim_ctrla,
|
||||
u32 sdrc_actim_ctrlb, u32 m2,
|
||||
u32 unlock_dll, u32 f, u32 sdrc_mr,
|
||||
u32 inc);
|
||||
extern u32 omap3_sram_configure_core_dpll(
|
||||
u32 m2, u32 unlock_dll, u32 f, u32 inc,
|
||||
u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
|
||||
u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
|
||||
u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
|
||||
u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
|
||||
extern unsigned long omap3_sram_configure_core_dpll_sz;
|
||||
|
||||
#endif
|
||||
|
|
|
@ -44,9 +44,9 @@
|
|||
#define OMAP2_SRAM_VA 0xe3000000
|
||||
#define OMAP2_SRAM_PUB_VA (OMAP2_SRAM_VA + 0x800)
|
||||
#define OMAP3_SRAM_PA 0x40200000
|
||||
#define OMAP3_SRAM_VA 0xd7000000
|
||||
#define OMAP3_SRAM_VA 0xe3000000
|
||||
#define OMAP3_SRAM_PUB_PA 0x40208000
|
||||
#define OMAP3_SRAM_PUB_VA 0xd7008000
|
||||
#define OMAP3_SRAM_PUB_VA (OMAP3_SRAM_VA + 0x8000)
|
||||
#define OMAP4_SRAM_PA 0x40200000 /*0x402f0000*/
|
||||
#define OMAP4_SRAM_VA 0xd7000000 /*0xd70f0000*/
|
||||
|
||||
|
@ -373,20 +373,26 @@ static inline int omap243x_sram_init(void)
|
|||
|
||||
#ifdef CONFIG_ARCH_OMAP3
|
||||
|
||||
static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
|
||||
u32 sdrc_actim_ctrla,
|
||||
u32 sdrc_actim_ctrlb,
|
||||
u32 m2, u32 unlock_dll,
|
||||
u32 f, u32 sdrc_mr, u32 inc);
|
||||
u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
|
||||
u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
|
||||
u32 f, u32 sdrc_mr, u32 inc)
|
||||
static u32 (*_omap3_sram_configure_core_dpll)(
|
||||
u32 m2, u32 unlock_dll, u32 f, u32 inc,
|
||||
u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
|
||||
u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
|
||||
u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
|
||||
u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
|
||||
|
||||
u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
|
||||
u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
|
||||
u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
|
||||
u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
|
||||
u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
|
||||
{
|
||||
BUG_ON(!_omap3_sram_configure_core_dpll);
|
||||
return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
|
||||
sdrc_actim_ctrla,
|
||||
sdrc_actim_ctrlb, m2,
|
||||
unlock_dll, f, sdrc_mr, inc);
|
||||
return _omap3_sram_configure_core_dpll(
|
||||
m2, unlock_dll, f, inc,
|
||||
sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
|
||||
sdrc_actim_ctrl_b_0, sdrc_mr_0,
|
||||
sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
|
||||
sdrc_actim_ctrl_b_1, sdrc_mr_1);
|
||||
}
|
||||
|
||||
/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
|
||||
|
|
|
@ -11,6 +11,8 @@
|
|||
#ifndef __PLAT_GPIO_H
|
||||
#define __PLAT_GPIO_H
|
||||
|
||||
#include <linux/init.h>
|
||||
|
||||
/*
|
||||
* GENERIC_GPIO primitives.
|
||||
*/
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue