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ARM: ux500: Enable PL310 Level 2 Cache Controller in Device Tree

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This provides PL310 Level 2 Cache Controller Device Tree
support for all u8500 based devices.

Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Lee Jones 2012-03-08 09:02:02 +00:00 committed by Arnd Bergmann
parent 4905af0e13
commit f1949ea0d1
2 changed files with 14 additions and 1 deletions
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8
arch/arm/boot/dts/db8500.dtsi
View file

@ -29,6 +29,14 @@
<0xa0410100 0x100>;
};
L2: l2-cache {
compatible = "arm,pl310-cache";
reg = <0xa0412000 0x1000>;
interrupts = <0 13 4>;
cache-unified;
cache-level = <2>;
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 7 0x4>;

7
arch/arm/mach-ux500/cache-l2x0.c
View file

@ -5,6 +5,8 @@
*/
#include <linux/io.h>
#include <linux/of.h>
#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
#include <mach/hardware.h>
@ -45,7 +47,10 @@ static int __init ux500_l2x0_init(void)
ux500_l2x0_unlock();
/* 64KB way size, 8 way associativity, force WA */
l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
if (of_have_populated_dt())
l2x0_of_init(0x3e060000, 0xc0000fff);
else
l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
/*
* We can't disable l2 as we are in non secure mode, currently