myri10ge: more Intel chipsets providing aligned PCIe completions
Add the Intel 5000 southbridge (aka Intel 6310/6311/6321ESB) PCIe ports and the Intel E30x0 chipsets to the whitelist of aligned PCIe completion. Signed-off-by: Brice Goglin <brice@myri.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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@ -2487,6 +2487,10 @@ static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
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#define PCI_DEVICE_ID_INTEL_E5000_PCIE23 0x25f7
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#define PCI_DEVICE_ID_INTEL_E5000_PCIE23 0x25f7
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#define PCI_DEVICE_ID_INTEL_E5000_PCIE47 0x25fa
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#define PCI_DEVICE_ID_INTEL_E5000_PCIE47 0x25fa
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#define PCI_DEVICE_ID_INTEL_6300ESB_PCIEE1 0x3510
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#define PCI_DEVICE_ID_INTEL_6300ESB_PCIEE4 0x351b
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#define PCI_DEVICE_ID_INTEL_E3000_PCIE 0x2779
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#define PCI_DEVICE_ID_INTEL_E3010_PCIE 0x277a
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#define PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_FIRST 0x140
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#define PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_FIRST 0x140
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#define PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_LAST 0x142
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#define PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_LAST 0x142
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@ -2526,6 +2530,18 @@ static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
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PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_FIRST
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PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_FIRST
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&& bridge->device <=
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&& bridge->device <=
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PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_LAST)
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PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_LAST)
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/* All Intel E3000/E3010 PCIE ports */
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|| (bridge->vendor == PCI_VENDOR_ID_INTEL
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&& (bridge->device ==
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PCI_DEVICE_ID_INTEL_E3000_PCIE
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|| bridge->device ==
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PCI_DEVICE_ID_INTEL_E3010_PCIE))
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/* All Intel 6310/6311/6321ESB PCIE ports */
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|| (bridge->vendor == PCI_VENDOR_ID_INTEL
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&& bridge->device >=
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PCI_DEVICE_ID_INTEL_6300ESB_PCIEE1
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&& bridge->device <=
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PCI_DEVICE_ID_INTEL_6300ESB_PCIEE4)
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/* All Intel E5000 PCIE ports */
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/* All Intel E5000 PCIE ports */
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|| (bridge->vendor == PCI_VENDOR_ID_INTEL
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|| (bridge->vendor == PCI_VENDOR_ID_INTEL
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&& bridge->device >=
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&& bridge->device >=
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