Merge branch 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung
* 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: S3C2440: fix section mismatch on mini2440 ARM: S3C24XX: drop return codes in void function of dma.c ARM: S3C24XX: don't use uninitialized variable in dma.c ARM: EXYNOS4: Set appropriate I2C device variant ARM: S5PC100: Fix for compilation error spi/s3c64xx: Bug fix for SPI with different FIFO level ARM: SAMSUNG: Add tx_st_done variable ARM: EXYNOS4: Address a section mismatch w/ suspend issue. ARM: S5P: Fix bug on init of PWMTimers for HRTimer ARM: SAMSUNG: header file revised to prevent declaring duplicated ARM: EXYNOS4: fix improper gpio configuration ARM: EXYNOS4: Fix card detection for sdhci 0 and 2
This commit is contained in:
commit
f1a04dbd1e
|
@ -23,6 +23,7 @@
|
|||
#include <plat/sdhci.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/fimc-core.h>
|
||||
#include <plat/iic-core.h>
|
||||
|
||||
#include <mach/regs-irq.h>
|
||||
|
||||
|
@ -132,6 +133,11 @@ void __init exynos4_map_io(void)
|
|||
s3c_fimc_setname(1, "exynos4-fimc");
|
||||
s3c_fimc_setname(2, "exynos4-fimc");
|
||||
s3c_fimc_setname(3, "exynos4-fimc");
|
||||
|
||||
/* The I2C bus controllers are directly compatible with s3c2440 */
|
||||
s3c_i2c0_setname("s3c2440-i2c");
|
||||
s3c_i2c1_setname("s3c2440-i2c");
|
||||
s3c_i2c2_setname("s3c2440-i2c");
|
||||
}
|
||||
|
||||
void __init exynos4_init_clocks(int xtal)
|
||||
|
|
|
@ -330,7 +330,7 @@ struct platform_device exynos4_device_ac97 = {
|
|||
|
||||
static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
|
||||
{
|
||||
s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(4));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -13,7 +13,7 @@
|
|||
#include <linux/linkage.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
__INIT
|
||||
__CPUINIT
|
||||
|
||||
/*
|
||||
* exynos4 specific entry point for secondary CPUs. This provides
|
||||
|
|
|
@ -78,9 +78,7 @@ static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
|
|||
};
|
||||
|
||||
static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
|
||||
.cd_type = S3C_SDHCI_CD_GPIO,
|
||||
.ext_cd_gpio = EXYNOS4_GPK0(2),
|
||||
.ext_cd_gpio_invert = 1,
|
||||
.cd_type = S3C_SDHCI_CD_INTERNAL,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
|
||||
.max_width = 8,
|
||||
|
@ -96,9 +94,7 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
|
|||
};
|
||||
|
||||
static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
|
||||
.cd_type = S3C_SDHCI_CD_GPIO,
|
||||
.ext_cd_gpio = EXYNOS4_GPK2(2),
|
||||
.ext_cd_gpio_invert = 1,
|
||||
.cd_type = S3C_SDHCI_CD_INTERNAL,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
|
||||
.max_width = 8,
|
||||
|
|
|
@ -552,7 +552,7 @@ struct mini2440_features_t {
|
|||
struct platform_device *optional[8];
|
||||
};
|
||||
|
||||
static void mini2440_parse_features(
|
||||
static void __init mini2440_parse_features(
|
||||
struct mini2440_features_t * features,
|
||||
const char * features_str )
|
||||
{
|
||||
|
|
|
@ -88,6 +88,7 @@ static struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
|
|||
.cfg_gpio = s3c64xx_spi_cfg_gpio,
|
||||
.fifo_lvl_mask = 0x7f,
|
||||
.rx_lvl_offset = 13,
|
||||
.tx_st_done = 21,
|
||||
};
|
||||
|
||||
static u64 spi_dmamask = DMA_BIT_MASK(32);
|
||||
|
@ -132,6 +133,7 @@ static struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
|
|||
.cfg_gpio = s3c64xx_spi_cfg_gpio,
|
||||
.fifo_lvl_mask = 0x7f,
|
||||
.rx_lvl_offset = 13,
|
||||
.tx_st_done = 21,
|
||||
};
|
||||
|
||||
struct platform_device s3c64xx_device_spi1 = {
|
||||
|
|
|
@ -112,12 +112,14 @@ static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
|
|||
.cfg_gpio = s5p6440_spi_cfg_gpio,
|
||||
.fifo_lvl_mask = 0x1ff,
|
||||
.rx_lvl_offset = 15,
|
||||
.tx_st_done = 25,
|
||||
};
|
||||
|
||||
static struct s3c64xx_spi_info s5p6450_spi0_pdata = {
|
||||
.cfg_gpio = s5p6450_spi_cfg_gpio,
|
||||
.fifo_lvl_mask = 0x1ff,
|
||||
.rx_lvl_offset = 15,
|
||||
.tx_st_done = 25,
|
||||
};
|
||||
|
||||
static u64 spi_dmamask = DMA_BIT_MASK(32);
|
||||
|
@ -160,12 +162,14 @@ static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
|
|||
.cfg_gpio = s5p6440_spi_cfg_gpio,
|
||||
.fifo_lvl_mask = 0x7f,
|
||||
.rx_lvl_offset = 15,
|
||||
.tx_st_done = 25,
|
||||
};
|
||||
|
||||
static struct s3c64xx_spi_info s5p6450_spi1_pdata = {
|
||||
.cfg_gpio = s5p6450_spi_cfg_gpio,
|
||||
.fifo_lvl_mask = 0x7f,
|
||||
.rx_lvl_offset = 15,
|
||||
.tx_st_done = 25,
|
||||
};
|
||||
|
||||
struct platform_device s5p64x0_device_spi1 = {
|
||||
|
|
|
@ -15,6 +15,7 @@
|
|||
#include <mach/dma.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/spi-clocks.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#include <plat/s3c64xx-spi.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
|
@ -90,6 +91,7 @@ static struct s3c64xx_spi_info s5pc100_spi0_pdata = {
|
|||
.fifo_lvl_mask = 0x7f,
|
||||
.rx_lvl_offset = 13,
|
||||
.high_speed = 1,
|
||||
.tx_st_done = 21,
|
||||
};
|
||||
|
||||
static u64 spi_dmamask = DMA_BIT_MASK(32);
|
||||
|
@ -134,6 +136,7 @@ static struct s3c64xx_spi_info s5pc100_spi1_pdata = {
|
|||
.fifo_lvl_mask = 0x7f,
|
||||
.rx_lvl_offset = 13,
|
||||
.high_speed = 1,
|
||||
.tx_st_done = 21,
|
||||
};
|
||||
|
||||
struct platform_device s5pc100_device_spi1 = {
|
||||
|
@ -176,6 +179,7 @@ static struct s3c64xx_spi_info s5pc100_spi2_pdata = {
|
|||
.fifo_lvl_mask = 0x7f,
|
||||
.rx_lvl_offset = 13,
|
||||
.high_speed = 1,
|
||||
.tx_st_done = 21,
|
||||
};
|
||||
|
||||
struct platform_device s5pc100_device_spi2 = {
|
||||
|
|
|
@ -85,6 +85,7 @@ static struct s3c64xx_spi_info s5pv210_spi0_pdata = {
|
|||
.fifo_lvl_mask = 0x1ff,
|
||||
.rx_lvl_offset = 15,
|
||||
.high_speed = 1,
|
||||
.tx_st_done = 25,
|
||||
};
|
||||
|
||||
static u64 spi_dmamask = DMA_BIT_MASK(32);
|
||||
|
@ -129,6 +130,7 @@ static struct s3c64xx_spi_info s5pv210_spi1_pdata = {
|
|||
.fifo_lvl_mask = 0x7f,
|
||||
.rx_lvl_offset = 15,
|
||||
.high_speed = 1,
|
||||
.tx_st_done = 25,
|
||||
};
|
||||
|
||||
struct platform_device s5pv210_device_spi1 = {
|
||||
|
|
|
@ -1027,17 +1027,13 @@ int s3c2410_dma_config(unsigned int channel,
|
|||
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
|
||||
unsigned int dcon;
|
||||
|
||||
pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
|
||||
__func__, channel, xferunit, dcon);
|
||||
pr_debug("%s: chan=%d, xfer_unit=%d\n", __func__, channel, xferunit);
|
||||
|
||||
if (chan == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
pr_debug("%s: Initial dcon is %08x\n", __func__, dcon);
|
||||
|
||||
dcon = chan->dcon & dma_sel.dcon_mask;
|
||||
|
||||
pr_debug("%s: New dcon is %08x\n", __func__, dcon);
|
||||
pr_debug("%s: dcon is %08x\n", __func__, dcon);
|
||||
|
||||
switch (chan->req_ch) {
|
||||
case DMACH_I2S_IN:
|
||||
|
@ -1235,7 +1231,7 @@ static void s3c2410_dma_resume_chan(struct s3c2410_dma_chan *cp)
|
|||
/* restore channel's hardware configuration */
|
||||
|
||||
if (!cp->in_use)
|
||||
return 0;
|
||||
return;
|
||||
|
||||
printk(KERN_INFO "dma%d: restoring configuration\n", cp->number);
|
||||
|
||||
|
@ -1246,8 +1242,6 @@ static void s3c2410_dma_resume_chan(struct s3c2410_dma_chan *cp)
|
|||
|
||||
if (cp->map != NULL)
|
||||
dma_sel.select(cp, cp->map);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void s3c2410_dma_resume(void)
|
||||
|
|
|
@ -370,11 +370,11 @@ static void __init s5p_clocksource_init(void)
|
|||
|
||||
clock_rate = clk_get_rate(tin_source);
|
||||
|
||||
init_sched_clock(&cd, s5p_update_sched_clock, 32, clock_rate);
|
||||
|
||||
s5p_time_setup(timer_source.source_id, TCNT_MAX);
|
||||
s5p_time_start(timer_source.source_id, PERIODIC);
|
||||
|
||||
init_sched_clock(&cd, s5p_update_sched_clock, 32, clock_rate);
|
||||
|
||||
if (clocksource_register_hz(&time_clocksource, clock_rate))
|
||||
panic("%s: can't register clocksource\n", time_clocksource.name);
|
||||
}
|
||||
|
|
|
@ -12,6 +12,10 @@
|
|||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __PLAT_DEVS_H
|
||||
#define __PLAT_DEVS_H __FILE__
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
struct s3c24xx_uart_resources {
|
||||
|
@ -159,3 +163,5 @@ extern struct platform_device s3c_device_ac97;
|
|||
*/
|
||||
extern void *s3c_set_platdata(void *pd, size_t pdsize,
|
||||
struct platform_device *pdev);
|
||||
|
||||
#endif /* __PLAT_DEVS_H */
|
||||
|
|
|
@ -39,6 +39,7 @@ struct s3c64xx_spi_csinfo {
|
|||
* @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6
|
||||
* @rx_lvl_offset: Depends on tx fifo_lvl field and bus number
|
||||
* @high_speed: If the controller supports HIGH_SPEED_EN bit
|
||||
* @tx_st_done: Depends on tx fifo_lvl field
|
||||
*/
|
||||
struct s3c64xx_spi_info {
|
||||
int src_clk_nr;
|
||||
|
@ -53,6 +54,7 @@ struct s3c64xx_spi_info {
|
|||
int fifo_lvl_mask;
|
||||
int rx_lvl_offset;
|
||||
int high_speed;
|
||||
int tx_st_done;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
|
@ -116,9 +116,7 @@
|
|||
(((i)->fifo_lvl_mask + 1))) \
|
||||
? 1 : 0)
|
||||
|
||||
#define S3C64XX_SPI_ST_TX_DONE(v, i) ((((v) >> (i)->rx_lvl_offset) & \
|
||||
(((i)->fifo_lvl_mask + 1) << 1)) \
|
||||
? 1 : 0)
|
||||
#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & (1 << (i)->tx_st_done)) ? 1 : 0)
|
||||
#define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask)
|
||||
#define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask)
|
||||
|
||||
|
|
Loading…
Reference in a new issue