x86/cpu: Sanitize FAM6_ATOM naming
Going primarily by: https://en.wikipedia.org/wiki/List_of_Intel_Atom_microprocessors with additional information gleaned from other related pages; notably: - Bonnell shrink was called Saltwell - Moorefield is the Merriefield refresh which makes it Airmont The general naming scheme is: FAM6_ATOM_UARCH_SOCTYPE for i in `git grep -l FAM6_ATOM` ; do sed -i -e 's/ATOM_PINEVIEW/ATOM_BONNELL/g' \ -e 's/ATOM_LINCROFT/ATOM_BONNELL_MID/' \ -e 's/ATOM_PENWELL/ATOM_SALTWELL_MID/g' \ -e 's/ATOM_CLOVERVIEW/ATOM_SALTWELL_TABLET/g' \ -e 's/ATOM_CEDARVIEW/ATOM_SALTWELL/g' \ -e 's/ATOM_SILVERMONT1/ATOM_SILVERMONT/g' \ -e 's/ATOM_SILVERMONT2/ATOM_SILVERMONT_X/g' \ -e 's/ATOM_MERRIFIELD/ATOM_SILVERMONT_MID/g' \ -e 's/ATOM_MOOREFIELD/ATOM_AIRMONT_MID/g' \ -e 's/ATOM_DENVERTON/ATOM_GOLDMONT_X/g' \ -e 's/ATOM_GEMINI_LAKE/ATOM_GOLDMONT_PLUS/g' ${i} done Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Cc: dave.hansen@linux.intel.com Cc: len.brown@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -4121,11 +4121,11 @@ __init int intel_pmu_init(void)
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name = "nehalem";
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break;
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case INTEL_FAM6_ATOM_PINEVIEW:
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case INTEL_FAM6_ATOM_LINCROFT:
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case INTEL_FAM6_ATOM_PENWELL:
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case INTEL_FAM6_ATOM_CLOVERVIEW:
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case INTEL_FAM6_ATOM_CEDARVIEW:
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case INTEL_FAM6_ATOM_BONNELL:
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case INTEL_FAM6_ATOM_BONNELL_MID:
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case INTEL_FAM6_ATOM_SALTWELL:
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case INTEL_FAM6_ATOM_SALTWELL_MID:
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case INTEL_FAM6_ATOM_SALTWELL_TABLET:
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memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
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sizeof(hw_cache_event_ids));
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@ -4138,9 +4138,11 @@ __init int intel_pmu_init(void)
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name = "bonnell";
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break;
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case INTEL_FAM6_ATOM_SILVERMONT1:
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case INTEL_FAM6_ATOM_SILVERMONT2:
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case INTEL_FAM6_ATOM_SILVERMONT:
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case INTEL_FAM6_ATOM_SILVERMONT_X:
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case INTEL_FAM6_ATOM_SILVERMONT_MID:
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case INTEL_FAM6_ATOM_AIRMONT:
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case INTEL_FAM6_ATOM_AIRMONT_MID:
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memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
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sizeof(hw_cache_event_ids));
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memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
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@ -4159,7 +4161,7 @@ __init int intel_pmu_init(void)
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break;
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case INTEL_FAM6_ATOM_GOLDMONT:
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case INTEL_FAM6_ATOM_DENVERTON:
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case INTEL_FAM6_ATOM_GOLDMONT_X:
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memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
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sizeof(hw_cache_event_ids));
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memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
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@ -4185,7 +4187,7 @@ __init int intel_pmu_init(void)
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name = "goldmont";
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break;
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case INTEL_FAM6_ATOM_GEMINI_LAKE:
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case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
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memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
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sizeof(hw_cache_event_ids));
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memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,
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@ -559,8 +559,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
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X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_ULT, hswult_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT1, slm_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT2, slm_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT, slm_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT_X, slm_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_ATOM_AIRMONT, slm_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_CORE, snb_cstates),
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@ -581,9 +581,9 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
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X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT, glm_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_ATOM_DENVERTON, glm_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_X, glm_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GEMINI_LAKE, glm_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_PLUS, glm_cstates),
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{ },
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};
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MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
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@ -777,9 +777,9 @@ static const struct x86_cpu_id rapl_cpu_match[] __initconst = {
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X86_RAPL_MODEL_MATCH(INTEL_FAM6_CANNONLAKE_MOBILE, skl_rapl_init),
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X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, hsw_rapl_init),
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X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_DENVERTON, hsw_rapl_init),
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X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT_X, hsw_rapl_init),
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X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GEMINI_LAKE, hsw_rapl_init),
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X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT_PLUS, hsw_rapl_init),
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{},
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};
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@ -69,14 +69,14 @@ static bool test_intel(int idx)
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case INTEL_FAM6_BROADWELL_GT3E:
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case INTEL_FAM6_BROADWELL_X:
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case INTEL_FAM6_ATOM_SILVERMONT1:
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case INTEL_FAM6_ATOM_SILVERMONT2:
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case INTEL_FAM6_ATOM_SILVERMONT:
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case INTEL_FAM6_ATOM_SILVERMONT_X:
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case INTEL_FAM6_ATOM_AIRMONT:
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case INTEL_FAM6_ATOM_GOLDMONT:
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case INTEL_FAM6_ATOM_DENVERTON:
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case INTEL_FAM6_ATOM_GOLDMONT_X:
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case INTEL_FAM6_ATOM_GEMINI_LAKE:
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case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
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case INTEL_FAM6_XEON_PHI_KNL:
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case INTEL_FAM6_XEON_PHI_KNM:
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@ -8,9 +8,6 @@
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* The "_X" parts are generally the EP and EX Xeons, or the
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* "Extreme" ones, like Broadwell-E.
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*
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* Things ending in "2" are usually because we have no better
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* name for them. There's no processor called "SILVERMONT2".
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*
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* While adding a new CPUID for a new microarchitecture, add a new
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* group to keep logically sorted out in chronological order. Within
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* that group keep the CPUID for the variants sorted by model number.
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@ -57,19 +54,23 @@
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/* "Small Core" Processors (Atom) */
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#define INTEL_FAM6_ATOM_PINEVIEW 0x1C
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#define INTEL_FAM6_ATOM_LINCROFT 0x26
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#define INTEL_FAM6_ATOM_PENWELL 0x27
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#define INTEL_FAM6_ATOM_CLOVERVIEW 0x35
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#define INTEL_FAM6_ATOM_CEDARVIEW 0x36
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#define INTEL_FAM6_ATOM_SILVERMONT1 0x37 /* BayTrail/BYT / Valleyview */
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#define INTEL_FAM6_ATOM_SILVERMONT2 0x4D /* Avaton/Rangely */
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#define INTEL_FAM6_ATOM_AIRMONT 0x4C /* CherryTrail / Braswell */
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#define INTEL_FAM6_ATOM_MERRIFIELD 0x4A /* Tangier */
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#define INTEL_FAM6_ATOM_MOOREFIELD 0x5A /* Anniedale */
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#define INTEL_FAM6_ATOM_GOLDMONT 0x5C
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#define INTEL_FAM6_ATOM_DENVERTON 0x5F /* Goldmont Microserver */
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#define INTEL_FAM6_ATOM_GEMINI_LAKE 0x7A
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#define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */
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#define INTEL_FAM6_ATOM_BONNELL_MID 0x26 /* Silverthorne, Lincroft */
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#define INTEL_FAM6_ATOM_SALTWELL 0x36 /* Cedarview */
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#define INTEL_FAM6_ATOM_SALTWELL_MID 0x27 /* Penwell */
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#define INTEL_FAM6_ATOM_SALTWELL_TABLET 0x35 /* Cloverview */
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#define INTEL_FAM6_ATOM_SILVERMONT 0x37 /* Bay Trail, Valleyview */
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#define INTEL_FAM6_ATOM_SILVERMONT_X 0x4D /* Avaton, Rangely */
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#define INTEL_FAM6_ATOM_SILVERMONT_MID 0x4A /* Merriefield */
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#define INTEL_FAM6_ATOM_AIRMONT 0x4C /* Cherry Trail, Braswell */
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#define INTEL_FAM6_ATOM_AIRMONT_MID 0x5A /* Moorefield */
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#define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
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#define INTEL_FAM6_ATOM_GOLDMONT_X 0x5F /* Denverton */
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#define INTEL_FAM6_ATOM_GOLDMONT_PLUS 0x7A /* Gemini Lake */
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/* Xeon Phi */
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@ -949,11 +949,11 @@ static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
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}
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static const __initconst struct x86_cpu_id cpu_no_speculation[] = {
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CEDARVIEW, X86_FEATURE_ANY },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CLOVERVIEW, X86_FEATURE_ANY },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_LINCROFT, X86_FEATURE_ANY },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PENWELL, X86_FEATURE_ANY },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PINEVIEW, X86_FEATURE_ANY },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SALTWELL, X86_FEATURE_ANY },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SALTWELL_TABLET, X86_FEATURE_ANY },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_BONNELL_MID, X86_FEATURE_ANY },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SALTWELL_MID, X86_FEATURE_ANY },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_BONNELL, X86_FEATURE_ANY },
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{ X86_VENDOR_CENTAUR, 5 },
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{ X86_VENDOR_INTEL, 5 },
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{ X86_VENDOR_NSC, 5 },
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/* Only list CPUs which speculate but are non susceptible to SSB */
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static const __initconst struct x86_cpu_id cpu_no_spec_store_bypass[] = {
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1 },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT2 },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_MERRIFIELD },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT_X },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT_MID },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_CORE_YONAH },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNL },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNM },
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@ -984,14 +984,14 @@ static const __initconst struct x86_cpu_id cpu_no_spec_store_bypass[] = {
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static const __initconst struct x86_cpu_id cpu_no_l1tf[] = {
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/* in addition to cpu_no_speculation */
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1 },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT2 },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT_X },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_MERRIFIELD },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_MOOREFIELD },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT_MID },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT_MID },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_DENVERTON },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_GEMINI_LAKE },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT_X },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT_PLUS },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNL },
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNM },
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{}
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@ -93,7 +93,7 @@ static u64 get_prefetch_disable_bits(void)
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*/
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return 0xF;
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case INTEL_FAM6_ATOM_GOLDMONT:
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case INTEL_FAM6_ATOM_GEMINI_LAKE:
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case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
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/*
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* SDM defines bits of MSR_MISC_FEATURE_CONTROL register
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* as:
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@ -1068,7 +1068,7 @@ static int measure_l2_residency(void *_plr)
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*/
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switch (boot_cpu_data.x86_model) {
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case INTEL_FAM6_ATOM_GOLDMONT:
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case INTEL_FAM6_ATOM_GEMINI_LAKE:
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case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
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perf_miss_attr.config = X86_CONFIG(.event = 0xd1,
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.umask = 0x10);
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perf_hit_attr.config = X86_CONFIG(.event = 0xd1,
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@ -635,7 +635,7 @@ unsigned long native_calibrate_tsc(void)
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case INTEL_FAM6_KABYLAKE_DESKTOP:
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crystal_khz = 24000; /* 24.0 MHz */
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break;
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case INTEL_FAM6_ATOM_DENVERTON:
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case INTEL_FAM6_ATOM_GOLDMONT_X:
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crystal_khz = 25000; /* 25.0 MHz */
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break;
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case INTEL_FAM6_ATOM_GOLDMONT:
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@ -59,12 +59,12 @@ static const struct freq_desc freq_desc_ann = {
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};
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static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
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INTEL_CPU_FAM6(ATOM_PENWELL, freq_desc_pnw),
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INTEL_CPU_FAM6(ATOM_CLOVERVIEW, freq_desc_clv),
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INTEL_CPU_FAM6(ATOM_SILVERMONT1, freq_desc_byt),
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INTEL_CPU_FAM6(ATOM_SALTWELL_MID, freq_desc_pnw),
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INTEL_CPU_FAM6(ATOM_SALTWELL_TABLET, freq_desc_clv),
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INTEL_CPU_FAM6(ATOM_SILVERMONT, freq_desc_byt),
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INTEL_CPU_FAM6(ATOM_SILVERMONT_MID, freq_desc_tng),
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INTEL_CPU_FAM6(ATOM_AIRMONT, freq_desc_cht),
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INTEL_CPU_FAM6(ATOM_MERRIFIELD, freq_desc_tng),
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INTEL_CPU_FAM6(ATOM_MOOREFIELD, freq_desc_ann),
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INTEL_CPU_FAM6(ATOM_AIRMONT_MID, freq_desc_ann),
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{}
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};
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@ -143,8 +143,8 @@ static void punit_dbgfs_unregister(void)
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(kernel_ulong_t)&drv_data }
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static const struct x86_cpu_id intel_punit_cpu_ids[] = {
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ICPU(INTEL_FAM6_ATOM_SILVERMONT1, punit_device_byt),
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ICPU(INTEL_FAM6_ATOM_MERRIFIELD, punit_device_tng),
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ICPU(INTEL_FAM6_ATOM_SILVERMONT, punit_device_byt),
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ICPU(INTEL_FAM6_ATOM_SILVERMONT_MID, punit_device_tng),
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ICPU(INTEL_FAM6_ATOM_AIRMONT, punit_device_cht),
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{}
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};
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@ -68,7 +68,7 @@ static struct bt_sfi_data tng_bt_sfi_data __initdata = {
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{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (kernel_ulong_t)&ddata }
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static const struct x86_cpu_id bt_sfi_cpu_ids[] = {
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ICPU(INTEL_FAM6_ATOM_MERRIFIELD, tng_bt_sfi_data),
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ICPU(INTEL_FAM6_ATOM_SILVERMONT_MID, tng_bt_sfi_data),
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{}
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};
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@ -292,7 +292,7 @@ static const struct lpss_device_desc bsw_spi_dev_desc = {
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#define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, }
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static const struct x86_cpu_id lpss_cpu_ids[] = {
|
||||
ICPU(INTEL_FAM6_ATOM_SILVERMONT1), /* Valleyview, Bay Trail */
|
||||
ICPU(INTEL_FAM6_ATOM_SILVERMONT), /* Valleyview, Bay Trail */
|
||||
ICPU(INTEL_FAM6_ATOM_AIRMONT), /* Braswell, Cherry Trail */
|
||||
{}
|
||||
};
|
||||
|
|
|
@ -54,7 +54,7 @@ static const struct always_present_id always_present_ids[] = {
|
|||
* Bay / Cherry Trail PWM directly poked by GPU driver in win10,
|
||||
* but Linux uses a separate PWM driver, harmless if not used.
|
||||
*/
|
||||
ENTRY("80860F09", "1", ICPU(INTEL_FAM6_ATOM_SILVERMONT1), {}),
|
||||
ENTRY("80860F09", "1", ICPU(INTEL_FAM6_ATOM_SILVERMONT), {}),
|
||||
ENTRY("80862288", "1", ICPU(INTEL_FAM6_ATOM_AIRMONT), {}),
|
||||
/*
|
||||
* The INT0002 device is necessary to clear wakeup interrupt sources
|
||||
|
|
|
@ -1778,7 +1778,7 @@ static const struct pstate_funcs knl_funcs = {
|
|||
static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
|
||||
ICPU(INTEL_FAM6_SANDYBRIDGE, core_funcs),
|
||||
ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_funcs),
|
||||
ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_funcs),
|
||||
ICPU(INTEL_FAM6_ATOM_SILVERMONT, silvermont_funcs),
|
||||
ICPU(INTEL_FAM6_IVYBRIDGE, core_funcs),
|
||||
ICPU(INTEL_FAM6_HASWELL_CORE, core_funcs),
|
||||
ICPU(INTEL_FAM6_BROADWELL_CORE, core_funcs),
|
||||
|
@ -1795,7 +1795,7 @@ static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
|
|||
ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_funcs),
|
||||
ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_funcs),
|
||||
ICPU(INTEL_FAM6_ATOM_GOLDMONT, core_funcs),
|
||||
ICPU(INTEL_FAM6_ATOM_GEMINI_LAKE, core_funcs),
|
||||
ICPU(INTEL_FAM6_ATOM_GOLDMONT_PLUS, core_funcs),
|
||||
ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
|
||||
{}
|
||||
};
|
||||
|
|
|
@ -1541,7 +1541,7 @@ static struct dunit_ops dnv_ops = {
|
|||
|
||||
static const struct x86_cpu_id pnd2_cpuids[] = {
|
||||
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT, 0, (kernel_ulong_t)&apl_ops },
|
||||
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_DENVERTON, 0, (kernel_ulong_t)&dnv_ops },
|
||||
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT_X, 0, (kernel_ulong_t)&dnv_ops },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(x86cpu, pnd2_cpuids);
|
||||
|
|
|
@ -1076,14 +1076,14 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = {
|
|||
ICPU(INTEL_FAM6_WESTMERE, idle_cpu_nehalem),
|
||||
ICPU(INTEL_FAM6_WESTMERE_EP, idle_cpu_nehalem),
|
||||
ICPU(INTEL_FAM6_NEHALEM_EX, idle_cpu_nehalem),
|
||||
ICPU(INTEL_FAM6_ATOM_PINEVIEW, idle_cpu_atom),
|
||||
ICPU(INTEL_FAM6_ATOM_LINCROFT, idle_cpu_lincroft),
|
||||
ICPU(INTEL_FAM6_ATOM_BONNELL, idle_cpu_atom),
|
||||
ICPU(INTEL_FAM6_ATOM_BONNELL_MID, idle_cpu_lincroft),
|
||||
ICPU(INTEL_FAM6_WESTMERE_EX, idle_cpu_nehalem),
|
||||
ICPU(INTEL_FAM6_SANDYBRIDGE, idle_cpu_snb),
|
||||
ICPU(INTEL_FAM6_SANDYBRIDGE_X, idle_cpu_snb),
|
||||
ICPU(INTEL_FAM6_ATOM_CEDARVIEW, idle_cpu_atom),
|
||||
ICPU(INTEL_FAM6_ATOM_SILVERMONT1, idle_cpu_byt),
|
||||
ICPU(INTEL_FAM6_ATOM_MERRIFIELD, idle_cpu_tangier),
|
||||
ICPU(INTEL_FAM6_ATOM_SALTWELL, idle_cpu_atom),
|
||||
ICPU(INTEL_FAM6_ATOM_SILVERMONT, idle_cpu_byt),
|
||||
ICPU(INTEL_FAM6_ATOM_SILVERMONT_MID, idle_cpu_tangier),
|
||||
ICPU(INTEL_FAM6_ATOM_AIRMONT, idle_cpu_cht),
|
||||
ICPU(INTEL_FAM6_IVYBRIDGE, idle_cpu_ivb),
|
||||
ICPU(INTEL_FAM6_IVYBRIDGE_X, idle_cpu_ivt),
|
||||
|
@ -1091,7 +1091,7 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = {
|
|||
ICPU(INTEL_FAM6_HASWELL_X, idle_cpu_hsw),
|
||||
ICPU(INTEL_FAM6_HASWELL_ULT, idle_cpu_hsw),
|
||||
ICPU(INTEL_FAM6_HASWELL_GT3E, idle_cpu_hsw),
|
||||
ICPU(INTEL_FAM6_ATOM_SILVERMONT2, idle_cpu_avn),
|
||||
ICPU(INTEL_FAM6_ATOM_SILVERMONT_X, idle_cpu_avn),
|
||||
ICPU(INTEL_FAM6_BROADWELL_CORE, idle_cpu_bdw),
|
||||
ICPU(INTEL_FAM6_BROADWELL_GT3E, idle_cpu_bdw),
|
||||
ICPU(INTEL_FAM6_BROADWELL_X, idle_cpu_bdw),
|
||||
|
@ -1104,8 +1104,8 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = {
|
|||
ICPU(INTEL_FAM6_XEON_PHI_KNL, idle_cpu_knl),
|
||||
ICPU(INTEL_FAM6_XEON_PHI_KNM, idle_cpu_knl),
|
||||
ICPU(INTEL_FAM6_ATOM_GOLDMONT, idle_cpu_bxt),
|
||||
ICPU(INTEL_FAM6_ATOM_GEMINI_LAKE, idle_cpu_bxt),
|
||||
ICPU(INTEL_FAM6_ATOM_DENVERTON, idle_cpu_dnv),
|
||||
ICPU(INTEL_FAM6_ATOM_GOLDMONT_PLUS, idle_cpu_bxt),
|
||||
ICPU(INTEL_FAM6_ATOM_GOLDMONT_X, idle_cpu_dnv),
|
||||
{}
|
||||
};
|
||||
|
||||
|
@ -1322,7 +1322,7 @@ static void intel_idle_state_table_update(void)
|
|||
ivt_idle_state_table_update();
|
||||
break;
|
||||
case INTEL_FAM6_ATOM_GOLDMONT:
|
||||
case INTEL_FAM6_ATOM_GEMINI_LAKE:
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
|
||||
bxt_idle_state_table_update();
|
||||
break;
|
||||
case INTEL_FAM6_SKYLAKE_DESKTOP:
|
||||
|
|
|
@ -246,7 +246,7 @@ static const struct sdhci_acpi_chip sdhci_acpi_chip_int = {
|
|||
static bool sdhci_acpi_byt(void)
|
||||
{
|
||||
static const struct x86_cpu_id byt[] = {
|
||||
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1 },
|
||||
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT },
|
||||
{}
|
||||
};
|
||||
|
||||
|
|
|
@ -62,8 +62,8 @@ static const struct pci_platform_pm_ops mid_pci_platform_pm = {
|
|||
* arch/x86/platform/intel-mid/pwr.c.
|
||||
*/
|
||||
static const struct x86_cpu_id lpss_cpu_ids[] = {
|
||||
ICPU(INTEL_FAM6_ATOM_PENWELL),
|
||||
ICPU(INTEL_FAM6_ATOM_MERRIFIELD),
|
||||
ICPU(INTEL_FAM6_ATOM_SALTWELL_MID),
|
||||
ICPU(INTEL_FAM6_ATOM_SILVERMONT_MID),
|
||||
{}
|
||||
};
|
||||
|
||||
|
|
|
@ -60,7 +60,7 @@ static const struct x86_cpu_id int0002_cpu_ids[] = {
|
|||
/*
|
||||
* Limit ourselves to Cherry Trail for now, until testing shows we
|
||||
* need to handle the INT0002 device on Baytrail too.
|
||||
* ICPU(INTEL_FAM6_ATOM_SILVERMONT1), * Valleyview, Bay Trail *
|
||||
* ICPU(INTEL_FAM6_ATOM_SILVERMONT), * Valleyview, Bay Trail *
|
||||
*/
|
||||
ICPU(INTEL_FAM6_ATOM_AIRMONT), /* Braswell, Cherry Trail */
|
||||
{}
|
||||
|
|
|
@ -125,8 +125,8 @@ static const struct mid_pb_ddata mrfld_ddata = {
|
|||
{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (kernel_ulong_t)&ddata }
|
||||
|
||||
static const struct x86_cpu_id mid_pb_cpu_ids[] = {
|
||||
ICPU(INTEL_FAM6_ATOM_PENWELL, mfld_ddata),
|
||||
ICPU(INTEL_FAM6_ATOM_MERRIFIELD, mrfld_ddata),
|
||||
ICPU(INTEL_FAM6_ATOM_SALTWELL_MID, mfld_ddata),
|
||||
ICPU(INTEL_FAM6_ATOM_SILVERMONT_MID, mrfld_ddata),
|
||||
{}
|
||||
};
|
||||
|
||||
|
|
|
@ -320,7 +320,7 @@ static struct telemetry_debugfs_conf telem_apl_debugfs_conf = {
|
|||
|
||||
static const struct x86_cpu_id telemetry_debugfs_cpu_ids[] = {
|
||||
TELEM_DEBUGFS_CPU(INTEL_FAM6_ATOM_GOLDMONT, telem_apl_debugfs_conf),
|
||||
TELEM_DEBUGFS_CPU(INTEL_FAM6_ATOM_GEMINI_LAKE, telem_apl_debugfs_conf),
|
||||
TELEM_DEBUGFS_CPU(INTEL_FAM6_ATOM_GOLDMONT_PLUS, telem_apl_debugfs_conf),
|
||||
{}
|
||||
};
|
||||
|
||||
|
|
|
@ -192,7 +192,7 @@ static struct telemetry_plt_config telem_glk_config = {
|
|||
|
||||
static const struct x86_cpu_id telemetry_cpu_ids[] = {
|
||||
TELEM_CPU(INTEL_FAM6_ATOM_GOLDMONT, telem_apl_config),
|
||||
TELEM_CPU(INTEL_FAM6_ATOM_GEMINI_LAKE, telem_glk_config),
|
||||
TELEM_CPU(INTEL_FAM6_ATOM_GOLDMONT_PLUS, telem_glk_config),
|
||||
{}
|
||||
};
|
||||
|
||||
|
|
|
@ -1164,13 +1164,13 @@ static const struct x86_cpu_id rapl_ids[] __initconst = {
|
|||
RAPL_CPU(INTEL_FAM6_KABYLAKE_DESKTOP, rapl_defaults_core),
|
||||
RAPL_CPU(INTEL_FAM6_CANNONLAKE_MOBILE, rapl_defaults_core),
|
||||
|
||||
RAPL_CPU(INTEL_FAM6_ATOM_SILVERMONT1, rapl_defaults_byt),
|
||||
RAPL_CPU(INTEL_FAM6_ATOM_SILVERMONT, rapl_defaults_byt),
|
||||
RAPL_CPU(INTEL_FAM6_ATOM_AIRMONT, rapl_defaults_cht),
|
||||
RAPL_CPU(INTEL_FAM6_ATOM_MERRIFIELD, rapl_defaults_tng),
|
||||
RAPL_CPU(INTEL_FAM6_ATOM_MOOREFIELD, rapl_defaults_ann),
|
||||
RAPL_CPU(INTEL_FAM6_ATOM_SILVERMONT_MID, rapl_defaults_tng),
|
||||
RAPL_CPU(INTEL_FAM6_ATOM_AIRMONT_MID, rapl_defaults_ann),
|
||||
RAPL_CPU(INTEL_FAM6_ATOM_GOLDMONT, rapl_defaults_core),
|
||||
RAPL_CPU(INTEL_FAM6_ATOM_GEMINI_LAKE, rapl_defaults_core),
|
||||
RAPL_CPU(INTEL_FAM6_ATOM_DENVERTON, rapl_defaults_core),
|
||||
RAPL_CPU(INTEL_FAM6_ATOM_GOLDMONT_PLUS, rapl_defaults_core),
|
||||
RAPL_CPU(INTEL_FAM6_ATOM_GOLDMONT_X, rapl_defaults_core),
|
||||
|
||||
RAPL_CPU(INTEL_FAM6_XEON_PHI_KNL, rapl_defaults_hsw_server),
|
||||
RAPL_CPU(INTEL_FAM6_XEON_PHI_KNM, rapl_defaults_hsw_server),
|
||||
|
|
|
@ -45,7 +45,7 @@ static irqreturn_t soc_irq_thread_fn(int irq, void *dev_data)
|
|||
}
|
||||
|
||||
static const struct x86_cpu_id soc_thermal_ids[] = {
|
||||
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1, 0,
|
||||
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT, 0,
|
||||
BYT_SOC_DTS_APIC_IRQ},
|
||||
{}
|
||||
};
|
||||
|
|
|
@ -787,7 +787,7 @@ static struct snd_soc_card byt_rt5651_card = {
|
|||
};
|
||||
|
||||
static const struct x86_cpu_id baytrail_cpu_ids[] = {
|
||||
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1 }, /* Valleyview */
|
||||
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT }, /* Valleyview */
|
||||
{}
|
||||
};
|
||||
|
||||
|
|
|
@ -2082,7 +2082,7 @@ int has_turbo_ratio_group_limits(int family, int model)
|
|||
switch (model) {
|
||||
case INTEL_FAM6_ATOM_GOLDMONT:
|
||||
case INTEL_FAM6_SKYLAKE_X:
|
||||
case INTEL_FAM6_ATOM_DENVERTON:
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_X:
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
|
@ -3149,9 +3149,9 @@ int probe_nhm_msrs(unsigned int family, unsigned int model)
|
|||
pkg_cstate_limits = skx_pkg_cstate_limits;
|
||||
has_misc_feature_control = 1;
|
||||
break;
|
||||
case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */
|
||||
case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
|
||||
no_MSR_MISC_PWR_MGMT = 1;
|
||||
case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */
|
||||
case INTEL_FAM6_ATOM_SILVERMONT_X: /* AVN */
|
||||
pkg_cstate_limits = slv_pkg_cstate_limits;
|
||||
break;
|
||||
case INTEL_FAM6_ATOM_AIRMONT: /* AMT */
|
||||
|
@ -3163,8 +3163,8 @@ int probe_nhm_msrs(unsigned int family, unsigned int model)
|
|||
pkg_cstate_limits = phi_pkg_cstate_limits;
|
||||
break;
|
||||
case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
|
||||
case INTEL_FAM6_ATOM_GEMINI_LAKE:
|
||||
case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_X: /* DNV */
|
||||
pkg_cstate_limits = bxt_pkg_cstate_limits;
|
||||
break;
|
||||
default:
|
||||
|
@ -3193,9 +3193,9 @@ int has_slv_msrs(unsigned int family, unsigned int model)
|
|||
return 0;
|
||||
|
||||
switch (model) {
|
||||
case INTEL_FAM6_ATOM_SILVERMONT1:
|
||||
case INTEL_FAM6_ATOM_MERRIFIELD:
|
||||
case INTEL_FAM6_ATOM_MOOREFIELD:
|
||||
case INTEL_FAM6_ATOM_SILVERMONT:
|
||||
case INTEL_FAM6_ATOM_SILVERMONT_MID:
|
||||
case INTEL_FAM6_ATOM_AIRMONT_MID:
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
|
@ -3207,7 +3207,7 @@ int is_dnv(unsigned int family, unsigned int model)
|
|||
return 0;
|
||||
|
||||
switch (model) {
|
||||
case INTEL_FAM6_ATOM_DENVERTON:
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_X:
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
|
@ -3724,8 +3724,8 @@ double get_tdp(unsigned int model)
|
|||
return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units;
|
||||
|
||||
switch (model) {
|
||||
case INTEL_FAM6_ATOM_SILVERMONT1:
|
||||
case INTEL_FAM6_ATOM_SILVERMONT2:
|
||||
case INTEL_FAM6_ATOM_SILVERMONT:
|
||||
case INTEL_FAM6_ATOM_SILVERMONT_X:
|
||||
return 30.0;
|
||||
default:
|
||||
return 135.0;
|
||||
|
@ -3791,7 +3791,7 @@ void rapl_probe(unsigned int family, unsigned int model)
|
|||
}
|
||||
break;
|
||||
case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
|
||||
case INTEL_FAM6_ATOM_GEMINI_LAKE:
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
|
||||
do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO;
|
||||
if (rapl_joules)
|
||||
BIC_PRESENT(BIC_Pkg_J);
|
||||
|
@ -3850,8 +3850,8 @@ void rapl_probe(unsigned int family, unsigned int model)
|
|||
BIC_PRESENT(BIC_RAMWatt);
|
||||
}
|
||||
break;
|
||||
case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */
|
||||
case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */
|
||||
case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
|
||||
case INTEL_FAM6_ATOM_SILVERMONT_X: /* AVN */
|
||||
do_rapl = RAPL_PKG | RAPL_CORES;
|
||||
if (rapl_joules) {
|
||||
BIC_PRESENT(BIC_Pkg_J);
|
||||
|
@ -3861,7 +3861,7 @@ void rapl_probe(unsigned int family, unsigned int model)
|
|||
BIC_PRESENT(BIC_CorWatt);
|
||||
}
|
||||
break;
|
||||
case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_X: /* DNV */
|
||||
do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS;
|
||||
BIC_PRESENT(BIC_PKG__);
|
||||
BIC_PRESENT(BIC_RAM__);
|
||||
|
@ -3884,7 +3884,7 @@ void rapl_probe(unsigned int family, unsigned int model)
|
|||
return;
|
||||
|
||||
rapl_power_units = 1.0 / (1 << (msr & 0xF));
|
||||
if (model == INTEL_FAM6_ATOM_SILVERMONT1)
|
||||
if (model == INTEL_FAM6_ATOM_SILVERMONT)
|
||||
rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000;
|
||||
else
|
||||
rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F));
|
||||
|
@ -4141,8 +4141,8 @@ int has_snb_msrs(unsigned int family, unsigned int model)
|
|||
case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */
|
||||
case INTEL_FAM6_SKYLAKE_X: /* SKX */
|
||||
case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
|
||||
case INTEL_FAM6_ATOM_GEMINI_LAKE:
|
||||
case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_X: /* DNV */
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
|
@ -4174,7 +4174,7 @@ int has_hsw_msrs(unsigned int family, unsigned int model)
|
|||
case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
|
||||
case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */
|
||||
case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
|
||||
case INTEL_FAM6_ATOM_GEMINI_LAKE:
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
|
@ -4209,8 +4209,8 @@ int is_slm(unsigned int family, unsigned int model)
|
|||
if (!genuine_intel)
|
||||
return 0;
|
||||
switch (model) {
|
||||
case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */
|
||||
case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */
|
||||
case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
|
||||
case INTEL_FAM6_ATOM_SILVERMONT_X: /* AVN */
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
|
@ -4581,11 +4581,11 @@ void process_cpuid()
|
|||
case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
|
||||
crystal_hz = 24000000; /* 24.0 MHz */
|
||||
break;
|
||||
case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_X: /* DNV */
|
||||
crystal_hz = 25000000; /* 25.0 MHz */
|
||||
break;
|
||||
case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
|
||||
case INTEL_FAM6_ATOM_GEMINI_LAKE:
|
||||
case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
|
||||
crystal_hz = 19200000; /* 19.2 MHz */
|
||||
break;
|
||||
default:
|
||||
|
|
Loading…
Reference in a new issue