drm/radeon/kms: fix 2D tiling CS support on EG/CM
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=43191 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -38,6 +38,7 @@ struct evergreen_cs_track {
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u32 group_size;
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u32 nbanks;
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u32 npipes;
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u32 row_size;
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/* value we track */
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u32 nsamples;
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u32 cb_color_base_last[12];
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@ -77,6 +78,44 @@ struct evergreen_cs_track {
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struct radeon_bo *db_s_write_bo;
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};
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static u32 evergreen_cs_get_aray_mode(u32 tiling_flags)
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{
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if (tiling_flags & RADEON_TILING_MACRO)
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return ARRAY_2D_TILED_THIN1;
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else if (tiling_flags & RADEON_TILING_MICRO)
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return ARRAY_1D_TILED_THIN1;
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else
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return ARRAY_LINEAR_GENERAL;
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}
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static u32 evergreen_cs_get_num_banks(u32 nbanks)
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{
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switch (nbanks) {
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case 2:
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return ADDR_SURF_2_BANK;
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case 4:
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return ADDR_SURF_4_BANK;
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case 8:
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default:
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return ADDR_SURF_8_BANK;
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case 16:
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return ADDR_SURF_16_BANK;
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}
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}
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static u32 evergreen_cs_get_tile_split(u32 row_size)
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{
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switch (row_size) {
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case 1:
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default:
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return ADDR_SURF_TILE_SPLIT_1KB;
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case 2:
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return ADDR_SURF_TILE_SPLIT_2KB;
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case 4:
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return ADDR_SURF_TILE_SPLIT_4KB;
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}
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}
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static void evergreen_cs_track_init(struct evergreen_cs_track *track)
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{
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int i;
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@ -490,12 +529,11 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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}
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ib[idx] &= ~Z_ARRAY_MODE(0xf);
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track->db_z_info &= ~Z_ARRAY_MODE(0xf);
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ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
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track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
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if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
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ib[idx] |= Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
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track->db_z_info |= Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
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} else {
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ib[idx] |= Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
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track->db_z_info |= Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
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ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
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ib[idx] |= DB_TILE_SPLIT(evergreen_cs_get_tile_split(track->row_size));
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}
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}
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break;
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@ -618,13 +656,8 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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"0x%04X\n", reg);
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return -EINVAL;
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}
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if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
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ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
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track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
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} else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
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ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
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track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
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}
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ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
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track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
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}
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break;
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case CB_COLOR8_INFO:
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@ -640,13 +673,8 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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"0x%04X\n", reg);
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return -EINVAL;
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}
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if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
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ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
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track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
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} else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
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ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
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track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
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}
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ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
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track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
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}
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break;
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case CB_COLOR0_PITCH:
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@ -701,6 +729,16 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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case CB_COLOR9_ATTRIB:
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case CB_COLOR10_ATTRIB:
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case CB_COLOR11_ATTRIB:
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r = evergreen_cs_packet_next_reloc(p, &reloc);
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if (r) {
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dev_warn(p->dev, "bad SET_CONTEXT_REG "
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"0x%04X\n", reg);
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return -EINVAL;
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}
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if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
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ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
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ib[idx] |= CB_TILE_SPLIT(evergreen_cs_get_tile_split(track->row_size));
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}
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break;
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case CB_COLOR0_DIM:
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case CB_COLOR1_DIM:
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@ -1318,10 +1356,14 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
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}
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ib[idx+1+(i*8)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
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if (!p->keep_tiling_flags) {
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if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
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ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
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else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
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ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
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ib[idx+1+(i*8)+1] |=
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TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
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if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
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ib[idx+1+(i*8)+6] |=
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TEX_TILE_SPLIT(evergreen_cs_get_tile_split(track->row_size));
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ib[idx+1+(i*8)+7] |=
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TEX_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
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}
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}
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texture = reloc->robj;
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/* tex mip base */
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@ -1422,6 +1464,7 @@ int evergreen_cs_parse(struct radeon_cs_parser *p)
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{
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struct radeon_cs_packet pkt;
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struct evergreen_cs_track *track;
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u32 tmp;
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int r;
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if (p->track == NULL) {
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@ -1430,9 +1473,63 @@ int evergreen_cs_parse(struct radeon_cs_parser *p)
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if (track == NULL)
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return -ENOMEM;
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evergreen_cs_track_init(track);
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track->npipes = p->rdev->config.evergreen.tiling_npipes;
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track->nbanks = p->rdev->config.evergreen.tiling_nbanks;
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track->group_size = p->rdev->config.evergreen.tiling_group_size;
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if (p->rdev->family >= CHIP_CAYMAN)
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tmp = p->rdev->config.cayman.tile_config;
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else
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tmp = p->rdev->config.evergreen.tile_config;
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switch (tmp & 0xf) {
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case 0:
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track->npipes = 1;
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break;
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case 1:
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default:
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track->npipes = 2;
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break;
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case 2:
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track->npipes = 4;
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break;
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case 3:
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track->npipes = 8;
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break;
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}
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switch ((tmp & 0xf0) >> 4) {
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case 0:
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track->nbanks = 4;
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break;
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case 1:
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default:
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track->nbanks = 8;
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break;
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case 2:
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track->nbanks = 16;
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break;
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}
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switch ((tmp & 0xf00) >> 8) {
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case 0:
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track->group_size = 256;
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break;
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case 1:
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default:
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track->group_size = 512;
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break;
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}
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switch ((tmp & 0xf000) >> 12) {
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case 0:
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track->row_size = 1;
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break;
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case 1:
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default:
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track->row_size = 2;
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break;
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case 2:
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track->row_size = 4;
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break;
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}
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p->track = track;
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}
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do {
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@ -899,6 +899,10 @@
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#define DB_HTILE_DATA_BASE 0x28014
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#define DB_Z_INFO 0x28040
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# define Z_ARRAY_MODE(x) ((x) << 4)
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# define DB_TILE_SPLIT(x) (((x) & 0x7) << 8)
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# define DB_NUM_BANKS(x) (((x) & 0x3) << 12)
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# define DB_BANK_WIDTH(x) (((x) & 0x3) << 16)
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# define DB_BANK_HEIGHT(x) (((x) & 0x3) << 20)
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#define DB_STENCIL_INFO 0x28044
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#define DB_Z_READ_BASE 0x28048
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#define DB_STENCIL_READ_BASE 0x2804c
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@ -951,6 +955,29 @@
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# define CB_SF_EXPORT_FULL 0
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# define CB_SF_EXPORT_NORM 1
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#define CB_COLOR0_ATTRIB 0x28c74
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# define CB_TILE_SPLIT(x) (((x) & 0x7) << 5)
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# define ADDR_SURF_TILE_SPLIT_64B 0
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# define ADDR_SURF_TILE_SPLIT_128B 1
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# define ADDR_SURF_TILE_SPLIT_256B 2
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# define ADDR_SURF_TILE_SPLIT_512B 3
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# define ADDR_SURF_TILE_SPLIT_1KB 4
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# define ADDR_SURF_TILE_SPLIT_2KB 5
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# define ADDR_SURF_TILE_SPLIT_4KB 6
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# define CB_NUM_BANKS(x) (((x) & 0x3) << 10)
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# define ADDR_SURF_2_BANK 0
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# define ADDR_SURF_4_BANK 1
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# define ADDR_SURF_8_BANK 2
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# define ADDR_SURF_16_BANK 3
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# define CB_BANK_WIDTH(x) (((x) & 0x3) << 13)
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# define ADDR_SURF_BANK_WIDTH_1 0
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# define ADDR_SURF_BANK_WIDTH_2 1
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# define ADDR_SURF_BANK_WIDTH_4 2
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# define ADDR_SURF_BANK_WIDTH_8 3
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# define CB_BANK_HEIGHT(x) (((x) & 0x3) << 16)
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# define ADDR_SURF_BANK_HEIGHT_1 0
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# define ADDR_SURF_BANK_HEIGHT_2 1
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# define ADDR_SURF_BANK_HEIGHT_4 2
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# define ADDR_SURF_BANK_HEIGHT_8 3
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#define CB_COLOR0_DIM 0x28c78
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/* only CB0-7 blocks have these regs */
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#define CB_COLOR0_CMASK 0x28c7c
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@ -1137,7 +1164,11 @@
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# define SQ_SEL_1 5
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#define SQ_TEX_RESOURCE_WORD5_0 0x30014
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#define SQ_TEX_RESOURCE_WORD6_0 0x30018
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# define TEX_TILE_SPLIT(x) (((x) & 0x7) << 29)
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#define SQ_TEX_RESOURCE_WORD7_0 0x3001c
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# define TEX_BANK_WIDTH(x) (((x) & 0x3) << 8)
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# define TEX_BANK_HEIGHT(x) (((x) & 0x3) << 10)
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# define TEX_NUM_BANKS(x) (((x) & 0x3) << 16)
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#define SQ_VTX_CONSTANT_WORD0_0 0x30000
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#define SQ_VTX_CONSTANT_WORD1_0 0x30004
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