fsldma: fix issue of slow dma
Fixed fsl dma slow issue by initializing dma mode register with bandwidth control. It boosts dma performance and should works with 85xx board. Signed-off-by: Forrest Shi <b29237@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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@ -50,9 +50,11 @@ static void dma_init(struct fsldma_chan *chan)
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* EIE - Error interrupt enable
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* EOSIE - End of segments interrupt enable (basic mode)
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* EOLNIE - End of links interrupt enable
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* BWC - Bandwidth sharing among channels
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*/
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DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EIE
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| FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32);
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DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC
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| FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE
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| FSL_DMA_MR_EOSIE, 32);
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break;
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case FSL_DMA_IP_83XX:
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/* Set the channel to below modes:
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
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* Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Author:
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* Zhang Wei <wei.zhang@freescale.com>, Jul 2007
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@ -36,6 +36,13 @@
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#define FSL_DMA_MR_DAHE 0x00002000
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#define FSL_DMA_MR_SAHE 0x00001000
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/*
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* Bandwidth/pause control determines how many bytes a given
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* channel is allowed to transfer before the DMA engine pauses
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* the current channel and switches to the next channel
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*/
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#define FSL_DMA_MR_BWC 0x08000000
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/* Special MR definition for MPC8349 */
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#define FSL_DMA_MR_EOTIE 0x00000080
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#define FSL_DMA_MR_PRC_RM 0x00000800
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