tg3: Move per-int tx members to a per-int struct
This patch moves the tx_prod, tx_cons, tx_pending, tx_ring, and tx_buffers transmit ring device members to a per-interrupt structure. It also adds a new transmit producer mailbox member (prodmbox) and converts the code to use it rather than a preprocessor constant. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>wifi-calibration
Matt Carlson
David S. Miller
parent
723344820a
commit
f3f3f27e5b
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@ -136,7 +136,7 @@
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#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
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/* minimum number of free TX descriptors required to wake up TX process */
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#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
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#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
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#define TG3_RAW_IP_ALIGN 2
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@ -656,7 +656,7 @@ static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
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work_exists = 1;
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}
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/* check for RX/TX work to do */
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if (sblk->idx[0].tx_consumer != tp->tx_cons ||
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if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
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sblk->idx[0].rx_producer != tnapi->rx_rcb_ptr)
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work_exists = 1;
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@ -4269,11 +4269,11 @@ static void tg3_tx_recover(struct tg3 *tp)
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spin_unlock(&tp->lock);
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}
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static inline u32 tg3_tx_avail(struct tg3 *tp)
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static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
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{
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smp_mb();
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return (tp->tx_pending -
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((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
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return tnapi->tx_pending -
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((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
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}
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/* Tigon3 never reports partial packet sends. So we do not
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@ -4284,10 +4284,10 @@ static void tg3_tx(struct tg3_napi *tnapi)
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{
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struct tg3 *tp = tnapi->tp;
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u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
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u32 sw_idx = tp->tx_cons;
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u32 sw_idx = tnapi->tx_cons;
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while (sw_idx != hw_idx) {
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struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
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struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
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struct sk_buff *skb = ri->skb;
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int i, tx_bug = 0;
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@ -4303,7 +4303,7 @@ static void tg3_tx(struct tg3_napi *tnapi)
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sw_idx = NEXT_TX(sw_idx);
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for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
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ri = &tp->tx_buffers[sw_idx];
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ri = &tnapi->tx_buffers[sw_idx];
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if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
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tx_bug = 1;
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sw_idx = NEXT_TX(sw_idx);
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@ -4317,7 +4317,7 @@ static void tg3_tx(struct tg3_napi *tnapi)
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}
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}
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tp->tx_cons = sw_idx;
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tnapi->tx_cons = sw_idx;
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/* Need to make the tx_cons update visible to tg3_start_xmit()
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* before checking for netif_queue_stopped(). Without the
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@ -4327,10 +4327,10 @@ static void tg3_tx(struct tg3_napi *tnapi)
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smp_mb();
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if (unlikely(netif_queue_stopped(tp->dev) &&
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(tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
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(tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
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netif_tx_lock(tp->dev);
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if (netif_queue_stopped(tp->dev) &&
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(tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
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(tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
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netif_wake_queue(tp->dev);
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netif_tx_unlock(tp->dev);
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}
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@ -4668,7 +4668,7 @@ static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
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}
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/* run TX completion thread */
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if (sblk->idx[0].tx_consumer != tp->tx_cons) {
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if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
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tg3_tx(tnapi);
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if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
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return work_done;
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@ -5044,13 +5044,14 @@ static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
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#endif
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}
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static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
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static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
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/* Workaround 4GB and 40-bit hardware DMA bugs. */
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static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
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u32 last_plus_one, u32 *start,
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u32 base_flags, u32 mss)
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{
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struct tg3_napi *tnapi = &tp->napi[0];
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struct sk_buff *new_skb;
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dma_addr_t new_addr = 0;
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u32 entry = *start;
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@ -5085,7 +5086,7 @@ static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
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dev_kfree_skb(new_skb);
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new_skb = NULL;
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} else {
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tg3_set_txd(tp, entry, new_addr, new_skb->len,
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tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
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base_flags, 1 | (mss << 1));
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*start = NEXT_TX(entry);
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}
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@ -5094,11 +5095,10 @@ static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
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/* Now clean up the sw ring entries. */
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i = 0;
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while (entry != last_plus_one) {
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if (i == 0) {
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tp->tx_buffers[entry].skb = new_skb;
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} else {
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tp->tx_buffers[entry].skb = NULL;
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}
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if (i == 0)
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tnapi->tx_buffers[entry].skb = new_skb;
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else
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tnapi->tx_buffers[entry].skb = NULL;
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entry = NEXT_TX(entry);
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i++;
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}
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@ -5109,11 +5109,11 @@ static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
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return ret;
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}
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static void tg3_set_txd(struct tg3 *tp, int entry,
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static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
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dma_addr_t mapping, int len, u32 flags,
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u32 mss_and_is_end)
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{
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struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
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struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
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int is_end = (mss_and_is_end & 0x1);
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u32 mss = (mss_and_is_end >> 1);
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u32 vlan_tag = 0;
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@ -5141,6 +5141,7 @@ static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
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u32 len, entry, base_flags, mss;
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struct skb_shared_info *sp;
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dma_addr_t mapping;
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struct tg3_napi *tnapi = &tp->napi[0];
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len = skb_headlen(skb);
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@ -5149,7 +5150,7 @@ static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
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* interrupt. Furthermore, IRQ processing runs lockless so we have
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* no IRQ context deadlocks to worry about either. Rejoice!
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*/
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if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
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if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
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if (!netif_queue_stopped(dev)) {
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netif_stop_queue(dev);
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@ -5160,7 +5161,7 @@ static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
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return NETDEV_TX_BUSY;
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}
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entry = tp->tx_prod;
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entry = tnapi->tx_prod;
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base_flags = 0;
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mss = 0;
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if ((mss = skb_shinfo(skb)->gso_size) != 0) {
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@ -5208,9 +5209,9 @@ static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
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mapping = sp->dma_head;
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tp->tx_buffers[entry].skb = skb;
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tnapi->tx_buffers[entry].skb = skb;
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tg3_set_txd(tp, entry, mapping, len, base_flags,
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tg3_set_txd(tnapi, entry, mapping, len, base_flags,
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(skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
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entry = NEXT_TX(entry);
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@ -5225,9 +5226,9 @@ static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
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len = frag->size;
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mapping = sp->dma_maps[i];
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tp->tx_buffers[entry].skb = NULL;
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tnapi->tx_buffers[entry].skb = NULL;
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tg3_set_txd(tp, entry, mapping, len,
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tg3_set_txd(tnapi, entry, mapping, len,
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base_flags, (i == last) | (mss << 1));
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entry = NEXT_TX(entry);
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@ -5235,12 +5236,12 @@ static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
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}
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/* Packets are ready, update Tx producer idx local and on card. */
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tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
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tw32_tx_mbox(tnapi->prodmbox, entry);
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tp->tx_prod = entry;
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if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
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tnapi->tx_prod = entry;
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if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
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netif_stop_queue(dev);
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if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
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if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
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netif_wake_queue(tp->dev);
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}
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@ -5258,11 +5259,12 @@ static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
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static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
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{
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struct sk_buff *segs, *nskb;
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u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
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/* Estimate the number of fragments in the worst case */
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if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
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if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
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netif_stop_queue(tp->dev);
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if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
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if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
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return NETDEV_TX_BUSY;
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netif_wake_queue(tp->dev);
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@ -5295,6 +5297,7 @@ static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
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struct skb_shared_info *sp;
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int would_hit_hwbug;
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dma_addr_t mapping;
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struct tg3_napi *tnapi = &tp->napi[0];
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len = skb_headlen(skb);
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@ -5303,7 +5306,7 @@ static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
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* interrupt. Furthermore, IRQ processing runs lockless so we have
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* no IRQ context deadlocks to worry about either. Rejoice!
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*/
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if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
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if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
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if (!netif_queue_stopped(dev)) {
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netif_stop_queue(dev);
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@ -5314,7 +5317,7 @@ static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
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return NETDEV_TX_BUSY;
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}
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entry = tp->tx_prod;
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entry = tnapi->tx_prod;
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base_flags = 0;
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if (skb->ip_summed == CHECKSUM_PARTIAL)
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base_flags |= TXD_FLAG_TCPUDP_CSUM;
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@ -5384,7 +5387,7 @@ static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
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mapping = sp->dma_head;
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tp->tx_buffers[entry].skb = skb;
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tnapi->tx_buffers[entry].skb = skb;
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would_hit_hwbug = 0;
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@ -5393,7 +5396,7 @@ static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
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else if (tg3_4g_overflow_test(mapping, len))
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would_hit_hwbug = 1;
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tg3_set_txd(tp, entry, mapping, len, base_flags,
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tg3_set_txd(tnapi, entry, mapping, len, base_flags,
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(skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
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entry = NEXT_TX(entry);
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@ -5409,7 +5412,7 @@ static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
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len = frag->size;
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mapping = sp->dma_maps[i];
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tp->tx_buffers[entry].skb = NULL;
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tnapi->tx_buffers[entry].skb = NULL;
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if (tg3_4g_overflow_test(mapping, len))
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would_hit_hwbug = 1;
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@ -5418,10 +5421,10 @@ static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
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would_hit_hwbug = 1;
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if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
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tg3_set_txd(tp, entry, mapping, len,
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tg3_set_txd(tnapi, entry, mapping, len,
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base_flags, (i == last)|(mss << 1));
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else
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tg3_set_txd(tp, entry, mapping, len,
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tg3_set_txd(tnapi, entry, mapping, len,
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base_flags, (i == last));
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entry = NEXT_TX(entry);
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@ -5446,12 +5449,12 @@ static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
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}
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/* Packets are ready, update Tx producer idx local and on card. */
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tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
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tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, entry);
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tp->tx_prod = entry;
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if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
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tnapi->tx_prod = entry;
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if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
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netif_stop_queue(dev);
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if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
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if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
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netif_wake_queue(tp->dev);
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}
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@ -5522,8 +5525,8 @@ static int tg3_change_mtu(struct net_device *dev, int new_mtu)
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static void tg3_rx_prodring_free(struct tg3 *tp,
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struct tg3_rx_prodring_set *tpr)
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{
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struct ring_info *rxp;
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int i;
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struct ring_info *rxp;
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for (i = 0; i < TG3_RX_RING_SIZE; i++) {
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rxp = &tpr->rx_std_buffers[i];
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@ -5710,13 +5713,14 @@ err_out:
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*/
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static void tg3_free_rings(struct tg3 *tp)
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{
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struct tg3_napi *tnapi = &tp->napi[0];
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int i;
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for (i = 0; i < TG3_TX_RING_SIZE; ) {
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struct tx_ring_info *txp;
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struct sk_buff *skb;
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txp = &tp->tx_buffers[i];
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txp = &tnapi->tx_buffers[i];
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skb = txp->skb;
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if (skb == NULL) {
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@ -5751,7 +5755,7 @@ static int tg3_init_rings(struct tg3 *tp)
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tg3_free_rings(tp);
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/* Zero out all descriptors. */
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memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
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memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
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tnapi->rx_rcb_ptr = 0;
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memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
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@ -5767,12 +5771,12 @@ static void tg3_free_consistent(struct tg3 *tp)
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{
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struct tg3_napi *tnapi = &tp->napi[0];
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kfree(tp->tx_buffers);
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tp->tx_buffers = NULL;
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if (tp->tx_ring) {
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kfree(tnapi->tx_buffers);
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tnapi->tx_buffers = NULL;
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if (tnapi->tx_ring) {
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pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
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tp->tx_ring, tp->tx_desc_mapping);
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tp->tx_ring = NULL;
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tnapi->tx_ring, tnapi->tx_desc_mapping);
|
||||
tnapi->tx_ring = NULL;
|
||||
}
|
||||
if (tnapi->rx_rcb) {
|
||||
pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
|
||||
|
|
@ -5804,14 +5808,14 @@ static int tg3_alloc_consistent(struct tg3 *tp)
|
|||
if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
|
||||
return -ENOMEM;
|
||||
|
||||
tp->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
|
||||
TG3_TX_RING_SIZE, GFP_KERNEL);
|
||||
if (!tp->tx_buffers)
|
||||
tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
|
||||
TG3_TX_RING_SIZE, GFP_KERNEL);
|
||||
if (!tnapi->tx_buffers)
|
||||
goto err_out;
|
||||
|
||||
tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
|
||||
&tp->tx_desc_mapping);
|
||||
if (!tp->tx_ring)
|
||||
tnapi->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
|
||||
&tnapi->tx_desc_mapping);
|
||||
if (!tnapi->tx_ring)
|
||||
goto err_out;
|
||||
|
||||
tnapi->hw_status = pci_alloc_consistent(tp->pdev,
|
||||
|
|
@ -7094,13 +7098,15 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
|
|||
BDINFO_FLAGS_DISABLED);
|
||||
}
|
||||
|
||||
tp->tx_prod = 0;
|
||||
tp->tx_cons = 0;
|
||||
tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
|
||||
tp->napi[0].tx_prod = 0;
|
||||
tp->napi[0].tx_cons = 0;
|
||||
tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
|
||||
|
||||
val = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
|
||||
tw32_mailbox(val, 0);
|
||||
|
||||
tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
|
||||
tp->tx_desc_mapping,
|
||||
tp->napi[0].tx_desc_mapping,
|
||||
(TG3_TX_RING_SIZE <<
|
||||
BDINFO_FLAGS_MAXLEN_SHIFT),
|
||||
NIC_SRAM_TX_BUFFER_DESC);
|
||||
|
|
@ -9093,7 +9099,7 @@ static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *
|
|||
else
|
||||
ering->rx_jumbo_pending = 0;
|
||||
|
||||
ering->tx_pending = tp->tx_pending;
|
||||
ering->tx_pending = tp->napi[0].tx_pending;
|
||||
}
|
||||
|
||||
static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
|
||||
|
|
@ -9123,7 +9129,7 @@ static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *e
|
|||
tp->rx_pending > 63)
|
||||
tp->rx_pending = 63;
|
||||
tp->rx_jumbo_pending = ering->rx_jumbo_pending;
|
||||
tp->tx_pending = ering->tx_pending;
|
||||
tp->napi[0].tx_pending = ering->tx_pending;
|
||||
|
||||
if (netif_running(dev)) {
|
||||
tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
|
||||
|
|
@ -9928,14 +9934,13 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
|
|||
|
||||
num_pkts = 0;
|
||||
|
||||
tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
|
||||
tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
|
||||
|
||||
tp->tx_prod++;
|
||||
tnapi->tx_prod++;
|
||||
num_pkts++;
|
||||
|
||||
tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
|
||||
tp->tx_prod);
|
||||
tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
|
||||
tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
|
||||
tr32_mailbox(tnapi->prodmbox);
|
||||
|
||||
udelay(10);
|
||||
|
||||
|
|
@ -9948,7 +9953,7 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
|
|||
|
||||
tx_idx = tnapi->hw_status->idx[0].tx_consumer;
|
||||
rx_idx = rnapi->hw_status->idx[0].rx_producer;
|
||||
if ((tx_idx == tp->tx_prod) &&
|
||||
if ((tx_idx == tnapi->tx_prod) &&
|
||||
(rx_idx == (rx_start_idx + num_pkts)))
|
||||
break;
|
||||
}
|
||||
|
|
@ -9956,7 +9961,7 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
|
|||
pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
|
||||
dev_kfree_skb(skb);
|
||||
|
||||
if (tx_idx != tp->tx_prod)
|
||||
if (tx_idx != tnapi->tx_prod)
|
||||
goto out;
|
||||
|
||||
if (rx_idx != rx_start_idx + num_pkts)
|
||||
|
|
@ -13415,11 +13420,12 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
|
|||
|
||||
tp->rx_pending = TG3_DEF_RX_RING_PENDING;
|
||||
tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
|
||||
tp->tx_pending = TG3_DEF_TX_RING_PENDING;
|
||||
|
||||
tp->napi[0].tp = tp;
|
||||
tp->napi[0].int_mbox = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
|
||||
tp->napi[0].consmbox = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
|
||||
tp->napi[0].prodmbox = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
|
||||
tp->napi[0].tx_pending = TG3_DEF_TX_RING_PENDING;
|
||||
netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
|
||||
dev->ethtool_ops = &tg3_ethtool_ops;
|
||||
dev->watchdog_timeo = TG3_TX_TIMEOUT;
|
||||
|
|
|
|||
|
|
@ -2497,13 +2497,21 @@ struct tg3_napi {
|
|||
u32 last_tag;
|
||||
u32 last_irq_tag;
|
||||
u32 int_mbox;
|
||||
u32 tx_prod;
|
||||
u32 tx_cons;
|
||||
u32 tx_pending;
|
||||
u32 prodmbox;
|
||||
|
||||
u32 consmbox;
|
||||
u32 rx_rcb_ptr;
|
||||
|
||||
struct tg3_rx_buffer_desc *rx_rcb;
|
||||
struct tg3_tx_buffer_desc *tx_ring;
|
||||
struct tx_ring_info *tx_buffers;
|
||||
|
||||
dma_addr_t status_mapping;
|
||||
dma_addr_t rx_rcb_mapping;
|
||||
dma_addr_t tx_desc_mapping;
|
||||
};
|
||||
|
||||
struct tg3 {
|
||||
|
|
@ -2563,13 +2571,6 @@ struct tg3 {
|
|||
/* begin "tx thread" cacheline section */
|
||||
void (*write32_tx_mbox) (struct tg3 *, u32,
|
||||
u32);
|
||||
u32 tx_prod;
|
||||
u32 tx_cons;
|
||||
u32 tx_pending;
|
||||
|
||||
struct tg3_tx_buffer_desc *tx_ring;
|
||||
struct tx_ring_info *tx_buffers;
|
||||
dma_addr_t tx_desc_mapping;
|
||||
|
||||
/* begin "rx thread" cacheline section */
|
||||
struct tg3_napi napi[TG3_IRQ_MAX_VECS];
|
||||
|
|
|
|||
Loading…
Reference in New Issue