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[PATCH] shpchp: fix improper write to Command Completion Detect bit 

Current SHPCHP driver writes a '0' to the Command Completion Detect
bit to clear the Command Complete Interrupt Pending. But according to
the SHPC spec (See 4.7.3.1 System Interrupts), SHPCHP driver must
write '1'. This patch fixes this bug.

Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
wifi-calibration
Kenji Kaneshige 2005-11-24 11:39:29 +09:00 committed by Greg Kroah-Hartman
parent 0455986cce
commit f467f6187f
1 changed files with 2 additions and 2 deletions
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4
drivers/pci/hotplug/shpchp_hpc.c
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@ -1058,11 +1058,11 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
if (intr_loc & 0x0001) {
/*
* Command Complete Interrupt Pending
* RO only - clear by writing 0 to the Command Completion
* RO only - clear by writing 1 to the Command Completion
* Detect bit in Controller SERR-INT register
*/
temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
temp_dword &= 0xfffeffff;
temp_dword &= 0xfffdffff;
writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
wake_up_interruptible(&ctrl->queue);
}