drm/i915: move the suspend/resume register file out of dev_priv
dev_priv has grown way too big, and grouping memebers into substructs and moving them out of line helps re-gain some overview. Unfortunatley I couldn't just call the substruct save and drop the prefix, since that will make most member names clash with registers #defines. Changes in i915_drv.h done by hand, everything else changed with s/\<save\([A-Z]*\)/regfile.save\1/ in vim. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter
parent
310c53a84f
commit
f4c956adc7
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@ -397,141 +397,7 @@ struct intel_gmbus {
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struct drm_i915_private *dev_priv;
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};
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typedef struct drm_i915_private {
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struct drm_device *dev;
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const struct intel_device_info *info;
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int relative_constants_mode;
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void __iomem *regs;
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struct drm_i915_gt_funcs gt;
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/** gt_fifo_count and the subsequent register write are synchronized
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* with dev->struct_mutex. */
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unsigned gt_fifo_count;
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/** forcewake_count is protected by gt_lock */
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unsigned forcewake_count;
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/** gt_lock is also taken in irq contexts. */
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struct spinlock gt_lock;
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struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
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/** gmbus_mutex protects against concurrent usage of the single hw gmbus
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* controller on different i2c buses. */
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struct mutex gmbus_mutex;
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/**
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* Base address of the gmbus and gpio block.
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*/
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uint32_t gpio_mmio_base;
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struct pci_dev *bridge_dev;
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struct intel_ring_buffer ring[I915_NUM_RINGS];
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uint32_t next_seqno;
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drm_dma_handle_t *status_page_dmah;
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uint32_t counter;
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struct drm_i915_gem_object *pwrctx;
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struct drm_i915_gem_object *renderctx;
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struct resource mch_res;
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atomic_t irq_received;
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/* protects the irq masks */
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spinlock_t irq_lock;
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/* DPIO indirect register protection */
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spinlock_t dpio_lock;
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/** Cached value of IMR to avoid reads in updating the bitfield */
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u32 pipestat[2];
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u32 irq_mask;
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u32 gt_irq_mask;
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u32 pch_irq_mask;
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u32 hotplug_supported_mask;
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struct work_struct hotplug_work;
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int num_pipe;
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int num_pch_pll;
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/* For hangcheck timer */
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#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
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#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
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struct timer_list hangcheck_timer;
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int hangcheck_count;
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uint32_t last_acthd[I915_NUM_RINGS];
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uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
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unsigned int stop_rings;
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unsigned long cfb_size;
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unsigned int cfb_fb;
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enum plane cfb_plane;
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int cfb_y;
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struct intel_fbc_work *fbc_work;
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struct intel_opregion opregion;
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/* overlay */
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struct intel_overlay *overlay;
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bool sprite_scaling_enabled;
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/* LVDS info */
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int backlight_level; /* restore backlight to this value */
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bool backlight_enabled;
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struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
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struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
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/* Feature bits from the VBIOS */
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unsigned int int_tv_support:1;
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unsigned int lvds_dither:1;
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unsigned int lvds_vbt:1;
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unsigned int int_crt_support:1;
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unsigned int lvds_use_ssc:1;
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unsigned int display_clock_mode:1;
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int lvds_ssc_freq;
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unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
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unsigned int lvds_val; /* used for checking LVDS channel mode */
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struct {
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int rate;
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int lanes;
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int preemphasis;
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int vswing;
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bool initialized;
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bool support;
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int bpp;
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struct edp_power_seq pps;
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} edp;
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bool no_aux_handshake;
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int crt_ddc_pin;
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struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
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int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
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int num_fence_regs; /* 8 on pre-965, 16 otherwise */
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unsigned int fsb_freq, mem_freq, is_ddr3;
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spinlock_t error_lock;
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/* Protected by dev->error_lock. */
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struct drm_i915_error_state *first_error;
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struct work_struct error_work;
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struct completion error_completion;
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struct workqueue_struct *wq;
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/* Display functions */
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struct drm_i915_display_funcs display;
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/* PCH chipset type */
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enum intel_pch pch_type;
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unsigned long quirks;
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/* Register state */
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bool modeset_on_lid;
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struct i915_suspend_saved_registers {
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u8 saveLBB;
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u32 saveDSPACNTR;
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u32 saveDSPBCNTR;
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@ -682,6 +548,142 @@ typedef struct drm_i915_private {
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u32 savePIPEB_LINK_N1;
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u32 saveMCHBAR_RENDER_STANDBY;
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u32 savePCH_PORT_HOTPLUG;
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};
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typedef struct drm_i915_private {
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struct drm_device *dev;
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const struct intel_device_info *info;
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int relative_constants_mode;
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void __iomem *regs;
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struct drm_i915_gt_funcs gt;
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/** gt_fifo_count and the subsequent register write are synchronized
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* with dev->struct_mutex. */
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unsigned gt_fifo_count;
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/** forcewake_count is protected by gt_lock */
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unsigned forcewake_count;
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/** gt_lock is also taken in irq contexts. */
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struct spinlock gt_lock;
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struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
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/** gmbus_mutex protects against concurrent usage of the single hw gmbus
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* controller on different i2c buses. */
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struct mutex gmbus_mutex;
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/**
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* Base address of the gmbus and gpio block.
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*/
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uint32_t gpio_mmio_base;
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struct pci_dev *bridge_dev;
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struct intel_ring_buffer ring[I915_NUM_RINGS];
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uint32_t next_seqno;
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drm_dma_handle_t *status_page_dmah;
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uint32_t counter;
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struct drm_i915_gem_object *pwrctx;
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struct drm_i915_gem_object *renderctx;
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struct resource mch_res;
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atomic_t irq_received;
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/* protects the irq masks */
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spinlock_t irq_lock;
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/* DPIO indirect register protection */
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spinlock_t dpio_lock;
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/** Cached value of IMR to avoid reads in updating the bitfield */
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u32 pipestat[2];
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u32 irq_mask;
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u32 gt_irq_mask;
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u32 pch_irq_mask;
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u32 hotplug_supported_mask;
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struct work_struct hotplug_work;
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int num_pipe;
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int num_pch_pll;
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/* For hangcheck timer */
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#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
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#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
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struct timer_list hangcheck_timer;
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int hangcheck_count;
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uint32_t last_acthd[I915_NUM_RINGS];
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uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
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unsigned int stop_rings;
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unsigned long cfb_size;
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unsigned int cfb_fb;
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enum plane cfb_plane;
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int cfb_y;
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struct intel_fbc_work *fbc_work;
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struct intel_opregion opregion;
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/* overlay */
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struct intel_overlay *overlay;
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bool sprite_scaling_enabled;
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/* LVDS info */
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int backlight_level; /* restore backlight to this value */
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bool backlight_enabled;
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struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
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struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
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/* Feature bits from the VBIOS */
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unsigned int int_tv_support:1;
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unsigned int lvds_dither:1;
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unsigned int lvds_vbt:1;
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unsigned int int_crt_support:1;
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unsigned int lvds_use_ssc:1;
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unsigned int display_clock_mode:1;
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int lvds_ssc_freq;
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unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
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unsigned int lvds_val; /* used for checking LVDS channel mode */
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struct {
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int rate;
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int lanes;
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int preemphasis;
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int vswing;
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bool initialized;
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bool support;
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int bpp;
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struct edp_power_seq pps;
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} edp;
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bool no_aux_handshake;
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int crt_ddc_pin;
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struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
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int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
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int num_fence_regs; /* 8 on pre-965, 16 otherwise */
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unsigned int fsb_freq, mem_freq, is_ddr3;
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spinlock_t error_lock;
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/* Protected by dev->error_lock. */
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struct drm_i915_error_state *first_error;
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struct work_struct error_work;
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struct completion error_completion;
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struct workqueue_struct *wq;
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/* Display functions */
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struct drm_i915_display_funcs display;
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/* PCH chipset type */
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enum intel_pch pch_type;
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unsigned long quirks;
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/* Register state */
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bool modeset_on_lid;
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struct {
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/** Bridge to intel-gtt-ko */
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@ -884,6 +886,8 @@ typedef struct drm_i915_private {
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struct work_struct parity_error_work;
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bool hw_contexts_disabled;
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uint32_t hw_context_size;
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struct i915_suspend_saved_registers regfile;
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} drm_i915_private_t;
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/* Iterate over initialised rings */
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File diff suppressed because it is too large
Load diff
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@ -138,24 +138,24 @@ static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv)
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if (HAS_PCH_SPLIT(dev_priv->dev)) {
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val = I915_READ(BLC_PWM_PCH_CTL2);
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if (dev_priv->saveBLC_PWM_CTL2 == 0) {
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dev_priv->saveBLC_PWM_CTL2 = val;
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if (dev_priv->regfile.saveBLC_PWM_CTL2 == 0) {
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dev_priv->regfile.saveBLC_PWM_CTL2 = val;
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} else if (val == 0) {
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I915_WRITE(BLC_PWM_PCH_CTL2,
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dev_priv->saveBLC_PWM_CTL2);
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val = dev_priv->saveBLC_PWM_CTL2;
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dev_priv->regfile.saveBLC_PWM_CTL2);
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val = dev_priv->regfile.saveBLC_PWM_CTL2;
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}
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} else {
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val = I915_READ(BLC_PWM_CTL);
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if (dev_priv->saveBLC_PWM_CTL == 0) {
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dev_priv->saveBLC_PWM_CTL = val;
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dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
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if (dev_priv->regfile.saveBLC_PWM_CTL == 0) {
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dev_priv->regfile.saveBLC_PWM_CTL = val;
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dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
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} else if (val == 0) {
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I915_WRITE(BLC_PWM_CTL,
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dev_priv->saveBLC_PWM_CTL);
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dev_priv->regfile.saveBLC_PWM_CTL);
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I915_WRITE(BLC_PWM_CTL2,
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dev_priv->saveBLC_PWM_CTL2);
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val = dev_priv->saveBLC_PWM_CTL;
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dev_priv->regfile.saveBLC_PWM_CTL2);
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val = dev_priv->regfile.saveBLC_PWM_CTL;
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}
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}
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