tg3: Code cleanup.
This patch applies cleanups that would otherwise clutter later patches. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: Benjamin Li <benli@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -1002,43 +1002,38 @@ static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
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return cap;
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}
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static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
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static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
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{
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u8 new_tg3_flags = 0;
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u8 flowctrl = 0;
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u32 old_rx_mode = tp->rx_mode;
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u32 old_tx_mode = tp->tx_mode;
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if (tp->link_config.autoneg == AUTONEG_ENABLE &&
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(tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
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if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
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new_tg3_flags = tg3_resolve_flowctrl_1000X(local_adv,
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remote_adv);
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flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
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else
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new_tg3_flags = tg3_resolve_flowctrl_1000T(local_adv,
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remote_adv);
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} else {
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new_tg3_flags = tp->link_config.flowctrl;
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}
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flowctrl = tg3_resolve_flowctrl_1000T(lcladv, rmtadv);
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} else
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flowctrl = tp->link_config.flowctrl;
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tp->link_config.active_flowctrl = new_tg3_flags;
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tp->link_config.active_flowctrl = flowctrl;
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if (new_tg3_flags & TG3_FLOW_CTRL_RX)
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if (flowctrl & TG3_FLOW_CTRL_RX)
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tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
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else
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tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
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if (old_rx_mode != tp->rx_mode) {
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if (old_rx_mode != tp->rx_mode)
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tw32_f(MAC_RX_MODE, tp->rx_mode);
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}
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if (new_tg3_flags & TG3_FLOW_CTRL_TX)
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if (flowctrl & TG3_FLOW_CTRL_TX)
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tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
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else
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tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
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if (old_tx_mode != tp->tx_mode) {
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if (old_tx_mode != tp->tx_mode)
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tw32_f(MAC_TX_MODE, tp->tx_mode);
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}
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}
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static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
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@ -7091,7 +7086,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) ||
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) ||
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761))
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val |= (1 << 29);
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val |= WDMAC_MODE_STATUS_TAG_FIX;
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tw32_f(WDMAC_MODE, val);
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udelay(40);
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@ -11542,14 +11537,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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}
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}
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
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if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
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(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
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tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
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pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
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@ -11833,8 +11822,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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tp->phy_otp = TG3_OTP_DEFAULT;
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}
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
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if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
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tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
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else
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tp->mi_mode = MAC_MI_MODE_BASE;
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@ -1109,6 +1109,7 @@
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#define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100
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#define WDMAC_MODE_LNGREAD_ENAB 0x00000200
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#define WDMAC_MODE_RX_ACCEL 0x00000400
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#define WDMAC_MODE_STATUS_TAG_FIX 0x20000000
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#define WDMAC_STATUS 0x00004c04
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#define WDMAC_STATUS_TGTABORT 0x00000004
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#define WDMAC_STATUS_MSTABORT 0x00000008
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