ASoC: mxs-saif: Fix channel swap for 24-bit format
Playing 24-bit format file leads to channel swap on mx28 and the reason is that the current driver performs one write/read to/from the SAIF_DATA register to trigger the transfer. This approach works fine for S16_LE case because SAIF_DATA is a 32-bit register and thus is capable of storing the 16-bit left and right channels, but for the S24_LE case it can only store one channel, so in order to not lose the FIFO sync an extra read/write is needed. Reported-by: Dan Winner <DWinner@tc-helicon.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Dan Winner <DWinner@tc-helicon.com> Acked-by: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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@ -523,16 +523,24 @@ static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd,
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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/*
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* write a data to saif data register to trigger
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* the transfer
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* write data to saif data register to trigger
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* the transfer.
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* For 24-bit format the 32-bit FIFO register stores
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* only one channel, so we need to write twice.
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* This is also safe for the other non 24-bit formats.
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*/
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__raw_writel(0, saif->base + SAIF_DATA);
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__raw_writel(0, saif->base + SAIF_DATA);
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} else {
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/*
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* read a data from saif data register to trigger
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* the receive
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* read data from saif data register to trigger
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* the receive.
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* For 24-bit format the 32-bit FIFO register stores
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* only one channel, so we need to read twice.
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* This is also safe for the other non 24-bit formats.
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*/
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__raw_readl(saif->base + SAIF_DATA);
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__raw_readl(saif->base + SAIF_DATA);
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}
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master_saif->ongoing = 1;
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