dma: mxs-dma: use global stmp_device functionality
This can get rid of the mach-dependency. Cc: Dan Williams <dan.j.williams@intel.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Huang Shijie <b32955@freescale.com> Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Wolfram Sang <w.sang@pengutronix.de> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Vinod Koul <vinod.koul@intel.com>
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@ -238,6 +238,7 @@ config IMX_DMA
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config MXS_DMA
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config MXS_DMA
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bool "MXS DMA support"
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bool "MXS DMA support"
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depends on SOC_IMX23 || SOC_IMX28
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depends on SOC_IMX23 || SOC_IMX28
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select STMP_DEVICE
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select DMA_ENGINE
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select DMA_ENGINE
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help
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help
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Support the MXS DMA engine. This engine including APBH-DMA
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Support the MXS DMA engine. This engine including APBH-DMA
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@ -23,10 +23,10 @@
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#include <linux/dmaengine.h>
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#include <linux/dmaengine.h>
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#include <linux/delay.h>
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#include <linux/delay.h>
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#include <linux/fsl/mxs-dma.h>
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#include <linux/fsl/mxs-dma.h>
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#include <linux/stmp_device.h>
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#include <asm/irq.h>
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#include <asm/irq.h>
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#include <mach/mxs.h>
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#include <mach/mxs.h>
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#include <mach/common.h>
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#include "dmaengine.h"
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#include "dmaengine.h"
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@ -138,10 +138,10 @@ static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan)
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if (dma_is_apbh() && apbh_is_old())
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if (dma_is_apbh() && apbh_is_old())
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writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL),
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writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL),
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mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
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mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
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else
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else
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writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
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writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
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mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR);
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mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
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}
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}
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static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan)
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static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan)
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@ -170,10 +170,10 @@ static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan)
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/* freeze the channel */
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/* freeze the channel */
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if (dma_is_apbh() && apbh_is_old())
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if (dma_is_apbh() && apbh_is_old())
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writel(1 << chan_id,
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writel(1 << chan_id,
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mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
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mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
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else
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else
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writel(1 << chan_id,
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writel(1 << chan_id,
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mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR);
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mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
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mxs_chan->status = DMA_PAUSED;
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mxs_chan->status = DMA_PAUSED;
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}
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}
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@ -186,10 +186,10 @@ static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan)
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/* unfreeze the channel */
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/* unfreeze the channel */
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if (dma_is_apbh() && apbh_is_old())
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if (dma_is_apbh() && apbh_is_old())
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writel(1 << chan_id,
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writel(1 << chan_id,
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mxs_dma->base + HW_APBHX_CTRL0 + MXS_CLR_ADDR);
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mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR);
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else
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else
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writel(1 << chan_id,
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writel(1 << chan_id,
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mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_CLR_ADDR);
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mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_CLR);
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mxs_chan->status = DMA_IN_PROGRESS;
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mxs_chan->status = DMA_IN_PROGRESS;
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}
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}
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@ -220,11 +220,11 @@ static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
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/* completion status */
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/* completion status */
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stat1 = readl(mxs_dma->base + HW_APBHX_CTRL1);
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stat1 = readl(mxs_dma->base + HW_APBHX_CTRL1);
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stat1 &= MXS_DMA_CHANNELS_MASK;
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stat1 &= MXS_DMA_CHANNELS_MASK;
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writel(stat1, mxs_dma->base + HW_APBHX_CTRL1 + MXS_CLR_ADDR);
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writel(stat1, mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR);
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/* error status */
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/* error status */
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stat2 = readl(mxs_dma->base + HW_APBHX_CTRL2);
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stat2 = readl(mxs_dma->base + HW_APBHX_CTRL2);
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writel(stat2, mxs_dma->base + HW_APBHX_CTRL2 + MXS_CLR_ADDR);
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writel(stat2, mxs_dma->base + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR);
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/*
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/*
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* When both completion and error of termination bits set at the
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* When both completion and error of termination bits set at the
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@ -567,7 +567,7 @@ static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma)
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if (ret)
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if (ret)
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return ret;
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return ret;
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ret = mxs_reset_block(mxs_dma->base);
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ret = stmp_reset_block(mxs_dma->base);
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if (ret)
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if (ret)
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goto err_out;
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goto err_out;
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@ -580,14 +580,14 @@ static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma)
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/* enable apbh burst */
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/* enable apbh burst */
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if (dma_is_apbh()) {
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if (dma_is_apbh()) {
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writel(BM_APBH_CTRL0_APB_BURST_EN,
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writel(BM_APBH_CTRL0_APB_BURST_EN,
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mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
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mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
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writel(BM_APBH_CTRL0_APB_BURST8_EN,
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writel(BM_APBH_CTRL0_APB_BURST8_EN,
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mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
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mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
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}
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}
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/* enable irq for all the channels */
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/* enable irq for all the channels */
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writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS,
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writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS,
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mxs_dma->base + HW_APBHX_CTRL1 + MXS_SET_ADDR);
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mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET);
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err_out:
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err_out:
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clk_disable_unprepare(mxs_dma->clk);
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clk_disable_unprepare(mxs_dma->clk);
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