mvebu drivers changes for v3.12
- MBus devicetree bindings - devbus update for address decoding window, cleanup -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.20 (GNU/Linux) iQEcBAABAgAGBQJSC9AMAAoJEAi3KVZQDZAeEskH+gLbu4awN//ItLxqdOjCffs1 o3N7C21SjAuGrueSxLFcYxLXk6XhM1x3mAEjvvbd1ze1yyKIY21PQGkwtjrxQxr5 DbRtz8slgFte9jnOtUQ9gfSM8Q4PsOT4oPtj6tFc9DREIhX8uZtDxLn5YVNsD1MI hLxKbL9OHUxtwQ6aM7IdyMmYXkmLVaBUZFJ7f86CH8oVRJXLcqYzVdLrOUmbRdBX GpB6hAnSqx2spfAYxI928Od+3PIRVW4qm724t0iLI+8xQmjCxIbIDz8sS2NKVM9G YowJ+im5dUI3Wv7l/huVi/r0mvQJJi6BL36c+O0YJUY7KeKT615zdeG3AekvB5g= =6spO -----END PGP SIGNATURE----- Merge tag 'drivers-3.12' of git://git.infradead.org/linux-mvebu into next/soc From Jason Cooper: mvebu drivers changes for v3.12 - MBus devicetree bindings - devbus update for address decoding window, cleanup * tag 'drivers-3.12' of git://git.infradead.org/linux-mvebu: (35 commits) memory: mvebu-devbus: Remove unused variable ARM: mvebu: Relocate PCIe node in Armada 370 RD board ARM: mvebu: Fix AXP-WiFi-AP DT for MBUS DT binding ARM: mvebu: add support for the AXP WiFi AP board ARM: mvebu: use dts pre-processor for mv78230 PCI: mvebu: Adapt to the new device tree layout bus: mvebu-mbus: Add devicetree binding ARM: kirkwood: Relocate PCIe device tree nodes ARM: kirkwood: Introduce MBUS_ID ARM: kirkwood: Introduce MBus DT node ARM: kirkwood: Use the preprocessor on device tree files ARM: kirkwood: Split DT and legacy MBus initialization ARM: mvebu: Relocate Armada 370/XP PCIe device tree nodes ARM: mvebu: Relocate Armada 370/XP DeviceBus device tree nodes ARM: mvebu: Add BootROM to Armada 370/XP device tree ARM: mvebu: Add MBus to Armada 370/XP device tree ARM: mvebu: Use the preprocessor on Armada 370/XP device tree files ARM: mvebu: Initialize MBus using the DT binding ARM: mvebu: Remove the harcoded BootROM window allocation bus: mvebu-mbus: Factorize Armada 370/XP data structures ... Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
f668adebf4
276
Documentation/devicetree/bindings/bus/mvebu-mbus.txt
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276
Documentation/devicetree/bindings/bus/mvebu-mbus.txt
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@ -0,0 +1,276 @@
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* Marvell MBus
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Required properties:
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- compatible: Should be set to one of the following:
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marvell,armada370-mbus
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marvell,armadaxp-mbus
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marvell,armada370-mbus
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marvell,armadaxp-mbus
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marvell,kirkwood-mbus
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marvell,dove-mbus
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marvell,orion5x-88f5281-mbus
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marvell,orion5x-88f5182-mbus
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marvell,orion5x-88f5181-mbus
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marvell,orion5x-88f6183-mbus
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marvell,mv78xx0-mbus
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- address-cells: Must be '2'. The first cell for the MBus ID encoding,
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the second cell for the address offset within the window.
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- size-cells: Must be '1'.
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- ranges: Must be set up to provide a proper translation for each child.
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See the examples below.
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- controller: Contains a single phandle referring to the MBus controller
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node. This allows to specify the node that contains the
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registers that control the MBus, which is typically contained
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within the internal register window (see below).
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Optional properties:
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- pcie-mem-aperture: This optional property contains the aperture for
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the memory region of the PCIe driver.
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If it's defined, it must encode the base address and
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size for the address decoding windows allocated for
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the PCIe memory region.
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- pcie-io-aperture: Just as explained for the above property, this
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optional property contains the aperture for the
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I/O region of the PCIe driver.
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* Marvell MBus controller
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Required properties:
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- compatible: Should be set to "marvell,mbus-controller".
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- reg: Device's register space.
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Two entries are expected (see the examples below):
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the first one controls the devices decoding window and
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the second one controls the SDRAM decoding window.
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Example:
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soc {
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compatible = "marvell,armada370-mbus", "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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controller = <&mbusc>;
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pcie-mem-aperture = <0xe0000000 0x8000000>;
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pcie-io-aperture = <0xe8000000 0x100000>;
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internal-regs {
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compatible = "simple-bus";
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mbusc: mbus-controller@20000 {
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compatible = "marvell,mbus-controller";
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reg = <0x20000 0x100>, <0x20180 0x20>;
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};
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/* more children ...*/
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};
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};
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** MBus address decoding window specification
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The MBus children address space is comprised of two cells: the first one for
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the window ID and the second one for the offset within the window.
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In order to allow to describe valid and non-valid window entries, the
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following encoding is used:
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0xSIAA0000 0x00oooooo
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Where:
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S = 0x0 for a MBus valid window
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S = 0xf for a non-valid window (see below)
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If S = 0x0, then:
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I = 4-bit window target ID
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AA = windpw attribute
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If S = 0xf, then:
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I = don't care
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AA = 1 for internal register
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Following the above encoding, for each ranges entry for a MBus valid window
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(S = 0x0), an address decoding window is allocated. On the other side,
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entries for translation that do not correspond to valid windows (S = 0xf)
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are skipped.
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soc {
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compatible = "marvell,armada370-mbus", "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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controller = <&mbusc>;
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ranges = <0xf0010000 0 0 0xd0000000 0x100000
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0x01e00000 0 0 0xfff00000 0x100000>;
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bootrom {
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compatible = "marvell,bootrom";
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reg = <0x01e00000 0 0x100000>;
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};
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/* other children */
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...
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internal-regs {
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compatible = "simple-bus";
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ranges = <0 0xf0010000 0 0x100000>;
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mbusc: mbus-controller@20000 {
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compatible = "marvell,mbus-controller";
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reg = <0x20000 0x100>, <0x20180 0x20>;
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};
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/* more children ...*/
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};
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};
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In the shown example, the translation entry in the 'ranges' property is what
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makes the MBus driver create a static decoding window for the corresponding
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given child device. Note that the binding does not require child nodes to be
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present. Of course, child nodes are needed to probe the devices.
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Since each window is identified by its target ID and attribute ID there's
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a special macro that can be use to simplify the translation entries:
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#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
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Using this macro, the above example would be:
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soc {
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compatible = "marvell,armada370-mbus", "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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controller = <&mbusc>;
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ranges = < MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
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MBUS_ID(0x01, 0xe0) 0 0 0xfff00000 0x100000>;
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bootrom {
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compatible = "marvell,bootrom";
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reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
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};
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/* other children */
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...
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internal-regs {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
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mbusc: mbus-controller@20000 {
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compatible = "marvell,mbus-controller";
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reg = <0x20000 0x100>, <0x20180 0x20>;
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};
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/* other children */
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...
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};
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};
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** About the window base address
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Remember the MBus controller allows a great deal of flexibility for choosing
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the decoding window base address. When planning the device tree layout it's
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possible to choose any address as the base address, provided of course there's
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a region large enough available, and with the required alignment.
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Yet in other words: there's nothing preventing us from setting a base address
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of 0xf0000000, or 0xd0000000 for the NOR device shown above, if such region is
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unused.
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** Window allocation policy
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The mbus-node ranges property defines a set of mbus windows that are expected
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to be set by the operating system and that are guaranteed to be free of overlaps
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with one another or with the system memory ranges.
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Each entry in the property refers to exactly one window. If the operating system
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choses to use a different set of mbus windows, it must ensure that any address
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translations performed from downstream devices are adapted accordingly.
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The operating system may insert additional mbus windows that do not conflict
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with the ones listed in the ranges, e.g. for mapping PCIe devices.
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As a special case, the internal register window must be set up by the boot
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loader at the address listed in the ranges property, since access to that region
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is needed to set up the other windows.
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** Example
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See the example below, where a more complete device tree is shown:
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soc {
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compatible = "marvell,armadaxp-mbus", "simple-bus";
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controller = <&mbusc>;
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 /* internal-regs */
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MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
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bootrom {
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compatible = "marvell,bootrom";
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reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
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};
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devbus-bootcs {
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status = "okay";
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ranges = <0 MBUS_ID(0x01, 0x2f) 0 0x8000000>;
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/* NOR */
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nor {
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compatible = "cfi-flash";
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reg = <0 0x8000000>;
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bank-width = <2>;
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};
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};
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pcie-controller {
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compatible = "marvell,armada-xp-pcie";
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status = "okay";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges =
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<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
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0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
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0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
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0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
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0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
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0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
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0x81000800 0 0 MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */>;
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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};
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internal-regs {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
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mbusc: mbus-controller@20000 {
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reg = <0x20000 0x100>, <0x20180 0x20>;
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};
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interrupt-controller@20000 {
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reg = <0x20a00 0x2d0>, <0x21070 0x58>;
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};
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};
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};
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@ -1,6 +1,7 @@
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* Marvell EBU PCIe interfaces
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Mandatory properties:
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- compatible: one of the following values:
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marvell,armada-370-pcie
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marvell,armada-xp-pcie
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@ -10,11 +11,49 @@ Mandatory properties:
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- #interrupt-cells, set to <1>
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- bus-range: PCI bus numbers covered
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- device_type, set to "pci"
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- ranges: ranges for the PCI memory and I/O regions, as well as the
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MMIO registers to control the PCIe interfaces.
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- ranges: ranges describing the MMIO registers to control the PCIe
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interfaces, and ranges describing the MBus windows needed to access
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the memory and I/O regions of each PCIe interface.
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In addition, the Device Tree node must have sub-nodes describing each
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The ranges describing the MMIO registers have the following layout:
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0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
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where:
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* r is a 32-bits value that gives the offset of the MMIO
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registers of this PCIe interface, from the base of the internal
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registers.
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* s is a 32-bits value that give the size of this MMIO
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registers area. This range entry translates the '0x82000000 0 r' PCI
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address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
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of the internal register window (as identified by MBUS_ID(0xf0,
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0x01)).
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The ranges describing the MBus windows have the following layout:
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0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
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where:
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* t is the type of the MBus window (as defined by the standard PCI DT
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bindings), 1 for I/O and 2 for memory.
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* s is the PCI slot that corresponds to this PCIe interface
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* w is the 'target ID' value for the MBus window
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* a the 'attribute' value for the MBus window.
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Since the location and size of the different MBus windows is not fixed in
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hardware, and only determined in runtime, those ranges cover the full first
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4 GB of the physical address space, and do not translate into a valid CPU
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address.
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In addition, the device tree node must have sub-nodes describing each
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PCIe interface, having the following mandatory properties:
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- reg: used only for interrupt mapping, so only the first four bytes
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are used to refer to the correct bus number and device number.
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- assigned-addresses: reference to the MMIO registers used to control
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@ -26,7 +65,8 @@ PCIe interface, having the following mandatory properties:
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- #address-cells, set to <3>
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- #size-cells, set to <2>
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- #interrupt-cells, set to <1>
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- ranges, empty property.
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- ranges, translating the MBus windows ranges of the parent node into
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standard PCI addresses.
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- interrupt-map-mask and interrupt-map, standard PCI properties to
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define the mapping of the PCIe interface to interrupt numbers.
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@ -47,27 +87,50 @@ pcie-controller {
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
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0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
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0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
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0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
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0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
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0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
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0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */
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0x82000000 0 0xd0084000 0xd0084000 0 0x00002000 /* Port 1.1 registers */
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0x82000000 0 0xd0088000 0xd0088000 0 0x00002000 /* Port 1.2 registers */
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0x82000000 0 0xd008c000 0xd008c000 0 0x00002000 /* Port 1.3 registers */
|
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0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
|
||||
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
|
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ranges =
|
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<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
|
||||
0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
|
||||
0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
|
||||
0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
|
||||
0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
|
||||
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
|
||||
0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
|
||||
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
|
||||
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
|
||||
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
|
||||
|
||||
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
|
||||
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
|
||||
0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
|
||||
0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
|
||||
0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
|
||||
0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
|
||||
0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
|
||||
0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
|
||||
|
||||
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
|
||||
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
|
||||
|
||||
0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
|
||||
0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 58>;
|
||||
marvell,pcie-port = <0>;
|
||||
|
@ -78,12 +141,13 @@ pcie-controller {
|
|||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
|
||||
assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 59>;
|
||||
marvell,pcie-port = <0>;
|
||||
|
@ -94,12 +158,13 @@ pcie-controller {
|
|||
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
|
||||
assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 60>;
|
||||
marvell,pcie-port = <0>;
|
||||
|
@ -110,12 +175,13 @@ pcie-controller {
|
|||
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
|
||||
assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x4 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 61>;
|
||||
marvell,pcie-port = <0>;
|
||||
|
@ -126,12 +192,13 @@ pcie-controller {
|
|||
|
||||
pcie@5,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
|
||||
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
|
||||
reg = <0x2800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x5 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 62>;
|
||||
marvell,pcie-port = <1>;
|
||||
|
@ -142,12 +209,13 @@ pcie-controller {
|
|||
|
||||
pcie@6,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
|
||||
assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
|
||||
reg = <0x3000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x6 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 63>;
|
||||
marvell,pcie-port = <1>;
|
||||
|
@ -158,12 +226,13 @@ pcie-controller {
|
|||
|
||||
pcie@7,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
|
||||
assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
|
||||
reg = <0x3800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x7 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 64>;
|
||||
marvell,pcie-port = <1>;
|
||||
|
@ -174,12 +243,13 @@ pcie-controller {
|
|||
|
||||
pcie@8,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
|
||||
assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
|
||||
reg = <0x4000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x8 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 65>;
|
||||
marvell,pcie-port = <1>;
|
||||
|
@ -187,14 +257,16 @@ pcie-controller {
|
|||
clocks = <&gateclk 12>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@9,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
|
||||
assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
|
||||
reg = <0x4800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x9 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 99>;
|
||||
marvell,pcie-port = <2>;
|
||||
|
@ -205,12 +277,13 @@ pcie-controller {
|
|||
|
||||
pcie@10,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
|
||||
assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
|
||||
reg = <0x5000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
|
||||
0x81000000 0 0 0x81000000 0xa 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 103>;
|
||||
marvell,pcie-port = <3>;
|
||||
|
|
|
@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
|
|||
dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
|
||||
armada-370-mirabox.dtb \
|
||||
armada-370-rd.dtb \
|
||||
armada-xp-axpwifiap.dtb \
|
||||
armada-xp-db.dtb \
|
||||
armada-xp-gp.dtb \
|
||||
armada-xp-openblocks-ax3-4.dtb
|
||||
|
|
|
@ -14,7 +14,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "armada-370.dtsi"
|
||||
#include "armada-370.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 370 Evaluation Board";
|
||||
|
@ -30,6 +30,9 @@
|
|||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
|
||||
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
|
||||
|
||||
internal-regs {
|
||||
serial@12000 {
|
||||
clock-frequency = <200000000>;
|
||||
|
|
|
@ -9,7 +9,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "armada-370.dtsi"
|
||||
#include "armada-370.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Globalscale Mirabox";
|
||||
|
@ -25,6 +25,25 @@
|
|||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
|
||||
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/* Internal mini-PCIe connector */
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Connected on the PCB to a USB 3.0 XHCI controller */
|
||||
pcie@2,0 {
|
||||
/* Port 1, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
serial@12000 {
|
||||
clock-frequency = <200000000>;
|
||||
|
@ -120,22 +139,6 @@
|
|||
reg = <0x25>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/* Internal mini-PCIe connector */
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Connected on the PCB to a USB 3.0 XHCI controller */
|
||||
pcie@2,0 {
|
||||
/* Port 1, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -12,7 +12,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "armada-370.dtsi"
|
||||
#include "armada-370.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 370 Reference Design";
|
||||
|
@ -28,6 +28,25 @@
|
|||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
|
||||
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/* Internal mini-PCIe connector */
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Internal mini-PCIe connector */
|
||||
pcie@2,0 {
|
||||
/* Port 1, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
serial@12000 {
|
||||
clock-frequency = <200000000>;
|
||||
|
@ -85,22 +104,6 @@
|
|||
gpios = <&gpio0 6 1>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/* Internal mini-PCIe connector */
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Internal mini-PCIe connector */
|
||||
pcie@2,0 {
|
||||
/* Port 1, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -18,6 +18,8 @@
|
|||
|
||||
/include/ "skeleton64.dtsi"
|
||||
|
||||
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 370 and XP SoC";
|
||||
compatible = "marvell,armada-370-xp";
|
||||
|
@ -38,18 +40,73 @@
|
|||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
controller = <&mbusc>;
|
||||
interrupt-parent = <&mpic>;
|
||||
ranges = <0 0 0xd0000000 0x0100000 /* internal registers */
|
||||
0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>;
|
||||
pcie-mem-aperture = <0xe0000000 0x8000000>;
|
||||
pcie-io-aperture = <0xe8000000 0x100000>;
|
||||
|
||||
devbus-bootcs {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs0 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs1 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs2 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs3 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
|
||||
|
||||
mbusc: mbus-controller@20000 {
|
||||
compatible = "marvell,mbus-controller";
|
||||
reg = <0x20000 0x100>, <0x20180 0x20>;
|
||||
};
|
||||
|
||||
mpic: interrupt-controller@20000 {
|
||||
compatible = "marvell,mpic";
|
||||
|
@ -195,50 +252,6 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-bootcs@10400 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <0x10400 0x8>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs0@10408 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <0x10408 0x8>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs1@10410 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <0x10410 0x8>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs2@10418 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <0x10418 0x8>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs3@10420 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <0x10420 0x8>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -15,7 +15,7 @@
|
|||
* common to all Armada SoCs.
|
||||
*/
|
||||
|
||||
/include/ "armada-370-xp.dtsi"
|
||||
#include "armada-370-xp.dtsi"
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
|
@ -29,8 +29,66 @@
|
|||
};
|
||||
|
||||
soc {
|
||||
ranges = <0 0xd0000000 0x0100000 /* internal registers */
|
||||
0xe0000000 0xe0000000 0x8100000 /* PCIe */>;
|
||||
compatible = "marvell,armada370-mbus", "simple-bus";
|
||||
|
||||
bootrom {
|
||||
compatible = "marvell,bootrom";
|
||||
reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-370-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
|
||||
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
|
||||
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 58>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 62>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 9>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
system-controller@18200 {
|
||||
compatible = "marvell,armada-370-xp-system-controller";
|
||||
|
@ -169,54 +227,6 @@
|
|||
0x18304 0x4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-370-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
|
||||
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
|
||||
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 58>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 62>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 9>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
164
arch/arm/boot/dts/armada-xp-axpwifiap.dts
Normal file
164
arch/arm/boot/dts/armada-xp-axpwifiap.dts
Normal file
|
@ -0,0 +1,164 @@
|
|||
/*
|
||||
* Device Tree file for Marvell RD-AXPWiFiAP.
|
||||
*
|
||||
* Note: this board is shipped with a new generation boot loader that
|
||||
* remaps internal registers at 0xf1000000. Therefore, if earlyprintk
|
||||
* is used, the CONFIG_DEBUG_MVEBU_UART_ALTERNATE option should be
|
||||
* used.
|
||||
*
|
||||
* Copyright (C) 2013 Marvell
|
||||
*
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "armada-xp-mv78230.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell RD-AXPWiFiAP";
|
||||
compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 earlyprintk";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/* First mini-PCIe port */
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Second mini-PCIe port */
|
||||
pcie@2,0 {
|
||||
/* Port 0, Lane 1 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Renesas uPD720202 USB 3.0 controller */
|
||||
pcie@3,0 {
|
||||
/* Port 0, Lane 3 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
pinctrl {
|
||||
pinctrl-0 = <&pmx_phy_int>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
pmx_ge0: pmx-ge0 {
|
||||
marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
|
||||
"mpp4", "mpp5", "mpp6", "mpp7",
|
||||
"mpp8", "mpp9", "mpp10", "mpp11";
|
||||
marvell,function = "ge0";
|
||||
};
|
||||
|
||||
pmx_ge1: pmx-ge1 {
|
||||
marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15",
|
||||
"mpp16", "mpp17", "mpp18", "mpp19",
|
||||
"mpp20", "mpp21", "mpp22", "mpp23";
|
||||
marvell,function = "ge1";
|
||||
};
|
||||
|
||||
pmx_keys: pmx-keys {
|
||||
marvell,pins = "mpp33";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
pmx_spi: pmx-spi {
|
||||
marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39";
|
||||
marvell,function = "spi";
|
||||
};
|
||||
|
||||
pmx_phy_int: pmx-phy-int {
|
||||
marvell,pins = "mpp32";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
serial@12000 {
|
||||
clock-frequency = <250000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@12100 {
|
||||
clock-frequency = <250000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sata@a0000 {
|
||||
nr-ports = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@70000 {
|
||||
pinctrl-0 = <&pmx_ge0>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
ethernet@74000 {
|
||||
pinctrl-0 = <&pmx_ge1>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&pmx_spi>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q128a13";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <108000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-0 = <&pmx_keys>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
button@1 {
|
||||
label = "Factory Reset Button";
|
||||
linux,code = <141>; /* KEY_SETUP */
|
||||
gpios = <&gpio1 1 1>;
|
||||
};
|
||||
};
|
||||
};
|
|
@ -14,7 +14,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "armada-xp-mv78460.dtsi"
|
||||
#include "armada-xp-mv78460.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP Evaluation Board";
|
||||
|
@ -30,9 +30,70 @@
|
|||
};
|
||||
|
||||
soc {
|
||||
ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
|
||||
0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
|
||||
0xf0000000 0 0xf0000000 0x1000000>; /* Device Bus, NOR 16MiB */
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
|
||||
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
|
||||
|
||||
devbus-bootcs {
|
||||
status = "okay";
|
||||
|
||||
/* Device Bus parameters are required */
|
||||
|
||||
/* Read parameters */
|
||||
devbus,bus-width = <8>;
|
||||
devbus,turn-off-ps = <60000>;
|
||||
devbus,badr-skew-ps = <0>;
|
||||
devbus,acc-first-ps = <124000>;
|
||||
devbus,acc-next-ps = <248000>;
|
||||
devbus,rd-setup-ps = <0>;
|
||||
devbus,rd-hold-ps = <0>;
|
||||
|
||||
/* Write parameters */
|
||||
devbus,sync-enable = <0>;
|
||||
devbus,wr-high-ps = <60000>;
|
||||
devbus,wr-low-ps = <60000>;
|
||||
devbus,ale-wr-ps = <60000>;
|
||||
|
||||
/* NOR 16 MiB */
|
||||
nor@0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x1000000>;
|
||||
bank-width = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* All 6 slots are physically present as
|
||||
* standard PCIe slots on the board.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@2,0 {
|
||||
/* Port 0, Lane 1 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@3,0 {
|
||||
/* Port 0, Lane 2 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@4,0 {
|
||||
/* Port 0, Lane 3 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@9,0 {
|
||||
/* Port 2, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@10,0 {
|
||||
/* Port 3, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
serial@12000 {
|
||||
|
@ -127,68 +188,6 @@
|
|||
spi-max-frequency = <20000000>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* All 6 slots are physically present as
|
||||
* standard PCIe slots on the board.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@2,0 {
|
||||
/* Port 0, Lane 1 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@3,0 {
|
||||
/* Port 0, Lane 2 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@4,0 {
|
||||
/* Port 0, Lane 3 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@9,0 {
|
||||
/* Port 2, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@10,0 {
|
||||
/* Port 3, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
devbus-bootcs@10400 {
|
||||
status = "okay";
|
||||
ranges = <0 0xf0000000 0x1000000>;
|
||||
|
||||
/* Device Bus parameters are required */
|
||||
|
||||
/* Read parameters */
|
||||
devbus,bus-width = <8>;
|
||||
devbus,turn-off-ps = <60000>;
|
||||
devbus,badr-skew-ps = <0>;
|
||||
devbus,acc-first-ps = <124000>;
|
||||
devbus,acc-next-ps = <248000>;
|
||||
devbus,rd-setup-ps = <0>;
|
||||
devbus,rd-hold-ps = <0>;
|
||||
|
||||
/* Write parameters */
|
||||
devbus,sync-enable = <0>;
|
||||
devbus,wr-high-ps = <60000>;
|
||||
devbus,wr-low-ps = <60000>;
|
||||
devbus,ale-wr-ps = <60000>;
|
||||
|
||||
/* NOR 16 MiB */
|
||||
nor@0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x1000000>;
|
||||
bank-width = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -14,7 +14,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "armada-xp-mv78460.dtsi"
|
||||
#include "armada-xp-mv78460.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP Development Board DB-MV784MP-GP";
|
||||
|
@ -39,9 +39,58 @@
|
|||
};
|
||||
|
||||
soc {
|
||||
ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
|
||||
0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
|
||||
0xf0000000 0 0xf0000000 0x1000000 /* Device Bus, NOR 16MiB */>;
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
|
||||
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
|
||||
|
||||
devbus-bootcs {
|
||||
status = "okay";
|
||||
|
||||
/* Device Bus parameters are required */
|
||||
|
||||
/* Read parameters */
|
||||
devbus,bus-width = <8>;
|
||||
devbus,turn-off-ps = <60000>;
|
||||
devbus,badr-skew-ps = <0>;
|
||||
devbus,acc-first-ps = <124000>;
|
||||
devbus,acc-next-ps = <248000>;
|
||||
devbus,rd-setup-ps = <0>;
|
||||
devbus,rd-hold-ps = <0>;
|
||||
|
||||
/* Write parameters */
|
||||
devbus,sync-enable = <0>;
|
||||
devbus,wr-high-ps = <60000>;
|
||||
devbus,wr-low-ps = <60000>;
|
||||
devbus,ale-wr-ps = <60000>;
|
||||
|
||||
/* NOR 16 MiB */
|
||||
nor@0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x1000000>;
|
||||
bank-width = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* The 3 slots are physically present as
|
||||
* standard PCIe slots on the board.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@9,0 {
|
||||
/* Port 2, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@10,0 {
|
||||
/* Port 3, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
serial@12000 {
|
||||
|
@ -126,56 +175,6 @@
|
|||
spi-max-frequency = <108000000>;
|
||||
};
|
||||
};
|
||||
|
||||
devbus-bootcs@10400 {
|
||||
status = "okay";
|
||||
ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
|
||||
|
||||
/* Device Bus parameters are required */
|
||||
|
||||
/* Read parameters */
|
||||
devbus,bus-width = <8>;
|
||||
devbus,turn-off-ps = <60000>;
|
||||
devbus,badr-skew-ps = <0>;
|
||||
devbus,acc-first-ps = <124000>;
|
||||
devbus,acc-next-ps = <248000>;
|
||||
devbus,rd-setup-ps = <0>;
|
||||
devbus,rd-hold-ps = <0>;
|
||||
|
||||
/* Write parameters */
|
||||
devbus,sync-enable = <0>;
|
||||
devbus,wr-high-ps = <60000>;
|
||||
devbus,wr-low-ps = <60000>;
|
||||
devbus,ale-wr-ps = <60000>;
|
||||
|
||||
/* NOR 16 MiB */
|
||||
nor@0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x1000000>;
|
||||
bank-width = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* The 3 slots are physically present as
|
||||
* standard PCIe slots on the board.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@9,0 {
|
||||
/* Port 2, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@10,0 {
|
||||
/* Port 3, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -13,7 +13,7 @@
|
|||
* common to all Armada XP SoCs.
|
||||
*/
|
||||
|
||||
/include/ "armada-xp.dtsi"
|
||||
#include "armada-xp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP MV78230 SoC";
|
||||
|
@ -44,6 +44,124 @@
|
|||
};
|
||||
|
||||
soc {
|
||||
/*
|
||||
* MV78230 has 2 PCIe units Gen2.0: One unit can be
|
||||
* configured as x4 or quad x1 lanes. One unit is
|
||||
* x4/x1.
|
||||
*/
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-xp-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
|
||||
0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
|
||||
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
|
||||
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
|
||||
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
|
||||
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
|
||||
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 58>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 59>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 60>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x4 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 61>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@9,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
|
||||
reg = <0x4800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x9 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 99>;
|
||||
marvell,pcie-port = <2>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 26>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
pinctrl {
|
||||
compatible = "marvell,mv78230-pinctrl";
|
||||
|
@ -77,110 +195,6 @@
|
|||
#interrupts-cells = <2>;
|
||||
interrupts = <87>, <88>, <89>;
|
||||
};
|
||||
|
||||
/*
|
||||
* MV78230 has 2 PCIe units Gen2.0: One unit can be
|
||||
* configured as x4 or quad x1 lanes. One unit is
|
||||
* x4/x1.
|
||||
*/
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-xp-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
|
||||
0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
|
||||
0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
|
||||
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 58>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 59>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 60>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 61>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@9,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
|
||||
reg = <0x4800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 99>;
|
||||
marvell,pcie-port = <2>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 26>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -13,7 +13,7 @@
|
|||
* common to all Armada XP SoCs.
|
||||
*/
|
||||
|
||||
/include/ "armada-xp.dtsi"
|
||||
#include "armada-xp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP MV78260 SoC";
|
||||
|
@ -45,6 +45,145 @@
|
|||
};
|
||||
|
||||
soc {
|
||||
/*
|
||||
* MV78260 has 3 PCIe units Gen2.0: Two units can be
|
||||
* configured as x4 or quad x1 lanes. One unit is
|
||||
* x4/x1.
|
||||
*/
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-xp-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
|
||||
0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
|
||||
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
|
||||
0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
|
||||
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
|
||||
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
|
||||
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
|
||||
0x82000000 0x9 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
|
||||
0x81000000 0x9 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
|
||||
0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
|
||||
0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 58>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 59>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 60>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x4 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 61>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@9,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
|
||||
reg = <0x4800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x9 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 99>;
|
||||
marvell,pcie-port = <2>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 26>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@10,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
|
||||
reg = <0x5000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
|
||||
0x81000000 0 0 0x81000000 0xa 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 103>;
|
||||
marvell,pcie-port = <3>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 27>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
pinctrl {
|
||||
compatible = "marvell,mv78260-pinctrl";
|
||||
|
@ -97,128 +236,6 @@
|
|||
clocks = <&gateclk 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/*
|
||||
* MV78260 has 3 PCIe units Gen2.0: Two units can be
|
||||
* configured as x4 or quad x1 lanes. One unit is
|
||||
* x4/x1.
|
||||
*/
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-xp-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
|
||||
0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
|
||||
0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
|
||||
0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
|
||||
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
|
||||
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 58>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 59>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 60>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 61>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@9,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
|
||||
reg = <0x4800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 99>;
|
||||
marvell,pcie-port = <2>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 26>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@10,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
|
||||
reg = <0x5000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 103>;
|
||||
marvell,pcie-port = <3>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 27>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -13,7 +13,7 @@
|
|||
* common to all Armada XP SoCs.
|
||||
*/
|
||||
|
||||
/include/ "armada-xp.dtsi"
|
||||
#include "armada-xp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP MV78460 SoC";
|
||||
|
@ -61,6 +61,227 @@
|
|||
};
|
||||
|
||||
soc {
|
||||
/*
|
||||
* MV78460 has 4 PCIe units Gen2.0: Two units can be
|
||||
* configured as x4 or quad x1 lanes. Two units are
|
||||
* x4/x1.
|
||||
*/
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-xp-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
|
||||
0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
|
||||
0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
|
||||
0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
|
||||
0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
|
||||
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
|
||||
0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
|
||||
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
|
||||
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
|
||||
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
|
||||
|
||||
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
|
||||
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
|
||||
0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
|
||||
0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
|
||||
0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
|
||||
0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
|
||||
0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
|
||||
0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
|
||||
|
||||
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
|
||||
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
|
||||
|
||||
0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
|
||||
0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 58>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 59>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 60>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x4 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 61>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@5,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
|
||||
reg = <0x2800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x5 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 62>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 9>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@6,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
|
||||
reg = <0x3000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x6 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 63>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 10>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@7,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
|
||||
reg = <0x3800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x7 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 64>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 11>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@8,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
|
||||
reg = <0x4000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x8 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 65>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 12>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@9,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
|
||||
reg = <0x4800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x9 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 99>;
|
||||
marvell,pcie-port = <2>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 26>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@10,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
|
||||
reg = <0x5000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
|
||||
0x81000000 0 0 0x81000000 0xa 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 103>;
|
||||
marvell,pcie-port = <3>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 27>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
pinctrl {
|
||||
compatible = "marvell,mv78460-pinctrl";
|
||||
|
@ -113,194 +334,6 @@
|
|||
clocks = <&gateclk 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/*
|
||||
* MV78460 has 4 PCIe units Gen2.0: Two units can be
|
||||
* configured as x4 or quad x1 lanes. Two units are
|
||||
* x4/x1.
|
||||
*/
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-xp-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
|
||||
0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
|
||||
0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
|
||||
0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
|
||||
0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */
|
||||
0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */
|
||||
0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */
|
||||
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
|
||||
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 58>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 59>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 60>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 61>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@5,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
|
||||
reg = <0x2800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 62>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 9>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@6,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
|
||||
reg = <0x3000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 63>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 10>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@7,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
|
||||
reg = <0x3800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 64>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 11>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@8,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
|
||||
reg = <0x4000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 65>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 12>;
|
||||
status = "disabled";
|
||||
};
|
||||
pcie@9,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
|
||||
reg = <0x4800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 99>;
|
||||
marvell,pcie-port = <2>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 26>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@10,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
|
||||
reg = <0x5000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 103>;
|
||||
marvell,pcie-port = <3>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 27>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -11,7 +11,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "armada-xp-mv78260.dtsi"
|
||||
#include "armada-xp-mv78260.dtsi"
|
||||
|
||||
/ {
|
||||
model = "PlatHome OpenBlocks AX3-4 board";
|
||||
|
@ -27,9 +27,46 @@
|
|||
};
|
||||
|
||||
soc {
|
||||
ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
|
||||
0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
|
||||
0xf0000000 0 0xf0000000 0x8000000 /* Device Bus, NOR 128MiB */>;
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
|
||||
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
|
||||
|
||||
devbus-bootcs {
|
||||
status = "okay";
|
||||
|
||||
/* Device Bus parameters are required */
|
||||
|
||||
/* Read parameters */
|
||||
devbus,bus-width = <8>;
|
||||
devbus,turn-off-ps = <60000>;
|
||||
devbus,badr-skew-ps = <0>;
|
||||
devbus,acc-first-ps = <124000>;
|
||||
devbus,acc-next-ps = <248000>;
|
||||
devbus,rd-setup-ps = <0>;
|
||||
devbus,rd-hold-ps = <0>;
|
||||
|
||||
/* Write parameters */
|
||||
devbus,sync-enable = <0>;
|
||||
devbus,wr-high-ps = <60000>;
|
||||
devbus,wr-low-ps = <60000>;
|
||||
devbus,ale-wr-ps = <60000>;
|
||||
|
||||
/* NOR 128 MiB */
|
||||
nor@0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x8000000>;
|
||||
bank-width = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
/* Internal mini-PCIe connector */
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
serial@12000 {
|
||||
|
@ -148,49 +185,6 @@
|
|||
usb@51000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* USB interface in the mini-PCIe connector */
|
||||
usb@52000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
devbus-bootcs@10400 {
|
||||
status = "okay";
|
||||
ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
|
||||
|
||||
/* Device Bus parameters are required */
|
||||
|
||||
/* Read parameters */
|
||||
devbus,bus-width = <8>;
|
||||
devbus,turn-off-ps = <60000>;
|
||||
devbus,badr-skew-ps = <0>;
|
||||
devbus,acc-first-ps = <124000>;
|
||||
devbus,acc-next-ps = <248000>;
|
||||
devbus,rd-setup-ps = <0>;
|
||||
devbus,rd-hold-ps = <0>;
|
||||
|
||||
/* Write parameters */
|
||||
devbus,sync-enable = <0>;
|
||||
devbus,wr-high-ps = <60000>;
|
||||
devbus,wr-low-ps = <60000>;
|
||||
devbus,ale-wr-ps = <60000>;
|
||||
|
||||
/* NOR 128 MiB */
|
||||
nor@0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x8000000>;
|
||||
bank-width = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
/* Internal mini-PCIe connector */
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -16,7 +16,7 @@
|
|||
* common to all Armada SoCs.
|
||||
*/
|
||||
|
||||
/include/ "armada-370-xp.dtsi"
|
||||
#include "armada-370-xp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP family SoC";
|
||||
|
@ -27,6 +27,13 @@
|
|||
};
|
||||
|
||||
soc {
|
||||
compatible = "marvell,armadaxp-mbus", "simple-bus";
|
||||
|
||||
bootrom {
|
||||
compatible = "marvell,bootrom";
|
||||
reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
L2: l2-cache {
|
||||
compatible = "marvell,aurora-system-cache";
|
||||
|
|
|
@ -1,4 +1,39 @@
|
|||
/ {
|
||||
mbus {
|
||||
pcie-controller {
|
||||
compatible = "marvell,kirkwood-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
|
||||
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &intc 9>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gate_clk 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ocp@f1000000 {
|
||||
pinctrl: pinctrl@10000 {
|
||||
compatible = "marvell,88f6281-pinctrl";
|
||||
|
@ -41,37 +76,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
compatible = "marvell,kirkwood-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
|
||||
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &intc 9>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gate_clk 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
rtc@10300 {
|
||||
compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
|
||||
reg = <0x10300 0x20>;
|
||||
|
|
|
@ -1,4 +1,59 @@
|
|||
/ {
|
||||
mbus {
|
||||
pcie-controller {
|
||||
compatible = "marvell,kirkwood-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
|
||||
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
|
||||
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>;
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &intc 9>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gate_clk 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &intc 10>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gate_clk 18>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
ocp@f1000000 {
|
||||
|
||||
pinctrl: pinctrl@10000 {
|
||||
|
@ -94,52 +149,5 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
compatible = "marvell,kirkwood-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0x00044000 0x00044000 0 0x00002000 /* Port 1.0 registers */
|
||||
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
|
||||
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &intc 9>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gate_clk 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &intc 10>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gate_clk 18>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood.dtsi"
|
||||
/include/ "kirkwood-6281.dtsi"
|
||||
#include "kirkwood.dtsi"
|
||||
#include "kirkwood-6281.dtsi"
|
||||
|
||||
/ {
|
||||
model = "LaCie CloudBox";
|
||||
|
|
|
@ -11,14 +11,15 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood-db.dtsi"
|
||||
/include/ "kirkwood-6281.dtsi"
|
||||
#include "kirkwood-db.dtsi"
|
||||
#include "kirkwood-6281.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell DB-88F6281-BP Development Board";
|
||||
compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood";
|
||||
|
||||
ocp@f1000000 {
|
||||
mbus {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
|
|
|
@ -11,14 +11,15 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood-db.dtsi"
|
||||
/include/ "kirkwood-6282.dtsi"
|
||||
#include "kirkwood-db.dtsi"
|
||||
#include "kirkwood-6282.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell DB-88F6282-BP Development Board";
|
||||
compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood";
|
||||
|
||||
ocp@f1000000 {
|
||||
mbus {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
|
|
|
@ -12,7 +12,7 @@
|
|||
* and 6282 variants of the Marvell Kirkwood Development Board.
|
||||
*/
|
||||
|
||||
/include/ "kirkwood.dtsi"
|
||||
#include "kirkwood.dtsi"
|
||||
|
||||
/ {
|
||||
memory {
|
||||
|
@ -77,13 +77,5 @@
|
|||
cd-gpios = <&gpio1 6 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
pcie@1,0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood-dnskw.dtsi"
|
||||
#include "kirkwood-dnskw.dtsi"
|
||||
|
||||
/ {
|
||||
model = "D-Link DNS-320 NAS (Rev A1)";
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood-dnskw.dtsi"
|
||||
#include "kirkwood-dnskw.dtsi"
|
||||
|
||||
/ {
|
||||
model = "D-Link DNS-325 NAS (Rev A1)";
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/include/ "kirkwood.dtsi"
|
||||
/include/ "kirkwood-6281.dtsi"
|
||||
#include "kirkwood.dtsi"
|
||||
#include "kirkwood-6281.dtsi"
|
||||
|
||||
/ {
|
||||
model = "D-Link DNS NASes (kirkwood-based)";
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood.dtsi"
|
||||
/include/ "kirkwood-6281.dtsi"
|
||||
#include "kirkwood.dtsi"
|
||||
#include "kirkwood-6281.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Seagate FreeAgent Dockstar";
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood.dtsi"
|
||||
/include/ "kirkwood-6281.dtsi"
|
||||
#include "kirkwood.dtsi"
|
||||
#include "kirkwood-6281.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Globalscale Technologies Dreamplug";
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood.dtsi"
|
||||
/include/ "kirkwood-6281.dtsi"
|
||||
#include "kirkwood.dtsi"
|
||||
#include "kirkwood-6281.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Seagate GoFlex Net";
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood.dtsi"
|
||||
/include/ "kirkwood-6281.dtsi"
|
||||
#include "kirkwood.dtsi"
|
||||
#include "kirkwood-6281.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Globalscale Technologies Guruplug Server Plus";
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood.dtsi"
|
||||
/include/ "kirkwood-6281.dtsi"
|
||||
#include "kirkwood.dtsi"
|
||||
#include "kirkwood-6281.dtsi"
|
||||
|
||||
/ {
|
||||
model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)";
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood.dtsi"
|
||||
/include/ "kirkwood-6281.dtsi"
|
||||
#include "kirkwood.dtsi"
|
||||
#include "kirkwood-6281.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Iomega Iconnect";
|
||||
|
@ -18,6 +18,17 @@
|
|||
linux,initrd-end = <0x4800000>;
|
||||
};
|
||||
|
||||
mbus {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
pcie@1,0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ocp@f1000000 {
|
||||
pinctrl: pinctrl@10000 {
|
||||
pmx_button_reset: pmx-button-reset {
|
||||
|
@ -101,14 +112,6 @@
|
|||
reg = <0x980000 0x1f400000>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
pcie@1,0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood.dtsi"
|
||||
/include/ "kirkwood-6281.dtsi"
|
||||
#include "kirkwood.dtsi"
|
||||
#include "kirkwood-6281.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Iomega StorCenter ix2-200";
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood-ns2-common.dtsi"
|
||||
#include "kirkwood-ns2-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "LaCie Internet Space v2";
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood.dtsi"
|
||||
/include/ "kirkwood-98dx4122.dtsi"
|
||||
#include "kirkwood.dtsi"
|
||||
#include "kirkwood-98dx4122.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Keymile Kirkwood Reference Design";
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood-lsxl.dtsi"
|
||||
#include "kirkwood-lsxl.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Buffalo Linkstation LS-CHLv2";
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood-lsxl.dtsi"
|
||||
#include "kirkwood-lsxl.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Buffalo Linkstation LS-XHL";
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/include/ "kirkwood.dtsi"
|
||||
/include/ "kirkwood-6281.dtsi"
|
||||
#include "kirkwood.dtsi"
|
||||
#include "kirkwood-6281.dtsi"
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood.dtsi"
|
||||
/include/ "kirkwood-6281.dtsi"
|
||||
#include "kirkwood.dtsi"
|
||||
#include "kirkwood-6281.dtsi"
|
||||
|
||||
/ {
|
||||
model = "MPL CEC4";
|
||||
|
@ -16,6 +16,17 @@
|
|||
bootargs = "console=ttyS0,115200n8 earlyprintk";
|
||||
};
|
||||
|
||||
mbus {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
pcie@1,0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ocp@f1000000 {
|
||||
pinctrl: pinctrl@10000 {
|
||||
pmx_led_health: pmx-led-health {
|
||||
|
@ -134,14 +145,6 @@
|
|||
cd-gpios = <&gpio1 15 1>;
|
||||
/* No WP GPIO */
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
pcie@1,0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood.dtsi"
|
||||
/include/ "kirkwood-6282.dtsi"
|
||||
#include "kirkwood.dtsi"
|
||||
#include "kirkwood-6282.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NETGEAR ReadyNAS Duo v2";
|
||||
|
@ -16,6 +16,17 @@
|
|||
bootargs = "console=ttyS0,115200n8 earlyprintk";
|
||||
};
|
||||
|
||||
mbus {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
pcie@1,0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ocp@f1000000 {
|
||||
pinctrl: pinctrl@10000 {
|
||||
pmx_button_power: pmx-button-power {
|
||||
|
@ -101,14 +112,6 @@
|
|||
status = "okay";
|
||||
nr-ports = <2>;
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
pcie@1,0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/include/ "kirkwood.dtsi"
|
||||
/include/ "kirkwood-6281.dtsi"
|
||||
#include "kirkwood.dtsi"
|
||||
#include "kirkwood-6281.dtsi"
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood-ns2-common.dtsi"
|
||||
#include "kirkwood-ns2-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "LaCie Network Space v2";
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood-ns2-common.dtsi"
|
||||
#include "kirkwood-ns2-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "LaCie Network Space Lite v2";
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood-ns2-common.dtsi"
|
||||
#include "kirkwood-ns2-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "LaCie Network Space Max v2";
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood-ns2-common.dtsi"
|
||||
#include "kirkwood-ns2-common.dtsi"
|
||||
|
||||
/ {
|
||||
/* This machine is embedded in the first LaCie CloudBox product. */
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood.dtsi"
|
||||
/include/ "kirkwood-6281.dtsi"
|
||||
#include "kirkwood.dtsi"
|
||||
#include "kirkwood-6281.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ZyXEL NSA310";
|
||||
|
@ -16,6 +16,17 @@
|
|||
bootargs = "console=ttyS0,115200";
|
||||
};
|
||||
|
||||
mbus {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
pcie@1,0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ocp@f1000000 {
|
||||
pinctrl: pinctrl@10000 {
|
||||
pinctrl-0 = <&pmx_unknown>;
|
||||
|
@ -162,14 +173,6 @@
|
|||
reg = <0x5040000 0x2fc0000>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
pcie@1,0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood.dtsi"
|
||||
/include/ "kirkwood-6282.dtsi"
|
||||
#include "kirkwood.dtsi"
|
||||
#include "kirkwood-6282.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Plat'Home OpenBlocksA6";
|
||||
|
|
|
@ -6,8 +6,8 @@
|
|||
* Licensed under GPLv2
|
||||
*/
|
||||
|
||||
/include/ "kirkwood.dtsi"
|
||||
/include/ "kirkwood-6281.dtsi"
|
||||
#include "kirkwood.dtsi"
|
||||
#include "kirkwood-6281.dtsi"
|
||||
|
||||
/ {
|
||||
memory {
|
||||
|
|
|
@ -8,7 +8,7 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood-sheevaplug-common.dtsi"
|
||||
#include "kirkwood-sheevaplug-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Globalscale Technologies eSATA SheevaPlug";
|
||||
|
|
|
@ -8,7 +8,7 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood-sheevaplug-common.dtsi"
|
||||
#include "kirkwood-sheevaplug-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Globalscale Technologies SheevaPlug";
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood.dtsi"
|
||||
/include/ "kirkwood-6282.dtsi"
|
||||
#include "kirkwood.dtsi"
|
||||
#include "kirkwood-6282.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Univeral Scientific Industrial Co. Topkick-1281P2";
|
||||
|
|
|
@ -1,8 +1,8 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood.dtsi"
|
||||
/include/ "kirkwood-6281.dtsi"
|
||||
/include/ "kirkwood-ts219.dtsi"
|
||||
#include "kirkwood.dtsi"
|
||||
#include "kirkwood-6281.dtsi"
|
||||
#include "kirkwood-ts219.dtsi"
|
||||
|
||||
/ {
|
||||
ocp@f1000000 {
|
||||
|
|
|
@ -1,10 +1,21 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood.dtsi"
|
||||
/include/ "kirkwood-6282.dtsi"
|
||||
/include/ "kirkwood-ts219.dtsi"
|
||||
#include "kirkwood.dtsi"
|
||||
#include "kirkwood-6282.dtsi"
|
||||
#include "kirkwood-ts219.dtsi"
|
||||
|
||||
/ {
|
||||
mbus {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
pcie@2,0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ocp@f1000000 {
|
||||
pinctrl: pinctrl@10000 {
|
||||
|
||||
|
@ -30,14 +41,6 @@
|
|||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
pcie@2,0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
|
|
|
@ -11,6 +11,16 @@
|
|||
bootargs = "console=ttyS0,115200n8";
|
||||
};
|
||||
|
||||
mbus {
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
pcie@1,0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ocp@f1000000 {
|
||||
i2c@11000 {
|
||||
status = "okay";
|
||||
|
@ -87,12 +97,5 @@
|
|||
status = "okay";
|
||||
nr-ports = <2>;
|
||||
};
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
pcie@1,0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -1,5 +1,7 @@
|
|||
/include/ "skeleton.dtsi"
|
||||
|
||||
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
|
||||
|
||||
/ {
|
||||
compatible = "marvell,kirkwood";
|
||||
interrupt-parent = <&intc>;
|
||||
|
@ -28,15 +30,28 @@
|
|||
<0xf1020214 0x04>;
|
||||
};
|
||||
|
||||
mbus {
|
||||
compatible = "marvell,kirkwood-mbus", "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
controller = <&mbusc>;
|
||||
pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
|
||||
pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
|
||||
};
|
||||
|
||||
ocp@f1000000 {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x00000000 0xf1000000 0x0100000
|
||||
0xe0000000 0xe0000000 0x8100000 /* PCIE */
|
||||
0xf4000000 0xf4000000 0x0000400
|
||||
0xf5000000 0xf5000000 0x0000400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
mbusc: mbus-controller@20000 {
|
||||
compatible = "marvell,mbus-controller";
|
||||
reg = <0x20000 0x80>, <0x1500 0x20>;
|
||||
};
|
||||
|
||||
core_clk: core-clocks@10030 {
|
||||
compatible = "marvell,kirkwood-core-clock";
|
||||
reg = <0x10030 0x4>;
|
||||
|
|
|
@ -27,6 +27,22 @@
|
|||
#include <plat/time.h>
|
||||
#include "common.h"
|
||||
|
||||
/* These can go away once Dove uses the mvebu-mbus DT binding */
|
||||
#define DOVE_MBUS_PCIE0_MEM_TARGET 0x4
|
||||
#define DOVE_MBUS_PCIE0_MEM_ATTR 0xe8
|
||||
#define DOVE_MBUS_PCIE0_IO_TARGET 0x4
|
||||
#define DOVE_MBUS_PCIE0_IO_ATTR 0xe0
|
||||
#define DOVE_MBUS_PCIE1_MEM_TARGET 0x8
|
||||
#define DOVE_MBUS_PCIE1_MEM_ATTR 0xe8
|
||||
#define DOVE_MBUS_PCIE1_IO_TARGET 0x8
|
||||
#define DOVE_MBUS_PCIE1_IO_ATTR 0xe0
|
||||
#define DOVE_MBUS_CESA_TARGET 0x3
|
||||
#define DOVE_MBUS_CESA_ATTR 0x1
|
||||
#define DOVE_MBUS_BOOTROM_TARGET 0x1
|
||||
#define DOVE_MBUS_BOOTROM_ATTR 0xfd
|
||||
#define DOVE_MBUS_SCRATCHPAD_TARGET 0xd
|
||||
#define DOVE_MBUS_SCRATCHPAD_ATTR 0x0
|
||||
|
||||
/*****************************************************************************
|
||||
* I/O Address Mapping
|
||||
****************************************************************************/
|
||||
|
@ -332,34 +348,40 @@ void __init dove_setup_cpu_wins(void)
|
|||
{
|
||||
/*
|
||||
* The PCIe windows will no longer be statically allocated
|
||||
* here once Dove is migrated to the pci-mvebu driver.
|
||||
* here once Dove is migrated to the pci-mvebu driver. The
|
||||
* non-PCIe windows will no longer be created here once Dove
|
||||
* fully moves to DT.
|
||||
*/
|
||||
mvebu_mbus_add_window_remap_flags("pcie0.0",
|
||||
mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET,
|
||||
DOVE_MBUS_PCIE0_IO_ATTR,
|
||||
DOVE_PCIE0_IO_PHYS_BASE,
|
||||
DOVE_PCIE0_IO_SIZE,
|
||||
DOVE_PCIE0_IO_BUS_BASE,
|
||||
MVEBU_MBUS_PCI_IO);
|
||||
mvebu_mbus_add_window_remap_flags("pcie1.0",
|
||||
DOVE_PCIE0_IO_BUS_BASE);
|
||||
mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET,
|
||||
DOVE_MBUS_PCIE1_IO_ATTR,
|
||||
DOVE_PCIE1_IO_PHYS_BASE,
|
||||
DOVE_PCIE1_IO_SIZE,
|
||||
DOVE_PCIE1_IO_BUS_BASE,
|
||||
MVEBU_MBUS_PCI_IO);
|
||||
mvebu_mbus_add_window_remap_flags("pcie0.0",
|
||||
DOVE_PCIE0_MEM_PHYS_BASE,
|
||||
DOVE_PCIE0_MEM_SIZE,
|
||||
MVEBU_MBUS_NO_REMAP,
|
||||
MVEBU_MBUS_PCI_MEM);
|
||||
mvebu_mbus_add_window_remap_flags("pcie1.0",
|
||||
DOVE_PCIE1_MEM_PHYS_BASE,
|
||||
DOVE_PCIE1_MEM_SIZE,
|
||||
MVEBU_MBUS_NO_REMAP,
|
||||
MVEBU_MBUS_PCI_MEM);
|
||||
mvebu_mbus_add_window("cesa", DOVE_CESA_PHYS_BASE,
|
||||
DOVE_CESA_SIZE);
|
||||
mvebu_mbus_add_window("bootrom", DOVE_BOOTROM_PHYS_BASE,
|
||||
DOVE_BOOTROM_SIZE);
|
||||
mvebu_mbus_add_window("scratchpad", DOVE_SCRATCHPAD_PHYS_BASE,
|
||||
DOVE_SCRATCHPAD_SIZE);
|
||||
DOVE_PCIE1_IO_BUS_BASE);
|
||||
mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET,
|
||||
DOVE_MBUS_PCIE0_MEM_ATTR,
|
||||
DOVE_PCIE0_MEM_PHYS_BASE,
|
||||
DOVE_PCIE0_MEM_SIZE);
|
||||
mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET,
|
||||
DOVE_MBUS_PCIE1_MEM_ATTR,
|
||||
DOVE_PCIE1_MEM_PHYS_BASE,
|
||||
DOVE_PCIE1_MEM_SIZE);
|
||||
mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET,
|
||||
DOVE_MBUS_CESA_ATTR,
|
||||
DOVE_CESA_PHYS_BASE,
|
||||
DOVE_CESA_SIZE);
|
||||
mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET,
|
||||
DOVE_MBUS_BOOTROM_ATTR,
|
||||
DOVE_BOOTROM_PHYS_BASE,
|
||||
DOVE_BOOTROM_SIZE);
|
||||
mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET,
|
||||
DOVE_MBUS_SCRATCHPAD_ATTR,
|
||||
DOVE_SCRATCHPAD_PHYS_BASE,
|
||||
DOVE_SCRATCHPAD_SIZE);
|
||||
}
|
||||
|
||||
void __init dove_init(void)
|
||||
|
|
|
@ -87,6 +87,7 @@ static void __init kirkwood_dt_init(void)
|
|||
*/
|
||||
writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
|
||||
|
||||
BUG_ON(mvebu_mbus_dt_init());
|
||||
kirkwood_setup_wins();
|
||||
|
||||
kirkwood_l2_init();
|
||||
|
|
|
@ -37,6 +37,12 @@
|
|||
#include <linux/platform_data/dma-mv_xor.h>
|
||||
#include "common.h"
|
||||
|
||||
/* These can go away once Kirkwood uses the mvebu-mbus DT binding */
|
||||
#define KIRKWOOD_MBUS_NAND_TARGET 0x01
|
||||
#define KIRKWOOD_MBUS_NAND_ATTR 0x2f
|
||||
#define KIRKWOOD_MBUS_SRAM_TARGET 0x03
|
||||
#define KIRKWOOD_MBUS_SRAM_ATTR 0x01
|
||||
|
||||
/*****************************************************************************
|
||||
* I/O Address Mapping
|
||||
****************************************************************************/
|
||||
|
@ -528,10 +534,6 @@ void __init kirkwood_cpuidle_init(void)
|
|||
void __init kirkwood_init_early(void)
|
||||
{
|
||||
orion_time_set_base(TIMER_VIRT_BASE);
|
||||
|
||||
mvebu_mbus_init("marvell,kirkwood-mbus",
|
||||
BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
|
||||
DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ);
|
||||
}
|
||||
|
||||
int kirkwood_tclk;
|
||||
|
@ -672,10 +674,14 @@ char * __init kirkwood_id(void)
|
|||
|
||||
void __init kirkwood_setup_wins(void)
|
||||
{
|
||||
mvebu_mbus_add_window("nand", KIRKWOOD_NAND_MEM_PHYS_BASE,
|
||||
KIRKWOOD_NAND_MEM_SIZE);
|
||||
mvebu_mbus_add_window("sram", KIRKWOOD_SRAM_PHYS_BASE,
|
||||
KIRKWOOD_SRAM_SIZE);
|
||||
mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_NAND_TARGET,
|
||||
KIRKWOOD_MBUS_NAND_ATTR,
|
||||
KIRKWOOD_NAND_MEM_PHYS_BASE,
|
||||
KIRKWOOD_NAND_MEM_SIZE);
|
||||
mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_SRAM_TARGET,
|
||||
KIRKWOOD_MBUS_SRAM_ATTR,
|
||||
KIRKWOOD_SRAM_PHYS_BASE,
|
||||
KIRKWOOD_SRAM_SIZE);
|
||||
}
|
||||
|
||||
void __init kirkwood_l2_init(void)
|
||||
|
@ -703,6 +709,10 @@ void __init kirkwood_init(void)
|
|||
*/
|
||||
writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
|
||||
|
||||
BUG_ON(mvebu_mbus_init("marvell,kirkwood-mbus",
|
||||
BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
|
||||
DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ));
|
||||
|
||||
kirkwood_setup_wins();
|
||||
|
||||
kirkwood_l2_init();
|
||||
|
|
|
@ -20,6 +20,16 @@
|
|||
#include <mach/bridge-regs.h>
|
||||
#include "common.h"
|
||||
|
||||
/* These can go away once Kirkwood uses the mvebu-mbus DT binding */
|
||||
#define KIRKWOOD_MBUS_PCIE0_MEM_TARGET 0x4
|
||||
#define KIRKWOOD_MBUS_PCIE0_MEM_ATTR 0xe8
|
||||
#define KIRKWOOD_MBUS_PCIE0_IO_TARGET 0x4
|
||||
#define KIRKWOOD_MBUS_PCIE0_IO_ATTR 0xe0
|
||||
#define KIRKWOOD_MBUS_PCIE1_MEM_TARGET 0x4
|
||||
#define KIRKWOOD_MBUS_PCIE1_MEM_ATTR 0xd8
|
||||
#define KIRKWOOD_MBUS_PCIE1_IO_TARGET 0x4
|
||||
#define KIRKWOOD_MBUS_PCIE1_IO_ATTR 0xd0
|
||||
|
||||
static void kirkwood_enable_pcie_clk(const char *port)
|
||||
{
|
||||
struct clk *clk;
|
||||
|
@ -254,26 +264,24 @@ static void __init add_pcie_port(int index, void __iomem *base)
|
|||
|
||||
void __init kirkwood_pcie_init(unsigned int portmask)
|
||||
{
|
||||
mvebu_mbus_add_window_remap_flags("pcie0.0",
|
||||
mvebu_mbus_add_window_remap_by_id(KIRKWOOD_MBUS_PCIE0_IO_TARGET,
|
||||
KIRKWOOD_MBUS_PCIE0_IO_ATTR,
|
||||
KIRKWOOD_PCIE_IO_PHYS_BASE,
|
||||
KIRKWOOD_PCIE_IO_SIZE,
|
||||
KIRKWOOD_PCIE_IO_BUS_BASE,
|
||||
MVEBU_MBUS_PCI_IO);
|
||||
mvebu_mbus_add_window_remap_flags("pcie0.0",
|
||||
KIRKWOOD_PCIE_MEM_PHYS_BASE,
|
||||
KIRKWOOD_PCIE_MEM_SIZE,
|
||||
MVEBU_MBUS_NO_REMAP,
|
||||
MVEBU_MBUS_PCI_MEM);
|
||||
mvebu_mbus_add_window_remap_flags("pcie1.0",
|
||||
KIRKWOOD_PCIE_IO_BUS_BASE);
|
||||
mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_PCIE0_MEM_TARGET,
|
||||
KIRKWOOD_MBUS_PCIE0_MEM_ATTR,
|
||||
KIRKWOOD_PCIE_MEM_PHYS_BASE,
|
||||
KIRKWOOD_PCIE_MEM_SIZE);
|
||||
mvebu_mbus_add_window_remap_by_id(KIRKWOOD_MBUS_PCIE1_IO_TARGET,
|
||||
KIRKWOOD_MBUS_PCIE1_IO_ATTR,
|
||||
KIRKWOOD_PCIE1_IO_PHYS_BASE,
|
||||
KIRKWOOD_PCIE1_IO_SIZE,
|
||||
KIRKWOOD_PCIE1_IO_BUS_BASE,
|
||||
MVEBU_MBUS_PCI_IO);
|
||||
mvebu_mbus_add_window_remap_flags("pcie1.0",
|
||||
KIRKWOOD_PCIE1_MEM_PHYS_BASE,
|
||||
KIRKWOOD_PCIE1_MEM_SIZE,
|
||||
MVEBU_MBUS_NO_REMAP,
|
||||
MVEBU_MBUS_PCI_MEM);
|
||||
KIRKWOOD_PCIE1_IO_BUS_BASE);
|
||||
mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_PCIE1_MEM_TARGET,
|
||||
KIRKWOOD_MBUS_PCIE1_MEM_ATTR,
|
||||
KIRKWOOD_PCIE1_MEM_PHYS_BASE,
|
||||
KIRKWOOD_PCIE1_MEM_SIZE);
|
||||
|
||||
vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;
|
||||
|
||||
|
|
|
@ -18,6 +18,11 @@
|
|||
#include <mach/mv78xx0.h>
|
||||
#include "common.h"
|
||||
|
||||
#define MV78XX0_MBUS_PCIE_MEM_TARGET(port, lane) ((port) ? 8 : 4)
|
||||
#define MV78XX0_MBUS_PCIE_MEM_ATTR(port, lane) (0xf8 & ~(0x10 << (lane)))
|
||||
#define MV78XX0_MBUS_PCIE_IO_TARGET(port, lane) ((port) ? 8 : 4)
|
||||
#define MV78XX0_MBUS_PCIE_IO_ATTR(port, lane) (0xf0 & ~(0x10 << (lane)))
|
||||
|
||||
struct pcie_port {
|
||||
u8 maj;
|
||||
u8 min;
|
||||
|
@ -71,7 +76,6 @@ static void __init mv78xx0_pcie_preinit(void)
|
|||
start = MV78XX0_PCIE_MEM_PHYS_BASE;
|
||||
for (i = 0; i < num_pcie_ports; i++) {
|
||||
struct pcie_port *pp = pcie_port + i;
|
||||
char winname[MVEBU_MBUS_MAX_WINNAME_SZ];
|
||||
|
||||
snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
|
||||
"PCIe %d.%d MEM", pp->maj, pp->min);
|
||||
|
@ -85,17 +89,12 @@ static void __init mv78xx0_pcie_preinit(void)
|
|||
if (request_resource(&iomem_resource, &pp->res))
|
||||
panic("can't allocate PCIe MEM sub-space");
|
||||
|
||||
snprintf(winname, sizeof(winname), "pcie%d.%d",
|
||||
pp->maj, pp->min);
|
||||
|
||||
mvebu_mbus_add_window_remap_flags(winname,
|
||||
pp->res.start,
|
||||
resource_size(&pp->res),
|
||||
MVEBU_MBUS_NO_REMAP,
|
||||
MVEBU_MBUS_PCI_MEM);
|
||||
mvebu_mbus_add_window_remap_flags(winname,
|
||||
i * SZ_64K, SZ_64K,
|
||||
0, MVEBU_MBUS_PCI_IO);
|
||||
mvebu_mbus_add_window_by_id(MV78XX0_MBUS_PCIE_MEM_TARGET(pp->maj, pp->min),
|
||||
MV78XX0_MBUS_PCIE_MEM_ATTR(pp->maj, pp->min),
|
||||
pp->res.start, resource_size(&pp->res));
|
||||
mvebu_mbus_add_window_remap_by_id(MV78XX0_MBUS_PCIE_IO_TARGET(pp->maj, pp->min),
|
||||
MV78XX0_MBUS_PCIE_IO_ATTR(pp->maj, pp->min),
|
||||
i * SZ_64K, SZ_64K, 0);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -34,44 +34,12 @@ static void __init armada_370_xp_map_io(void)
|
|||
debug_ll_io_init();
|
||||
}
|
||||
|
||||
/*
|
||||
* This initialization will be replaced by a DT-based
|
||||
* initialization once the mvebu-mbus driver gains DT support.
|
||||
*/
|
||||
|
||||
#define ARMADA_370_XP_MBUS_WINS_OFFS 0x20000
|
||||
#define ARMADA_370_XP_MBUS_WINS_SIZE 0x100
|
||||
#define ARMADA_370_XP_SDRAM_WINS_OFFS 0x20180
|
||||
#define ARMADA_370_XP_SDRAM_WINS_SIZE 0x20
|
||||
|
||||
static void __init armada_370_xp_mbus_init(void)
|
||||
{
|
||||
char *mbus_soc_name;
|
||||
struct device_node *dn;
|
||||
const __be32 mbus_wins_offs = cpu_to_be32(ARMADA_370_XP_MBUS_WINS_OFFS);
|
||||
const __be32 sdram_wins_offs = cpu_to_be32(ARMADA_370_XP_SDRAM_WINS_OFFS);
|
||||
|
||||
if (of_machine_is_compatible("marvell,armada370"))
|
||||
mbus_soc_name = "marvell,armada370-mbus";
|
||||
else
|
||||
mbus_soc_name = "marvell,armadaxp-mbus";
|
||||
|
||||
dn = of_find_node_by_name(NULL, "internal-regs");
|
||||
BUG_ON(!dn);
|
||||
|
||||
mvebu_mbus_init(mbus_soc_name,
|
||||
of_translate_address(dn, &mbus_wins_offs),
|
||||
ARMADA_370_XP_MBUS_WINS_SIZE,
|
||||
of_translate_address(dn, &sdram_wins_offs),
|
||||
ARMADA_370_XP_SDRAM_WINS_SIZE);
|
||||
}
|
||||
|
||||
static void __init armada_370_xp_timer_and_clk_init(void)
|
||||
{
|
||||
of_clk_init(NULL);
|
||||
armada_370_xp_timer_init();
|
||||
coherency_init();
|
||||
armada_370_xp_mbus_init();
|
||||
BUG_ON(mvebu_mbus_dt_init());
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
l2x0_of_init(0, ~0UL);
|
||||
#endif
|
||||
|
|
|
@ -21,6 +21,7 @@
|
|||
#include <linux/smp.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/mbus.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/smp_plat.h>
|
||||
|
@ -29,6 +30,9 @@
|
|||
#include "pmsu.h"
|
||||
#include "coherency.h"
|
||||
|
||||
#define AXP_BOOTROM_BASE 0xfff00000
|
||||
#define AXP_BOOTROM_SIZE 0x100000
|
||||
|
||||
void __init set_secondary_cpus_clock(void)
|
||||
{
|
||||
int thiscpu;
|
||||
|
@ -114,10 +118,29 @@ static void __init armada_xp_smp_init_cpus(void)
|
|||
|
||||
void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
struct device_node *node;
|
||||
struct resource res;
|
||||
int err;
|
||||
|
||||
set_secondary_cpus_clock();
|
||||
flush_cache_all();
|
||||
set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
|
||||
mvebu_mbus_add_window("bootrom", 0xfff00000, SZ_1M);
|
||||
|
||||
/*
|
||||
* In order to boot the secondary CPUs we need to ensure
|
||||
* the bootROM is mapped at the correct address.
|
||||
*/
|
||||
node = of_find_compatible_node(NULL, NULL, "marvell,bootrom");
|
||||
if (!node)
|
||||
panic("Cannot find 'marvell,bootrom' compatible node");
|
||||
|
||||
err = of_address_to_resource(node, 0, &res);
|
||||
if (err < 0)
|
||||
panic("Cannot get 'bootrom' node address");
|
||||
|
||||
if (res.start != AXP_BOOTROM_BASE ||
|
||||
resource_size(&res) != AXP_BOOTROM_SIZE)
|
||||
panic("The address for the BootROM is incorrect");
|
||||
}
|
||||
|
||||
struct smp_operations armada_xp_smp_ops __initdata = {
|
||||
|
|
|
@ -174,8 +174,10 @@ void __init orion5x_xor_init(void)
|
|||
****************************************************************************/
|
||||
static void __init orion5x_crypto_init(void)
|
||||
{
|
||||
mvebu_mbus_add_window("sram", ORION5X_SRAM_PHYS_BASE,
|
||||
ORION5X_SRAM_SIZE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_SRAM_TARGET,
|
||||
ORION_MBUS_SRAM_ATTR,
|
||||
ORION5X_SRAM_PHYS_BASE,
|
||||
ORION5X_SRAM_SIZE);
|
||||
orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
|
||||
SZ_8K, IRQ_ORION5X_CESA);
|
||||
}
|
||||
|
@ -222,22 +224,24 @@ void orion5x_setup_wins(void)
|
|||
* The PCIe windows will no longer be statically allocated
|
||||
* here once Orion5x is migrated to the pci-mvebu driver.
|
||||
*/
|
||||
mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_IO_PHYS_BASE,
|
||||
mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET,
|
||||
ORION_MBUS_PCIE_IO_ATTR,
|
||||
ORION5X_PCIE_IO_PHYS_BASE,
|
||||
ORION5X_PCIE_IO_SIZE,
|
||||
ORION5X_PCIE_IO_BUS_BASE,
|
||||
MVEBU_MBUS_PCI_IO);
|
||||
mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_MEM_PHYS_BASE,
|
||||
ORION5X_PCIE_MEM_SIZE,
|
||||
MVEBU_MBUS_NO_REMAP,
|
||||
MVEBU_MBUS_PCI_MEM);
|
||||
mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_IO_PHYS_BASE,
|
||||
ORION5X_PCIE_IO_BUS_BASE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET,
|
||||
ORION_MBUS_PCIE_MEM_ATTR,
|
||||
ORION5X_PCIE_MEM_PHYS_BASE,
|
||||
ORION5X_PCIE_MEM_SIZE);
|
||||
mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
|
||||
ORION_MBUS_PCI_IO_ATTR,
|
||||
ORION5X_PCI_IO_PHYS_BASE,
|
||||
ORION5X_PCI_IO_SIZE,
|
||||
ORION5X_PCI_IO_BUS_BASE,
|
||||
MVEBU_MBUS_PCI_IO);
|
||||
mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_MEM_PHYS_BASE,
|
||||
ORION5X_PCI_MEM_SIZE,
|
||||
MVEBU_MBUS_NO_REMAP,
|
||||
MVEBU_MBUS_PCI_MEM);
|
||||
ORION5X_PCI_IO_BUS_BASE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
|
||||
ORION_MBUS_PCI_MEM_ATTR,
|
||||
ORION5X_PCI_MEM_PHYS_BASE,
|
||||
ORION5X_PCI_MEM_SIZE);
|
||||
}
|
||||
|
||||
int orion5x_tclk;
|
||||
|
|
|
@ -7,6 +7,23 @@ struct dsa_platform_data;
|
|||
struct mv643xx_eth_platform_data;
|
||||
struct mv_sata_platform_data;
|
||||
|
||||
#define ORION_MBUS_PCIE_MEM_TARGET 0x04
|
||||
#define ORION_MBUS_PCIE_MEM_ATTR 0x59
|
||||
#define ORION_MBUS_PCIE_IO_TARGET 0x04
|
||||
#define ORION_MBUS_PCIE_IO_ATTR 0x51
|
||||
#define ORION_MBUS_PCIE_WA_TARGET 0x04
|
||||
#define ORION_MBUS_PCIE_WA_ATTR 0x79
|
||||
#define ORION_MBUS_PCI_MEM_TARGET 0x03
|
||||
#define ORION_MBUS_PCI_MEM_ATTR 0x59
|
||||
#define ORION_MBUS_PCI_IO_TARGET 0x03
|
||||
#define ORION_MBUS_PCI_IO_ATTR 0x51
|
||||
#define ORION_MBUS_DEVBUS_BOOT_TARGET 0x01
|
||||
#define ORION_MBUS_DEVBUS_BOOT_ATTR 0x0f
|
||||
#define ORION_MBUS_DEVBUS_TARGET(cs) 0x01
|
||||
#define ORION_MBUS_DEVBUS_ATTR(cs) (~(1 << cs))
|
||||
#define ORION_MBUS_SRAM_TARGET 0x00
|
||||
#define ORION_MBUS_SRAM_ATTR 0x00
|
||||
|
||||
/*
|
||||
* Basic Orion init functions used early by machine-setup.
|
||||
*/
|
||||
|
|
|
@ -317,8 +317,10 @@ static void __init d2net_init(void)
|
|||
d2net_sata_power_init();
|
||||
orion5x_sata_init(&d2net_sata_data);
|
||||
|
||||
mvebu_mbus_add_window("devbus-boot", D2NET_NOR_BOOT_BASE,
|
||||
D2NET_NOR_BOOT_SIZE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
|
||||
ORION_MBUS_DEVBUS_BOOT_ATTR,
|
||||
D2NET_NOR_BOOT_BASE,
|
||||
D2NET_NOR_BOOT_SIZE);
|
||||
platform_device_register(&d2net_nor_flash);
|
||||
|
||||
platform_device_register(&d2net_gpio_buttons);
|
||||
|
|
|
@ -340,19 +340,27 @@ static void __init db88f5281_init(void)
|
|||
orion5x_uart0_init();
|
||||
orion5x_uart1_init();
|
||||
|
||||
mvebu_mbus_add_window("devbus-boot", DB88F5281_NOR_BOOT_BASE,
|
||||
DB88F5281_NOR_BOOT_SIZE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
|
||||
ORION_MBUS_DEVBUS_BOOT_ATTR,
|
||||
DB88F5281_NOR_BOOT_BASE,
|
||||
DB88F5281_NOR_BOOT_SIZE);
|
||||
platform_device_register(&db88f5281_boot_flash);
|
||||
|
||||
mvebu_mbus_add_window("devbus-cs0", DB88F5281_7SEG_BASE,
|
||||
DB88F5281_7SEG_SIZE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0),
|
||||
ORION_MBUS_DEVBUS_ATTR(0),
|
||||
DB88F5281_7SEG_BASE,
|
||||
DB88F5281_7SEG_SIZE);
|
||||
|
||||
mvebu_mbus_add_window("devbus-cs1", DB88F5281_NOR_BASE,
|
||||
DB88F5281_NOR_SIZE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1),
|
||||
ORION_MBUS_DEVBUS_ATTR(1),
|
||||
DB88F5281_NOR_BASE,
|
||||
DB88F5281_NOR_SIZE);
|
||||
platform_device_register(&db88f5281_nor_flash);
|
||||
|
||||
mvebu_mbus_add_window("devbus-cs2", DB88F5281_NAND_BASE,
|
||||
DB88F5281_NAND_SIZE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(2),
|
||||
ORION_MBUS_DEVBUS_ATTR(2),
|
||||
DB88F5281_NAND_BASE,
|
||||
DB88F5281_NAND_SIZE);
|
||||
platform_device_register(&db88f5281_nand_flash);
|
||||
|
||||
i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
|
||||
|
|
|
@ -611,8 +611,10 @@ static void __init dns323_init(void)
|
|||
/* setup flash mapping
|
||||
* CS3 holds a 8 MB Spansion S29GL064M90TFIR4
|
||||
*/
|
||||
mvebu_mbus_add_window("devbus-boot", DNS323_NOR_BOOT_BASE,
|
||||
DNS323_NOR_BOOT_SIZE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
|
||||
ORION_MBUS_DEVBUS_BOOT_ATTR,
|
||||
DNS323_NOR_BOOT_BASE,
|
||||
DNS323_NOR_BOOT_SIZE);
|
||||
platform_device_register(&dns323_nor_flash);
|
||||
|
||||
/* Sort out LEDs, Buttons and i2c devices */
|
||||
|
|
|
@ -154,8 +154,10 @@ void __init edmini_v2_init(void)
|
|||
orion5x_ehci0_init();
|
||||
orion5x_eth_init(&edmini_v2_eth_data);
|
||||
|
||||
mvebu_mbus_add_window("devbus-boot", EDMINI_V2_NOR_BOOT_BASE,
|
||||
EDMINI_V2_NOR_BOOT_SIZE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
|
||||
ORION_MBUS_DEVBUS_BOOT_ATTR,
|
||||
EDMINI_V2_NOR_BOOT_BASE,
|
||||
EDMINI_V2_NOR_BOOT_SIZE);
|
||||
platform_device_register(&edmini_v2_nor_flash);
|
||||
|
||||
pr_notice("edmini_v2: USB device port, flash write and power-off "
|
||||
|
|
|
@ -359,13 +359,17 @@ static void __init kurobox_pro_init(void)
|
|||
orion5x_uart1_init();
|
||||
orion5x_xor_init();
|
||||
|
||||
mvebu_mbus_add_window("devbus-boot", KUROBOX_PRO_NOR_BOOT_BASE,
|
||||
KUROBOX_PRO_NOR_BOOT_SIZE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
|
||||
ORION_MBUS_DEVBUS_BOOT_ATTR,
|
||||
KUROBOX_PRO_NOR_BOOT_BASE,
|
||||
KUROBOX_PRO_NOR_BOOT_SIZE);
|
||||
platform_device_register(&kurobox_pro_nor_flash);
|
||||
|
||||
if (machine_is_kurobox_pro()) {
|
||||
mvebu_mbus_add_window("devbus-cs0", KUROBOX_PRO_NAND_BASE,
|
||||
KUROBOX_PRO_NAND_SIZE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0),
|
||||
ORION_MBUS_DEVBUS_ATTR(0),
|
||||
KUROBOX_PRO_NAND_BASE,
|
||||
KUROBOX_PRO_NAND_SIZE);
|
||||
platform_device_register(&kurobox_pro_nand_flash);
|
||||
}
|
||||
|
||||
|
|
|
@ -294,8 +294,10 @@ static void __init lschl_init(void)
|
|||
orion5x_uart0_init();
|
||||
orion5x_xor_init();
|
||||
|
||||
mvebu_mbus_add_window("devbus-boot", LSCHL_NOR_BOOT_BASE,
|
||||
LSCHL_NOR_BOOT_SIZE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
|
||||
ORION_MBUS_DEVBUS_BOOT_ATTR,
|
||||
LSCHL_NOR_BOOT_BASE,
|
||||
LSCHL_NOR_BOOT_SIZE);
|
||||
platform_device_register(&lschl_nor_flash);
|
||||
|
||||
platform_device_register(&lschl_leds);
|
||||
|
|
|
@ -243,8 +243,10 @@ static void __init ls_hgl_init(void)
|
|||
orion5x_uart0_init();
|
||||
orion5x_xor_init();
|
||||
|
||||
mvebu_mbus_add_window("devbus-boot", LS_HGL_NOR_BOOT_BASE,
|
||||
LS_HGL_NOR_BOOT_SIZE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
|
||||
ORION_MBUS_DEVBUS_BOOT_ATTR,
|
||||
LS_HGL_NOR_BOOT_BASE,
|
||||
LS_HGL_NOR_BOOT_SIZE);
|
||||
platform_device_register(&ls_hgl_nor_flash);
|
||||
|
||||
platform_device_register(&ls_hgl_button_device);
|
||||
|
|
|
@ -244,8 +244,10 @@ static void __init lsmini_init(void)
|
|||
orion5x_uart0_init();
|
||||
orion5x_xor_init();
|
||||
|
||||
mvebu_mbus_add_window("devbus-boot", LSMINI_NOR_BOOT_BASE,
|
||||
LSMINI_NOR_BOOT_SIZE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
|
||||
ORION_MBUS_DEVBUS_BOOT_ATTR,
|
||||
LSMINI_NOR_BOOT_BASE,
|
||||
LSMINI_NOR_BOOT_SIZE);
|
||||
platform_device_register(&lsmini_nor_flash);
|
||||
|
||||
platform_device_register(&lsmini_button_device);
|
||||
|
|
|
@ -241,8 +241,10 @@ static void __init mss2_init(void)
|
|||
orion5x_uart0_init();
|
||||
orion5x_xor_init();
|
||||
|
||||
mvebu_mbus_add_window("devbus-boot", MSS2_NOR_BOOT_BASE,
|
||||
MSS2_NOR_BOOT_SIZE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
|
||||
ORION_MBUS_DEVBUS_BOOT_ATTR,
|
||||
MSS2_NOR_BOOT_BASE,
|
||||
MSS2_NOR_BOOT_SIZE);
|
||||
platform_device_register(&mss2_nor_flash);
|
||||
|
||||
platform_device_register(&mss2_button_device);
|
||||
|
|
|
@ -204,8 +204,10 @@ static void __init mv2120_init(void)
|
|||
orion5x_uart0_init();
|
||||
orion5x_xor_init();
|
||||
|
||||
mvebu_mbus_add_window("devbus-boot", MV2120_NOR_BOOT_BASE,
|
||||
MV2120_NOR_BOOT_SIZE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
|
||||
ORION_MBUS_DEVBUS_BOOT_ATTR,
|
||||
MV2120_NOR_BOOT_BASE,
|
||||
MV2120_NOR_BOOT_SIZE);
|
||||
platform_device_register(&mv2120_nor_flash);
|
||||
|
||||
platform_device_register(&mv2120_button_device);
|
||||
|
|
|
@ -397,8 +397,10 @@ static void __init net2big_init(void)
|
|||
net2big_sata_power_init();
|
||||
orion5x_sata_init(&net2big_sata_data);
|
||||
|
||||
mvebu_mbus_add_window("devbus-boot", NET2BIG_NOR_BOOT_BASE,
|
||||
NET2BIG_NOR_BOOT_SIZE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
|
||||
ORION_MBUS_DEVBUS_BOOT_ATTR,
|
||||
NET2BIG_NOR_BOOT_BASE,
|
||||
NET2BIG_NOR_BOOT_SIZE);
|
||||
platform_device_register(&net2big_nor_flash);
|
||||
|
||||
platform_device_register(&net2big_gpio_buttons);
|
||||
|
|
|
@ -157,11 +157,10 @@ static int __init pcie_setup(struct pci_sys_data *sys)
|
|||
if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
|
||||
printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
|
||||
"read transaction workaround\n");
|
||||
mvebu_mbus_add_window_remap_flags("pcie0.0",
|
||||
ORION5X_PCIE_WA_PHYS_BASE,
|
||||
ORION5X_PCIE_WA_SIZE,
|
||||
MVEBU_MBUS_NO_REMAP,
|
||||
MVEBU_MBUS_PCI_WA);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_WA_TARGET,
|
||||
ORION_MBUS_PCIE_WA_ATTR,
|
||||
ORION5X_PCIE_WA_PHYS_BASE,
|
||||
ORION5X_PCIE_WA_SIZE);
|
||||
pcie_ops.read = pcie_rd_conf_wa;
|
||||
}
|
||||
|
||||
|
|
|
@ -123,8 +123,10 @@ static void __init rd88f5181l_fxo_init(void)
|
|||
orion5x_eth_switch_init(&rd88f5181l_fxo_switch_plat_data, NO_IRQ);
|
||||
orion5x_uart0_init();
|
||||
|
||||
mvebu_mbus_add_window("devbus-boot", RD88F5181L_FXO_NOR_BOOT_BASE,
|
||||
RD88F5181L_FXO_NOR_BOOT_SIZE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
|
||||
ORION_MBUS_DEVBUS_BOOT_ATTR,
|
||||
RD88F5181L_FXO_NOR_BOOT_BASE,
|
||||
RD88F5181L_FXO_NOR_BOOT_SIZE);
|
||||
platform_device_register(&rd88f5181l_fxo_nor_boot_flash);
|
||||
}
|
||||
|
||||
|
|
|
@ -130,8 +130,10 @@ static void __init rd88f5181l_ge_init(void)
|
|||
orion5x_i2c_init();
|
||||
orion5x_uart0_init();
|
||||
|
||||
mvebu_mbus_add_window("devbus-boot", RD88F5181L_GE_NOR_BOOT_BASE,
|
||||
RD88F5181L_GE_NOR_BOOT_SIZE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
|
||||
ORION_MBUS_DEVBUS_BOOT_ATTR,
|
||||
RD88F5181L_GE_NOR_BOOT_BASE,
|
||||
RD88F5181L_GE_NOR_BOOT_SIZE);
|
||||
platform_device_register(&rd88f5181l_ge_nor_boot_flash);
|
||||
|
||||
i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1);
|
||||
|
|
|
@ -264,11 +264,14 @@ static void __init rd88f5182_init(void)
|
|||
orion5x_uart0_init();
|
||||
orion5x_xor_init();
|
||||
|
||||
mvebu_mbus_add_window("devbus-boot", RD88F5182_NOR_BOOT_BASE,
|
||||
RD88F5182_NOR_BOOT_SIZE);
|
||||
|
||||
mvebu_mbus_add_window("devbus-cs1", RD88F5182_NOR_BASE,
|
||||
RD88F5182_NOR_SIZE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
|
||||
ORION_MBUS_DEVBUS_BOOT_ATTR,
|
||||
RD88F5182_NOR_BOOT_BASE,
|
||||
RD88F5182_NOR_BOOT_SIZE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1),
|
||||
ORION_MBUS_DEVBUS_ATTR(1),
|
||||
RD88F5182_NOR_BASE,
|
||||
RD88F5182_NOR_SIZE);
|
||||
platform_device_register(&rd88f5182_nor_flash);
|
||||
platform_device_register(&rd88f5182_gpio_leds);
|
||||
|
||||
|
|
|
@ -329,8 +329,10 @@ static void __init tsp2_init(void)
|
|||
/*
|
||||
* Configure peripherals.
|
||||
*/
|
||||
mvebu_mbus_add_window("devbus-boot", TSP2_NOR_BOOT_BASE,
|
||||
TSP2_NOR_BOOT_SIZE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
|
||||
ORION_MBUS_DEVBUS_BOOT_ATTR,
|
||||
TSP2_NOR_BOOT_BASE,
|
||||
TSP2_NOR_BOOT_SIZE);
|
||||
platform_device_register(&tsp2_nor_flash);
|
||||
|
||||
orion5x_ehci0_init();
|
||||
|
|
|
@ -286,8 +286,10 @@ static void __init qnap_ts209_init(void)
|
|||
/*
|
||||
* Configure peripherals.
|
||||
*/
|
||||
mvebu_mbus_add_window("devbus-boot", QNAP_TS209_NOR_BOOT_BASE,
|
||||
QNAP_TS209_NOR_BOOT_SIZE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
|
||||
ORION_MBUS_DEVBUS_BOOT_ATTR,
|
||||
QNAP_TS209_NOR_BOOT_BASE,
|
||||
QNAP_TS209_NOR_BOOT_SIZE);
|
||||
platform_device_register(&qnap_ts209_nor_flash);
|
||||
|
||||
orion5x_ehci0_init();
|
||||
|
|
|
@ -277,8 +277,10 @@ static void __init qnap_ts409_init(void)
|
|||
/*
|
||||
* Configure peripherals.
|
||||
*/
|
||||
mvebu_mbus_add_window("devbus-boot", QNAP_TS409_NOR_BOOT_BASE,
|
||||
QNAP_TS409_NOR_BOOT_SIZE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
|
||||
ORION_MBUS_DEVBUS_BOOT_ATTR,
|
||||
QNAP_TS409_NOR_BOOT_BASE,
|
||||
QNAP_TS409_NOR_BOOT_SIZE);
|
||||
platform_device_register(&qnap_ts409_nor_flash);
|
||||
|
||||
orion5x_ehci0_init();
|
||||
|
|
|
@ -127,8 +127,10 @@ static void __init wnr854t_init(void)
|
|||
orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ);
|
||||
orion5x_uart0_init();
|
||||
|
||||
mvebu_mbus_add_window("devbus-boot", WNR854T_NOR_BOOT_BASE,
|
||||
WNR854T_NOR_BOOT_SIZE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
|
||||
ORION_MBUS_DEVBUS_BOOT_ATTR,
|
||||
WNR854T_NOR_BOOT_BASE,
|
||||
WNR854T_NOR_BOOT_SIZE);
|
||||
platform_device_register(&wnr854t_nor_flash);
|
||||
}
|
||||
|
||||
|
|
|
@ -213,8 +213,10 @@ static void __init wrt350n_v2_init(void)
|
|||
orion5x_eth_switch_init(&wrt350n_v2_switch_plat_data, NO_IRQ);
|
||||
orion5x_uart0_init();
|
||||
|
||||
mvebu_mbus_add_window("devbus-boot", WRT350N_V2_NOR_BOOT_BASE,
|
||||
WRT350N_V2_NOR_BOOT_SIZE);
|
||||
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
|
||||
ORION_MBUS_DEVBUS_BOOT_ATTR,
|
||||
WRT350N_V2_NOR_BOOT_BASE,
|
||||
WRT350N_V2_NOR_BOOT_SIZE);
|
||||
platform_device_register(&wrt350n_v2_nor_flash);
|
||||
platform_device_register(&wrt350n_v2_leds);
|
||||
platform_device_register(&wrt350n_v2_button_device);
|
||||
|
|
|
@ -35,13 +35,9 @@
|
|||
*
|
||||
* - Provides an API for platform code or device drivers to
|
||||
* dynamically add or remove address decoding windows for the CPU ->
|
||||
* device accesses. This API is mvebu_mbus_add_window(),
|
||||
* mvebu_mbus_add_window_remap_flags() and
|
||||
* mvebu_mbus_del_window(). Since the (target, attribute) values
|
||||
* differ from one SoC family to another, the API uses a 'const char
|
||||
* *' string to identify devices, and this driver is responsible for
|
||||
* knowing the mapping between the name of a device and its
|
||||
* corresponding (target, attribute) in the current SoC family.
|
||||
* device accesses. This API is mvebu_mbus_add_window_by_id(),
|
||||
* mvebu_mbus_add_window_remap_by_id() and
|
||||
* mvebu_mbus_del_window().
|
||||
*
|
||||
* - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
|
||||
* see the list of CPU -> SDRAM windows and their configuration
|
||||
|
@ -97,33 +93,6 @@
|
|||
|
||||
#define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
|
||||
|
||||
struct mvebu_mbus_mapping {
|
||||
const char *name;
|
||||
u8 target;
|
||||
u8 attr;
|
||||
u8 attrmask;
|
||||
};
|
||||
|
||||
/*
|
||||
* Masks used for the 'attrmask' field of mvebu_mbus_mapping. They
|
||||
* allow to get the real attribute value, discarding the special bits
|
||||
* used to select a PCI MEM region or a PCI WA region. This allows the
|
||||
* debugfs code to reverse-match the name of a device from its
|
||||
* target/attr values.
|
||||
*
|
||||
* For all devices except PCI, all bits of 'attr' must be
|
||||
* considered. For most SoCs, only bit 3 should be ignored (it allows
|
||||
* to select between PCI MEM and PCI I/O). On Orion5x however, there
|
||||
* is the special bit 5 to select a PCI WA region.
|
||||
*/
|
||||
#define MAPDEF_NOMASK 0xff
|
||||
#define MAPDEF_PCIMASK 0xf7
|
||||
#define MAPDEF_ORIONPCIMASK 0xd7
|
||||
|
||||
/* Macro used to define one mvebu_mbus_mapping entry */
|
||||
#define MAPDEF(__n, __t, __a, __m) \
|
||||
{ .name = __n, .target = __t, .attr = __a, .attrmask = __m }
|
||||
|
||||
struct mvebu_mbus_state;
|
||||
|
||||
struct mvebu_mbus_soc_data {
|
||||
|
@ -133,7 +102,6 @@ struct mvebu_mbus_soc_data {
|
|||
void (*setup_cpu_target)(struct mvebu_mbus_state *s);
|
||||
int (*show_cpu_target)(struct mvebu_mbus_state *s,
|
||||
struct seq_file *seq, void *v);
|
||||
const struct mvebu_mbus_mapping *map;
|
||||
};
|
||||
|
||||
struct mvebu_mbus_state {
|
||||
|
@ -142,6 +110,8 @@ struct mvebu_mbus_state {
|
|||
struct dentry *debugfs_root;
|
||||
struct dentry *debugfs_sdram;
|
||||
struct dentry *debugfs_devs;
|
||||
struct resource pcie_mem_aperture;
|
||||
struct resource pcie_io_aperture;
|
||||
const struct mvebu_mbus_soc_data *soc;
|
||||
int hw_io_coherency;
|
||||
};
|
||||
|
@ -428,8 +398,7 @@ static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
|
|||
u64 wbase, wremap;
|
||||
u32 wsize;
|
||||
u8 wtarget, wattr;
|
||||
int enabled, i;
|
||||
const char *name;
|
||||
int enabled;
|
||||
|
||||
mvebu_mbus_read_window(mbus, win,
|
||||
&enabled, &wbase, &wsize,
|
||||
|
@ -440,18 +409,9 @@ static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
|
|||
continue;
|
||||
}
|
||||
|
||||
|
||||
for (i = 0; mbus->soc->map[i].name; i++)
|
||||
if (mbus->soc->map[i].target == wtarget &&
|
||||
mbus->soc->map[i].attr ==
|
||||
(wattr & mbus->soc->map[i].attrmask))
|
||||
break;
|
||||
|
||||
name = mbus->soc->map[i].name ?: "unknown";
|
||||
|
||||
seq_printf(seq, "[%02d] %016llx - %016llx : %s",
|
||||
seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x",
|
||||
win, (unsigned long long)wbase,
|
||||
(unsigned long long)(wbase + wsize), name);
|
||||
(unsigned long long)(wbase + wsize), wtarget, wattr);
|
||||
|
||||
if (win < mbus->soc->num_remappable_wins) {
|
||||
seq_printf(seq, " (remap %016llx)\n",
|
||||
|
@ -576,62 +536,12 @@ mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
|
|||
mvebu_mbus_dram_info.num_cs = cs;
|
||||
}
|
||||
|
||||
static const struct mvebu_mbus_mapping armada_370_map[] = {
|
||||
MAPDEF("bootrom", 1, 0xe0, MAPDEF_NOMASK),
|
||||
MAPDEF("devbus-boot", 1, 0x2f, MAPDEF_NOMASK),
|
||||
MAPDEF("devbus-cs0", 1, 0x3e, MAPDEF_NOMASK),
|
||||
MAPDEF("devbus-cs1", 1, 0x3d, MAPDEF_NOMASK),
|
||||
MAPDEF("devbus-cs2", 1, 0x3b, MAPDEF_NOMASK),
|
||||
MAPDEF("devbus-cs3", 1, 0x37, MAPDEF_NOMASK),
|
||||
MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
|
||||
MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
|
||||
{},
|
||||
};
|
||||
|
||||
static const struct mvebu_mbus_soc_data armada_370_mbus_data = {
|
||||
static const struct mvebu_mbus_soc_data armada_370_xp_mbus_data = {
|
||||
.num_wins = 20,
|
||||
.num_remappable_wins = 8,
|
||||
.win_cfg_offset = armada_370_xp_mbus_win_offset,
|
||||
.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
|
||||
.show_cpu_target = mvebu_sdram_debug_show_orion,
|
||||
.map = armada_370_map,
|
||||
};
|
||||
|
||||
static const struct mvebu_mbus_mapping armada_xp_map[] = {
|
||||
MAPDEF("bootrom", 1, 0x1d, MAPDEF_NOMASK),
|
||||
MAPDEF("devbus-boot", 1, 0x2f, MAPDEF_NOMASK),
|
||||
MAPDEF("devbus-cs0", 1, 0x3e, MAPDEF_NOMASK),
|
||||
MAPDEF("devbus-cs1", 1, 0x3d, MAPDEF_NOMASK),
|
||||
MAPDEF("devbus-cs2", 1, 0x3b, MAPDEF_NOMASK),
|
||||
MAPDEF("devbus-cs3", 1, 0x37, MAPDEF_NOMASK),
|
||||
MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
|
||||
MAPDEF("pcie0.1", 4, 0xd0, MAPDEF_PCIMASK),
|
||||
MAPDEF("pcie0.2", 4, 0xb0, MAPDEF_PCIMASK),
|
||||
MAPDEF("pcie0.3", 4, 0x70, MAPDEF_PCIMASK),
|
||||
MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
|
||||
MAPDEF("pcie1.1", 8, 0xd0, MAPDEF_PCIMASK),
|
||||
MAPDEF("pcie1.2", 8, 0xb0, MAPDEF_PCIMASK),
|
||||
MAPDEF("pcie1.3", 8, 0x70, MAPDEF_PCIMASK),
|
||||
MAPDEF("pcie2.0", 4, 0xf0, MAPDEF_PCIMASK),
|
||||
MAPDEF("pcie3.0", 8, 0xf0, MAPDEF_PCIMASK),
|
||||
{},
|
||||
};
|
||||
|
||||
static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
|
||||
.num_wins = 20,
|
||||
.num_remappable_wins = 8,
|
||||
.win_cfg_offset = armada_370_xp_mbus_win_offset,
|
||||
.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
|
||||
.show_cpu_target = mvebu_sdram_debug_show_orion,
|
||||
.map = armada_xp_map,
|
||||
};
|
||||
|
||||
static const struct mvebu_mbus_mapping kirkwood_map[] = {
|
||||
MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
|
||||
MAPDEF("pcie1.0", 4, 0xd0, MAPDEF_PCIMASK),
|
||||
MAPDEF("sram", 3, 0x01, MAPDEF_NOMASK),
|
||||
MAPDEF("nand", 1, 0x2f, MAPDEF_NOMASK),
|
||||
{},
|
||||
};
|
||||
|
||||
static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
|
||||
|
@ -640,16 +550,6 @@ static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
|
|||
.win_cfg_offset = orion_mbus_win_offset,
|
||||
.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
|
||||
.show_cpu_target = mvebu_sdram_debug_show_orion,
|
||||
.map = kirkwood_map,
|
||||
};
|
||||
|
||||
static const struct mvebu_mbus_mapping dove_map[] = {
|
||||
MAPDEF("pcie0.0", 0x4, 0xe0, MAPDEF_PCIMASK),
|
||||
MAPDEF("pcie1.0", 0x8, 0xe0, MAPDEF_PCIMASK),
|
||||
MAPDEF("cesa", 0x3, 0x01, MAPDEF_NOMASK),
|
||||
MAPDEF("bootrom", 0x1, 0xfd, MAPDEF_NOMASK),
|
||||
MAPDEF("scratchpad", 0xd, 0x0, MAPDEF_NOMASK),
|
||||
{},
|
||||
};
|
||||
|
||||
static const struct mvebu_mbus_soc_data dove_mbus_data = {
|
||||
|
@ -658,18 +558,6 @@ static const struct mvebu_mbus_soc_data dove_mbus_data = {
|
|||
.win_cfg_offset = orion_mbus_win_offset,
|
||||
.setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
|
||||
.show_cpu_target = mvebu_sdram_debug_show_dove,
|
||||
.map = dove_map,
|
||||
};
|
||||
|
||||
static const struct mvebu_mbus_mapping orion5x_map[] = {
|
||||
MAPDEF("pcie0.0", 4, 0x51, MAPDEF_ORIONPCIMASK),
|
||||
MAPDEF("pci0.0", 3, 0x51, MAPDEF_ORIONPCIMASK),
|
||||
MAPDEF("devbus-boot", 1, 0x0f, MAPDEF_NOMASK),
|
||||
MAPDEF("devbus-cs0", 1, 0x1e, MAPDEF_NOMASK),
|
||||
MAPDEF("devbus-cs1", 1, 0x1d, MAPDEF_NOMASK),
|
||||
MAPDEF("devbus-cs2", 1, 0x1b, MAPDEF_NOMASK),
|
||||
MAPDEF("sram", 0, 0x00, MAPDEF_NOMASK),
|
||||
{},
|
||||
};
|
||||
|
||||
/*
|
||||
|
@ -682,7 +570,6 @@ static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
|
|||
.win_cfg_offset = orion_mbus_win_offset,
|
||||
.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
|
||||
.show_cpu_target = mvebu_sdram_debug_show_orion,
|
||||
.map = orion5x_map,
|
||||
};
|
||||
|
||||
static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
|
||||
|
@ -691,21 +578,6 @@ static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
|
|||
.win_cfg_offset = orion_mbus_win_offset,
|
||||
.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
|
||||
.show_cpu_target = mvebu_sdram_debug_show_orion,
|
||||
.map = orion5x_map,
|
||||
};
|
||||
|
||||
static const struct mvebu_mbus_mapping mv78xx0_map[] = {
|
||||
MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
|
||||
MAPDEF("pcie0.1", 4, 0xd0, MAPDEF_PCIMASK),
|
||||
MAPDEF("pcie0.2", 4, 0xb0, MAPDEF_PCIMASK),
|
||||
MAPDEF("pcie0.3", 4, 0x70, MAPDEF_PCIMASK),
|
||||
MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
|
||||
MAPDEF("pcie1.1", 8, 0xd0, MAPDEF_PCIMASK),
|
||||
MAPDEF("pcie1.2", 8, 0xb0, MAPDEF_PCIMASK),
|
||||
MAPDEF("pcie1.3", 8, 0x70, MAPDEF_PCIMASK),
|
||||
MAPDEF("pcie2.0", 4, 0xf0, MAPDEF_PCIMASK),
|
||||
MAPDEF("pcie3.0", 8, 0xf0, MAPDEF_PCIMASK),
|
||||
{},
|
||||
};
|
||||
|
||||
static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
|
||||
|
@ -714,7 +586,6 @@ static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
|
|||
.win_cfg_offset = mv78xx0_mbus_win_offset,
|
||||
.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
|
||||
.show_cpu_target = mvebu_sdram_debug_show_orion,
|
||||
.map = mv78xx0_map,
|
||||
};
|
||||
|
||||
/*
|
||||
|
@ -725,9 +596,9 @@ static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
|
|||
*/
|
||||
static const struct of_device_id of_mvebu_mbus_ids[] = {
|
||||
{ .compatible = "marvell,armada370-mbus",
|
||||
.data = &armada_370_mbus_data, },
|
||||
.data = &armada_370_xp_mbus_data, },
|
||||
{ .compatible = "marvell,armadaxp-mbus",
|
||||
.data = &armada_xp_mbus_data, },
|
||||
.data = &armada_370_xp_mbus_data, },
|
||||
{ .compatible = "marvell,kirkwood-mbus",
|
||||
.data = &kirkwood_mbus_data, },
|
||||
{ .compatible = "marvell,dove-mbus",
|
||||
|
@ -748,48 +619,27 @@ static const struct of_device_id of_mvebu_mbus_ids[] = {
|
|||
/*
|
||||
* Public API of the driver
|
||||
*/
|
||||
int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base,
|
||||
size_t size, phys_addr_t remap,
|
||||
unsigned int flags)
|
||||
int mvebu_mbus_add_window_remap_by_id(unsigned int target,
|
||||
unsigned int attribute,
|
||||
phys_addr_t base, size_t size,
|
||||
phys_addr_t remap)
|
||||
{
|
||||
struct mvebu_mbus_state *s = &mbus_state;
|
||||
u8 target, attr;
|
||||
int i;
|
||||
|
||||
if (!s->soc->map)
|
||||
return -ENODEV;
|
||||
|
||||
for (i = 0; s->soc->map[i].name; i++)
|
||||
if (!strcmp(s->soc->map[i].name, devname))
|
||||
break;
|
||||
|
||||
if (!s->soc->map[i].name) {
|
||||
pr_err("unknown device '%s'\n", devname);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
target = s->soc->map[i].target;
|
||||
attr = s->soc->map[i].attr;
|
||||
|
||||
if (flags == MVEBU_MBUS_PCI_MEM)
|
||||
attr |= 0x8;
|
||||
else if (flags == MVEBU_MBUS_PCI_WA)
|
||||
attr |= 0x28;
|
||||
|
||||
if (!mvebu_mbus_window_conflicts(s, base, size, target, attr)) {
|
||||
pr_err("cannot add window '%s', conflicts with another window\n",
|
||||
devname);
|
||||
if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
|
||||
pr_err("cannot add window '%x:%x', conflicts with another window\n",
|
||||
target, attribute);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return mvebu_mbus_alloc_window(s, base, size, remap, target, attr);
|
||||
|
||||
return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
|
||||
}
|
||||
|
||||
int mvebu_mbus_add_window(const char *devname, phys_addr_t base, size_t size)
|
||||
int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
|
||||
phys_addr_t base, size_t size)
|
||||
{
|
||||
return mvebu_mbus_add_window_remap_flags(devname, base, size,
|
||||
MVEBU_MBUS_NO_REMAP, 0);
|
||||
return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
|
||||
size, MVEBU_MBUS_NO_REMAP);
|
||||
}
|
||||
|
||||
int mvebu_mbus_del_window(phys_addr_t base, size_t size)
|
||||
|
@ -804,6 +654,20 @@ int mvebu_mbus_del_window(phys_addr_t base, size_t size)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
|
||||
{
|
||||
if (!res)
|
||||
return;
|
||||
*res = mbus_state.pcie_mem_aperture;
|
||||
}
|
||||
|
||||
void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
|
||||
{
|
||||
if (!res)
|
||||
return;
|
||||
*res = mbus_state.pcie_io_aperture;
|
||||
}
|
||||
|
||||
static __init int mvebu_mbus_debugfs_init(void)
|
||||
{
|
||||
struct mvebu_mbus_state *s = &mbus_state;
|
||||
|
@ -830,26 +694,14 @@ static __init int mvebu_mbus_debugfs_init(void)
|
|||
}
|
||||
fs_initcall(mvebu_mbus_debugfs_init);
|
||||
|
||||
int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
|
||||
size_t mbuswins_size,
|
||||
phys_addr_t sdramwins_phys_base,
|
||||
size_t sdramwins_size)
|
||||
static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
|
||||
phys_addr_t mbuswins_phys_base,
|
||||
size_t mbuswins_size,
|
||||
phys_addr_t sdramwins_phys_base,
|
||||
size_t sdramwins_size)
|
||||
{
|
||||
struct mvebu_mbus_state *mbus = &mbus_state;
|
||||
const struct of_device_id *of_id;
|
||||
int win;
|
||||
|
||||
for (of_id = of_mvebu_mbus_ids; of_id->compatible; of_id++)
|
||||
if (!strcmp(of_id->compatible, soc))
|
||||
break;
|
||||
|
||||
if (!of_id->compatible) {
|
||||
pr_err("could not find a matching SoC family\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
mbus->soc = of_id->data;
|
||||
|
||||
mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
|
||||
if (!mbus->mbuswins_base)
|
||||
return -ENOMEM;
|
||||
|
@ -870,3 +722,218 @@ int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
|
||||
size_t mbuswins_size,
|
||||
phys_addr_t sdramwins_phys_base,
|
||||
size_t sdramwins_size)
|
||||
{
|
||||
const struct of_device_id *of_id;
|
||||
|
||||
for (of_id = of_mvebu_mbus_ids; of_id->compatible; of_id++)
|
||||
if (!strcmp(of_id->compatible, soc))
|
||||
break;
|
||||
|
||||
if (!of_id->compatible) {
|
||||
pr_err("could not find a matching SoC family\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
mbus_state.soc = of_id->data;
|
||||
|
||||
return mvebu_mbus_common_init(&mbus_state,
|
||||
mbuswins_phys_base,
|
||||
mbuswins_size,
|
||||
sdramwins_phys_base,
|
||||
sdramwins_size);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
/*
|
||||
* The window IDs in the ranges DT property have the following format:
|
||||
* - bits 28 to 31: MBus custom field
|
||||
* - bits 24 to 27: window target ID
|
||||
* - bits 16 to 23: window attribute ID
|
||||
* - bits 0 to 15: unused
|
||||
*/
|
||||
#define CUSTOM(id) (((id) & 0xF0000000) >> 24)
|
||||
#define TARGET(id) (((id) & 0x0F000000) >> 24)
|
||||
#define ATTR(id) (((id) & 0x00FF0000) >> 16)
|
||||
|
||||
static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
|
||||
u32 base, u32 size,
|
||||
u8 target, u8 attr)
|
||||
{
|
||||
if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
|
||||
pr_err("cannot add window '%04x:%04x', conflicts with another window\n",
|
||||
target, attr);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
|
||||
target, attr)) {
|
||||
pr_err("cannot add window '%04x:%04x', too many windows\n",
|
||||
target, attr);
|
||||
return -ENOMEM;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init
|
||||
mbus_parse_ranges(struct device_node *node,
|
||||
int *addr_cells, int *c_addr_cells, int *c_size_cells,
|
||||
int *cell_count, const __be32 **ranges_start,
|
||||
const __be32 **ranges_end)
|
||||
{
|
||||
const __be32 *prop;
|
||||
int ranges_len, tuple_len;
|
||||
|
||||
/* Allow a node with no 'ranges' property */
|
||||
*ranges_start = of_get_property(node, "ranges", &ranges_len);
|
||||
if (*ranges_start == NULL) {
|
||||
*addr_cells = *c_addr_cells = *c_size_cells = *cell_count = 0;
|
||||
*ranges_start = *ranges_end = NULL;
|
||||
return 0;
|
||||
}
|
||||
*ranges_end = *ranges_start + ranges_len / sizeof(__be32);
|
||||
|
||||
*addr_cells = of_n_addr_cells(node);
|
||||
|
||||
prop = of_get_property(node, "#address-cells", NULL);
|
||||
*c_addr_cells = be32_to_cpup(prop);
|
||||
|
||||
prop = of_get_property(node, "#size-cells", NULL);
|
||||
*c_size_cells = be32_to_cpup(prop);
|
||||
|
||||
*cell_count = *addr_cells + *c_addr_cells + *c_size_cells;
|
||||
tuple_len = (*cell_count) * sizeof(__be32);
|
||||
|
||||
if (ranges_len % tuple_len) {
|
||||
pr_warn("malformed ranges entry '%s'\n", node->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus,
|
||||
struct device_node *np)
|
||||
{
|
||||
int addr_cells, c_addr_cells, c_size_cells;
|
||||
int i, ret, cell_count;
|
||||
const __be32 *r, *ranges_start, *ranges_end;
|
||||
|
||||
ret = mbus_parse_ranges(np, &addr_cells, &c_addr_cells,
|
||||
&c_size_cells, &cell_count,
|
||||
&ranges_start, &ranges_end);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
for (i = 0, r = ranges_start; r < ranges_end; r += cell_count, i++) {
|
||||
u32 windowid, base, size;
|
||||
u8 target, attr;
|
||||
|
||||
/*
|
||||
* An entry with a non-zero custom field do not
|
||||
* correspond to a static window, so skip it.
|
||||
*/
|
||||
windowid = of_read_number(r, 1);
|
||||
if (CUSTOM(windowid))
|
||||
continue;
|
||||
|
||||
target = TARGET(windowid);
|
||||
attr = ATTR(windowid);
|
||||
|
||||
base = of_read_number(r + c_addr_cells, addr_cells);
|
||||
size = of_read_number(r + c_addr_cells + addr_cells,
|
||||
c_size_cells);
|
||||
ret = mbus_dt_setup_win(mbus, base, size, target, attr);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
|
||||
struct resource *mem,
|
||||
struct resource *io)
|
||||
{
|
||||
u32 reg[2];
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* These are optional, so we clear them and they'll
|
||||
* be zero if they are missing from the DT.
|
||||
*/
|
||||
memset(mem, 0, sizeof(struct resource));
|
||||
memset(io, 0, sizeof(struct resource));
|
||||
|
||||
ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg));
|
||||
if (!ret) {
|
||||
mem->start = reg[0];
|
||||
mem->end = mem->start + reg[1];
|
||||
mem->flags = IORESOURCE_MEM;
|
||||
}
|
||||
|
||||
ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg));
|
||||
if (!ret) {
|
||||
io->start = reg[0];
|
||||
io->end = io->start + reg[1];
|
||||
io->flags = IORESOURCE_IO;
|
||||
}
|
||||
}
|
||||
|
||||
int __init mvebu_mbus_dt_init(void)
|
||||
{
|
||||
struct resource mbuswins_res, sdramwins_res;
|
||||
struct device_node *np, *controller;
|
||||
const struct of_device_id *of_id;
|
||||
const __be32 *prop;
|
||||
int ret;
|
||||
|
||||
np = of_find_matching_node(NULL, of_mvebu_mbus_ids);
|
||||
if (!np) {
|
||||
pr_err("could not find a matching SoC family\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
of_id = of_match_node(of_mvebu_mbus_ids, np);
|
||||
mbus_state.soc = of_id->data;
|
||||
|
||||
prop = of_get_property(np, "controller", NULL);
|
||||
if (!prop) {
|
||||
pr_err("required 'controller' property missing\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
controller = of_find_node_by_phandle(be32_to_cpup(prop));
|
||||
if (!controller) {
|
||||
pr_err("could not find an 'mbus-controller' node\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (of_address_to_resource(controller, 0, &mbuswins_res)) {
|
||||
pr_err("cannot get MBUS register address\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (of_address_to_resource(controller, 1, &sdramwins_res)) {
|
||||
pr_err("cannot get SDRAM register address\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Get optional pcie-{mem,io}-aperture properties */
|
||||
mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture,
|
||||
&mbus_state.pcie_io_aperture);
|
||||
|
||||
ret = mvebu_mbus_common_init(&mbus_state,
|
||||
mbuswins_res.start,
|
||||
resource_size(&mbuswins_res),
|
||||
sdramwins_res.start,
|
||||
resource_size(&sdramwins_res));
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Setup statically declared windows in the DT */
|
||||
return mbus_dt_setup(&mbus_state, np);
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -44,14 +44,6 @@
|
|||
#define READ_PARAM_OFFSET 0x0
|
||||
#define WRITE_PARAM_OFFSET 0x4
|
||||
|
||||
static const char * const devbus_wins[] = {
|
||||
"devbus-boot",
|
||||
"devbus-cs0",
|
||||
"devbus-cs1",
|
||||
"devbus-cs2",
|
||||
"devbus-cs3",
|
||||
};
|
||||
|
||||
struct devbus_read_params {
|
||||
u32 bus_width;
|
||||
u32 badr_skew;
|
||||
|
@ -208,16 +200,11 @@ static int mvebu_devbus_probe(struct platform_device *pdev)
|
|||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
struct device_node *parent;
|
||||
struct devbus *devbus;
|
||||
struct resource *res;
|
||||
struct clk *clk;
|
||||
unsigned long rate;
|
||||
const __be32 *ranges;
|
||||
int err, cs;
|
||||
int addr_cells, p_addr_cells, size_cells;
|
||||
int ranges_len, tuple_len;
|
||||
u32 base, size;
|
||||
int err;
|
||||
|
||||
devbus = devm_kzalloc(&pdev->dev, sizeof(struct devbus), GFP_KERNEL);
|
||||
if (!devbus)
|
||||
|
@ -247,69 +234,14 @@ static int mvebu_devbus_probe(struct platform_device *pdev)
|
|||
if (err < 0)
|
||||
return err;
|
||||
|
||||
/*
|
||||
* Allocate an address window for this device.
|
||||
* If the device probing fails, then we won't be able to
|
||||
* remove the allocated address decoding window.
|
||||
*
|
||||
* FIXME: This is only a temporary hack! We need to do this here
|
||||
* because we still don't have device tree bindings for mbus.
|
||||
* Once that support is added, we will declare these address windows
|
||||
* statically in the device tree, and remove the window configuration
|
||||
* from here.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Get the CS to choose the window string.
|
||||
* This is a bit hacky, but it will be removed once the
|
||||
* address windows are declared in the device tree.
|
||||
*/
|
||||
cs = (((unsigned long)devbus->base) % 0x400) / 8;
|
||||
|
||||
/*
|
||||
* Parse 'ranges' property to obtain a (base,size) window tuple.
|
||||
* This will be removed once the address windows
|
||||
* are declared in the device tree.
|
||||
*/
|
||||
parent = of_get_parent(node);
|
||||
if (!parent)
|
||||
return -EINVAL;
|
||||
|
||||
p_addr_cells = of_n_addr_cells(parent);
|
||||
of_node_put(parent);
|
||||
|
||||
addr_cells = of_n_addr_cells(node);
|
||||
size_cells = of_n_size_cells(node);
|
||||
tuple_len = (p_addr_cells + addr_cells + size_cells) * sizeof(__be32);
|
||||
|
||||
ranges = of_get_property(node, "ranges", &ranges_len);
|
||||
if (ranges == NULL || ranges_len != tuple_len)
|
||||
return -EINVAL;
|
||||
|
||||
base = of_translate_address(node, ranges + addr_cells);
|
||||
if (base == OF_BAD_ADDR)
|
||||
return -EINVAL;
|
||||
size = of_read_number(ranges + addr_cells + p_addr_cells, size_cells);
|
||||
|
||||
/*
|
||||
* Create an mbus address windows.
|
||||
* FIXME: Remove this, together with the above code, once the
|
||||
* address windows are declared in the device tree.
|
||||
*/
|
||||
err = mvebu_mbus_add_window(devbus_wins[cs], base, size);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
/*
|
||||
* We need to create a child device explicitly from here to
|
||||
* guarantee that the child will be probed after the timing
|
||||
* parameters for the bus are written.
|
||||
*/
|
||||
err = of_platform_populate(node, NULL, NULL, dev);
|
||||
if (err < 0) {
|
||||
mvebu_mbus_del_window(base, size);
|
||||
if (err < 0)
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -123,6 +123,10 @@ struct mvebu_pcie_port {
|
|||
u32 port;
|
||||
u32 lane;
|
||||
int devfn;
|
||||
unsigned int mem_target;
|
||||
unsigned int mem_attr;
|
||||
unsigned int io_target;
|
||||
unsigned int io_attr;
|
||||
struct clk *clk;
|
||||
struct mvebu_sw_pci_bridge bridge;
|
||||
struct device_node *dn;
|
||||
|
@ -307,10 +311,9 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
|
|||
(port->bridge.iolimitupper << 16)) -
|
||||
iobase);
|
||||
|
||||
mvebu_mbus_add_window_remap_flags(port->name, port->iowin_base,
|
||||
port->iowin_size,
|
||||
iobase,
|
||||
MVEBU_MBUS_PCI_IO);
|
||||
mvebu_mbus_add_window_remap_by_id(port->io_target, port->io_attr,
|
||||
port->iowin_base, port->iowin_size,
|
||||
iobase);
|
||||
|
||||
pci_ioremap_io(iobase, port->iowin_base);
|
||||
}
|
||||
|
@ -342,10 +345,8 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
|
|||
(((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
|
||||
port->memwin_base;
|
||||
|
||||
mvebu_mbus_add_window_remap_flags(port->name, port->memwin_base,
|
||||
port->memwin_size,
|
||||
MVEBU_MBUS_NO_REMAP,
|
||||
MVEBU_MBUS_PCI_MEM);
|
||||
mvebu_mbus_add_window_by_id(port->mem_target, port->mem_attr,
|
||||
port->memwin_base, port->memwin_size);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -661,6 +662,8 @@ static int __init mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
|
|||
|
||||
for (i = 0; i < pcie->nports; i++) {
|
||||
struct mvebu_pcie_port *port = &pcie->ports[i];
|
||||
if (!port->base)
|
||||
continue;
|
||||
mvebu_pcie_setup_hw(port);
|
||||
}
|
||||
|
||||
|
@ -755,12 +758,54 @@ mvebu_pcie_map_registers(struct platform_device *pdev,
|
|||
return devm_request_and_ioremap(&pdev->dev, ®s);
|
||||
}
|
||||
|
||||
#define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
|
||||
#define DT_TYPE_IO 0x1
|
||||
#define DT_TYPE_MEM32 0x2
|
||||
#define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
|
||||
#define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
|
||||
|
||||
static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
|
||||
unsigned long type, int *tgt, int *attr)
|
||||
{
|
||||
const int na = 3, ns = 2;
|
||||
const __be32 *range;
|
||||
int rlen, nranges, rangesz, pna, i;
|
||||
|
||||
range = of_get_property(np, "ranges", &rlen);
|
||||
if (!range)
|
||||
return -EINVAL;
|
||||
|
||||
pna = of_n_addr_cells(np);
|
||||
rangesz = pna + na + ns;
|
||||
nranges = rlen / sizeof(__be32) / rangesz;
|
||||
|
||||
for (i = 0; i < nranges; i++) {
|
||||
u32 flags = of_read_number(range, 1);
|
||||
u32 slot = of_read_number(range, 2);
|
||||
u64 cpuaddr = of_read_number(range + na, pna);
|
||||
unsigned long rtype;
|
||||
|
||||
if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
|
||||
rtype = IORESOURCE_IO;
|
||||
else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
|
||||
rtype = IORESOURCE_MEM;
|
||||
|
||||
if (slot == PCI_SLOT(devfn) && type == rtype) {
|
||||
*tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
|
||||
*attr = DT_CPUADDR_TO_ATTR(cpuaddr);
|
||||
return 0;
|
||||
}
|
||||
|
||||
range += rangesz;
|
||||
}
|
||||
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
static int __init mvebu_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct mvebu_pcie *pcie;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct of_pci_range range;
|
||||
struct of_pci_range_parser parser;
|
||||
struct device_node *child;
|
||||
int i, ret;
|
||||
|
||||
|
@ -771,29 +816,25 @@ static int __init mvebu_pcie_probe(struct platform_device *pdev)
|
|||
|
||||
pcie->pdev = pdev;
|
||||
|
||||
if (of_pci_range_parser_init(&parser, np))
|
||||
/* Get the PCIe memory and I/O aperture */
|
||||
mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
|
||||
if (resource_size(&pcie->mem) == 0) {
|
||||
dev_err(&pdev->dev, "invalid memory aperture size\n");
|
||||
return -EINVAL;
|
||||
|
||||
/* Get the I/O and memory ranges from DT */
|
||||
for_each_of_pci_range(&parser, &range) {
|
||||
unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
|
||||
if (restype == IORESOURCE_IO) {
|
||||
of_pci_range_to_resource(&range, np, &pcie->io);
|
||||
of_pci_range_to_resource(&range, np, &pcie->realio);
|
||||
pcie->io.name = "I/O";
|
||||
pcie->realio.start = max_t(resource_size_t,
|
||||
PCIBIOS_MIN_IO,
|
||||
range.pci_addr);
|
||||
pcie->realio.end = min_t(resource_size_t,
|
||||
IO_SPACE_LIMIT,
|
||||
range.pci_addr + range.size);
|
||||
}
|
||||
if (restype == IORESOURCE_MEM) {
|
||||
of_pci_range_to_resource(&range, np, &pcie->mem);
|
||||
pcie->mem.name = "MEM";
|
||||
}
|
||||
}
|
||||
|
||||
mvebu_mbus_get_pcie_io_aperture(&pcie->io);
|
||||
if (resource_size(&pcie->io) == 0) {
|
||||
dev_err(&pdev->dev, "invalid I/O aperture size\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pcie->realio.flags = pcie->io.flags;
|
||||
pcie->realio.start = PCIBIOS_MIN_IO;
|
||||
pcie->realio.end = min_t(resource_size_t,
|
||||
IO_SPACE_LIMIT,
|
||||
resource_size(&pcie->io));
|
||||
|
||||
/* Get the bus range */
|
||||
ret = of_pci_parse_bus_range(np, &pcie->busn);
|
||||
if (ret) {
|
||||
|
@ -841,6 +882,22 @@ static int __init mvebu_pcie_probe(struct platform_device *pdev)
|
|||
if (port->devfn < 0)
|
||||
continue;
|
||||
|
||||
ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_MEM,
|
||||
&port->mem_target, &port->mem_attr);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for mem window\n",
|
||||
port->port, port->lane);
|
||||
continue;
|
||||
}
|
||||
|
||||
ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_IO,
|
||||
&port->io_target, &port->io_attr);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for io window\n",
|
||||
port->port, port->lane);
|
||||
continue;
|
||||
}
|
||||
|
||||
port->base = mvebu_pcie_map_registers(pdev, child, port);
|
||||
if (!port->base) {
|
||||
dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
|
||||
|
|
|
@ -11,6 +11,8 @@
|
|||
#ifndef __LINUX_MBUS_H
|
||||
#define __LINUX_MBUS_H
|
||||
|
||||
struct resource;
|
||||
|
||||
struct mbus_dram_target_info
|
||||
{
|
||||
/*
|
||||
|
@ -59,14 +61,18 @@ static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base,
|
||||
size_t size, phys_addr_t remap,
|
||||
unsigned int flags);
|
||||
int mvebu_mbus_add_window(const char *devname, phys_addr_t base,
|
||||
size_t size);
|
||||
void mvebu_mbus_get_pcie_mem_aperture(struct resource *res);
|
||||
void mvebu_mbus_get_pcie_io_aperture(struct resource *res);
|
||||
int mvebu_mbus_add_window_remap_by_id(unsigned int target,
|
||||
unsigned int attribute,
|
||||
phys_addr_t base, size_t size,
|
||||
phys_addr_t remap);
|
||||
int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
|
||||
phys_addr_t base, size_t size);
|
||||
int mvebu_mbus_del_window(phys_addr_t base, size_t size);
|
||||
int mvebu_mbus_init(const char *soc, phys_addr_t mbus_phys_base,
|
||||
size_t mbus_size, phys_addr_t sdram_phys_base,
|
||||
size_t sdram_size);
|
||||
int mvebu_mbus_dt_init(void);
|
||||
|
||||
#endif /* __LINUX_MBUS_H */
|
||||
|
|
Loading…
Reference in a new issue