iommu/mediatek: Fix protect memory setting
[ Upstream commitpull/10/head70ca608b2e
] In MediaTek's IOMMU design, When a iommu translation fault occurs (HW can NOT translate the destination address to a valid physical address), the IOMMU HW output the dirty data into a special memory to avoid corrupting the main memory, this is called "protect memory". the register(0x114) for protect memory is a little different between mt8173 and mt2712. In the mt8173, bit[30:6] in the register represents [31:7] of the physical address. In the 4GB mode, the register bit[31] should be 1. While in the mt2712, the bits don't shift. bit[31:7] in the register represents [31:7] in the physical address, and bit[1:0] in the register represents bit[33:32] of the physical address if it has. Fixes:e6dec92308
("iommu/mediatek: Add mt2712 IOMMU support") Reported-by: Honghui Zhang <honghui.zhang@mediatek.com> Signed-off-by: Yong Wu <yong.wu@mediatek.com> Signed-off-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
parent
8c8f0b1f59
commit
f69b52965d
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@ -60,7 +60,7 @@
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(((prot) & 0x3) << F_MMU_TF_PROTECT_SEL_SHIFT(data))
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#define REG_MMU_IVRP_PADDR 0x114
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#define F_MMU_IVRP_PA_SET(pa, ext) (((pa) >> 1) | ((!!(ext)) << 31))
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#define REG_MMU_VLD_PA_RNG 0x118
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#define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA))
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@ -532,8 +532,13 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
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F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
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writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
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writel_relaxed(F_MMU_IVRP_PA_SET(data->protect_base, data->enable_4GB),
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data->base + REG_MMU_IVRP_PADDR);
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if (data->m4u_plat == M4U_MT8173)
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regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
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else
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regval = lower_32_bits(data->protect_base) |
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upper_32_bits(data->protect_base);
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writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
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if (data->enable_4GB && data->m4u_plat != M4U_MT8173) {
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/*
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* If 4GB mode is enabled, the validate PA range is from
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@ -688,6 +693,7 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev)
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reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
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reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0);
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reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
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reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR);
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clk_disable_unprepare(data->bclk);
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return 0;
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}
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@ -710,8 +716,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
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writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
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writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);
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writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
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writel_relaxed(F_MMU_IVRP_PA_SET(data->protect_base, data->enable_4GB),
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base + REG_MMU_IVRP_PADDR);
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writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR);
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if (data->m4u_dom)
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writel(data->m4u_dom->cfg.arm_v7s_cfg.ttbr[0],
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base + REG_MMU_PT_BASE_ADDR);
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@ -32,6 +32,7 @@ struct mtk_iommu_suspend_reg {
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u32 ctrl_reg;
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u32 int_control0;
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u32 int_main_control;
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u32 ivrp_paddr;
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};
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enum mtk_iommu_plat {
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