drm/radeon: update cik init for Mullins.
Also add golden registers, update firmware loading functions. Signed-off-by: Samuel Li <samuel.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com>wifi-calibration
parent
b0a9f22a18
commit
f73a9e8372
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@ -63,6 +63,12 @@ MODULE_FIRMWARE("radeon/KABINI_ce.bin");
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MODULE_FIRMWARE("radeon/KABINI_mec.bin");
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MODULE_FIRMWARE("radeon/KABINI_mec.bin");
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MODULE_FIRMWARE("radeon/KABINI_rlc.bin");
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MODULE_FIRMWARE("radeon/KABINI_rlc.bin");
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MODULE_FIRMWARE("radeon/KABINI_sdma.bin");
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MODULE_FIRMWARE("radeon/KABINI_sdma.bin");
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MODULE_FIRMWARE("radeon/MULLINS_pfp.bin");
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MODULE_FIRMWARE("radeon/MULLINS_me.bin");
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MODULE_FIRMWARE("radeon/MULLINS_ce.bin");
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MODULE_FIRMWARE("radeon/MULLINS_mec.bin");
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MODULE_FIRMWARE("radeon/MULLINS_rlc.bin");
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MODULE_FIRMWARE("radeon/MULLINS_sdma.bin");
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extern int r600_ih_ring_alloc(struct radeon_device *rdev);
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extern int r600_ih_ring_alloc(struct radeon_device *rdev);
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extern void r600_ih_ring_fini(struct radeon_device *rdev);
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extern void r600_ih_ring_fini(struct radeon_device *rdev);
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@ -1473,6 +1479,43 @@ static const u32 hawaii_mgcg_cgcg_init[] =
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0xd80c, 0xff000ff0, 0x00000100
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0xd80c, 0xff000ff0, 0x00000100
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};
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};
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static const u32 godavari_golden_registers[] =
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{
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0x55e4, 0xff607fff, 0xfc000100,
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0x6ed8, 0x00010101, 0x00010000,
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0x9830, 0xffffffff, 0x00000000,
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0x98302, 0xf00fffff, 0x00000400,
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0x6130, 0xffffffff, 0x00010000,
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0x5bb0, 0x000000f0, 0x00000070,
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0x5bc0, 0xf0311fff, 0x80300000,
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0x98f8, 0x73773777, 0x12010001,
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0x98fc, 0xffffffff, 0x00000010,
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0x8030, 0x00001f0f, 0x0000100a,
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0x2f48, 0x73773777, 0x12010001,
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0x2408, 0x000fffff, 0x000c007f,
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0x8a14, 0xf000003f, 0x00000007,
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0x8b24, 0xffffffff, 0x00ff0fff,
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0x30a04, 0x0000ff0f, 0x00000000,
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0x28a4c, 0x07ffffff, 0x06000000,
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0x4d8, 0x00000fff, 0x00000100,
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0xd014, 0x00010000, 0x00810001,
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0xd814, 0x00010000, 0x00810001,
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0x3e78, 0x00000001, 0x00000002,
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0xc768, 0x00000008, 0x00000008,
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0xc770, 0x00000f00, 0x00000800,
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0xc774, 0x00000f00, 0x00000800,
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0xc798, 0x00ffffff, 0x00ff7fbf,
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0xc79c, 0x00ffffff, 0x00ff7faf,
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0x8c00, 0x000000ff, 0x00000001,
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0x214f8, 0x01ff01ff, 0x00000002,
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0x21498, 0x007ff800, 0x00200000,
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0x2015c, 0xffffffff, 0x00000f40,
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0x88c4, 0x001f3ae3, 0x00000082,
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0x88d4, 0x0000001f, 0x00000010,
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0x30934, 0xffffffff, 0x00000000
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};
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static void cik_init_golden_registers(struct radeon_device *rdev)
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static void cik_init_golden_registers(struct radeon_device *rdev)
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{
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{
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switch (rdev->family) {
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switch (rdev->family) {
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@ -1504,6 +1547,20 @@ static void cik_init_golden_registers(struct radeon_device *rdev)
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kalindi_golden_spm_registers,
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kalindi_golden_spm_registers,
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(const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
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(const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
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break;
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break;
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case CHIP_MULLINS:
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radeon_program_register_sequence(rdev,
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kalindi_mgcg_cgcg_init,
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(const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
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radeon_program_register_sequence(rdev,
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godavari_golden_registers,
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(const u32)ARRAY_SIZE(godavari_golden_registers));
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radeon_program_register_sequence(rdev,
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kalindi_golden_common_registers,
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(const u32)ARRAY_SIZE(kalindi_golden_common_registers));
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radeon_program_register_sequence(rdev,
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kalindi_golden_spm_registers,
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(const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
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break;
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case CHIP_KAVERI:
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case CHIP_KAVERI:
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radeon_program_register_sequence(rdev,
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radeon_program_register_sequence(rdev,
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spectre_mgcg_cgcg_init,
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spectre_mgcg_cgcg_init,
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@ -1834,6 +1891,15 @@ static int cik_init_microcode(struct radeon_device *rdev)
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rlc_req_size = KB_RLC_UCODE_SIZE * 4;
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rlc_req_size = KB_RLC_UCODE_SIZE * 4;
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sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
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sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
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break;
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break;
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case CHIP_MULLINS:
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chip_name = "MULLINS";
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pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
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me_req_size = CIK_ME_UCODE_SIZE * 4;
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ce_req_size = CIK_CE_UCODE_SIZE * 4;
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mec_req_size = CIK_MEC_UCODE_SIZE * 4;
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rlc_req_size = ML_RLC_UCODE_SIZE * 4;
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sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
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break;
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default: BUG();
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default: BUG();
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}
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}
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@ -3272,6 +3338,7 @@ static void cik_gpu_init(struct radeon_device *rdev)
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gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
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gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
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break;
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break;
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case CHIP_KABINI:
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case CHIP_KABINI:
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case CHIP_MULLINS:
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default:
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default:
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rdev->config.cik.max_shader_engines = 1;
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rdev->config.cik.max_shader_engines = 1;
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rdev->config.cik.max_tile_pipes = 2;
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rdev->config.cik.max_tile_pipes = 2;
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@ -5801,6 +5868,9 @@ static int cik_rlc_resume(struct radeon_device *rdev)
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case CHIP_KABINI:
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case CHIP_KABINI:
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size = KB_RLC_UCODE_SIZE;
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size = KB_RLC_UCODE_SIZE;
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break;
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break;
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case CHIP_MULLINS:
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size = ML_RLC_UCODE_SIZE;
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break;
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}
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}
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cik_rlc_stop(rdev);
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cik_rlc_stop(rdev);
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@ -6549,6 +6619,7 @@ void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer)
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buffer[count++] = cpu_to_le32(0x00000000);
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buffer[count++] = cpu_to_le32(0x00000000);
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break;
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break;
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case CHIP_KABINI:
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case CHIP_KABINI:
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case CHIP_MULLINS:
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buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
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buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
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buffer[count++] = cpu_to_le32(0x00000000);
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buffer[count++] = cpu_to_le32(0x00000000);
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break;
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break;
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@ -52,6 +52,7 @@
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#define BONAIRE_RLC_UCODE_SIZE 2048
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#define BONAIRE_RLC_UCODE_SIZE 2048
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#define KB_RLC_UCODE_SIZE 2560
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#define KB_RLC_UCODE_SIZE 2560
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#define KV_RLC_UCODE_SIZE 2560
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#define KV_RLC_UCODE_SIZE 2560
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#define ML_RLC_UCODE_SIZE 2560
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/* MC */
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/* MC */
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#define BTC_MC_UCODE_SIZE 6024
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#define BTC_MC_UCODE_SIZE 6024
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