Merge branch 'clk-fixes' into clk-next
* clk-fixes: clk: mediatek: mt8173: Fix enabling of critical clocks drivers: clk: st: Fix mux bit-setting for Cortex A9 clocks drivers: clk: st: Add CLK_GET_RATE_NOCACHE flag to clocks drivers: clk: st: Fix flexgen lock init drivers: clk: st: Fix FSYN channel values drivers: clk: st: Remove unused code clk: qcom: Use parent rate when set rate to pixel RCG clock clk: at91: do not leak resources clk: stm32: Fix out-by-one error path in the index lookup clk: iproc: fix bit manipulation arithmetic clk: iproc: fix memory leak from clock name
This commit is contained in:
commit
f75073fabd
|
@ -116,8 +116,10 @@ void __init of_sama5d4_clk_h32mx_setup(struct device_node *np,
|
||||||
h32mxclk->pmc = pmc;
|
h32mxclk->pmc = pmc;
|
||||||
|
|
||||||
clk = clk_register(NULL, &h32mxclk->hw);
|
clk = clk_register(NULL, &h32mxclk->hw);
|
||||||
if (!clk)
|
if (!clk) {
|
||||||
|
kfree(h32mxclk);
|
||||||
return;
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
||||||
}
|
}
|
||||||
|
|
|
@ -171,8 +171,10 @@ at91_clk_register_main_osc(struct at91_pmc *pmc,
|
||||||
irq_set_status_flags(osc->irq, IRQ_NOAUTOEN);
|
irq_set_status_flags(osc->irq, IRQ_NOAUTOEN);
|
||||||
ret = request_irq(osc->irq, clk_main_osc_irq_handler,
|
ret = request_irq(osc->irq, clk_main_osc_irq_handler,
|
||||||
IRQF_TRIGGER_HIGH, name, osc);
|
IRQF_TRIGGER_HIGH, name, osc);
|
||||||
if (ret)
|
if (ret) {
|
||||||
|
kfree(osc);
|
||||||
return ERR_PTR(ret);
|
return ERR_PTR(ret);
|
||||||
|
}
|
||||||
|
|
||||||
if (bypass)
|
if (bypass)
|
||||||
pmc_write(pmc, AT91_CKGR_MOR,
|
pmc_write(pmc, AT91_CKGR_MOR,
|
||||||
|
|
|
@ -165,12 +165,16 @@ at91_clk_register_master(struct at91_pmc *pmc, unsigned int irq,
|
||||||
irq_set_status_flags(master->irq, IRQ_NOAUTOEN);
|
irq_set_status_flags(master->irq, IRQ_NOAUTOEN);
|
||||||
ret = request_irq(master->irq, clk_master_irq_handler,
|
ret = request_irq(master->irq, clk_master_irq_handler,
|
||||||
IRQF_TRIGGER_HIGH, "clk-master", master);
|
IRQF_TRIGGER_HIGH, "clk-master", master);
|
||||||
if (ret)
|
if (ret) {
|
||||||
|
kfree(master);
|
||||||
return ERR_PTR(ret);
|
return ERR_PTR(ret);
|
||||||
|
}
|
||||||
|
|
||||||
clk = clk_register(NULL, &master->hw);
|
clk = clk_register(NULL, &master->hw);
|
||||||
if (IS_ERR(clk))
|
if (IS_ERR(clk)) {
|
||||||
|
free_irq(master->irq, master);
|
||||||
kfree(master);
|
kfree(master);
|
||||||
|
}
|
||||||
|
|
||||||
return clk;
|
return clk;
|
||||||
}
|
}
|
||||||
|
|
|
@ -346,12 +346,16 @@ at91_clk_register_pll(struct at91_pmc *pmc, unsigned int irq, const char *name,
|
||||||
irq_set_status_flags(pll->irq, IRQ_NOAUTOEN);
|
irq_set_status_flags(pll->irq, IRQ_NOAUTOEN);
|
||||||
ret = request_irq(pll->irq, clk_pll_irq_handler, IRQF_TRIGGER_HIGH,
|
ret = request_irq(pll->irq, clk_pll_irq_handler, IRQF_TRIGGER_HIGH,
|
||||||
id ? "clk-pllb" : "clk-plla", pll);
|
id ? "clk-pllb" : "clk-plla", pll);
|
||||||
if (ret)
|
if (ret) {
|
||||||
|
kfree(pll);
|
||||||
return ERR_PTR(ret);
|
return ERR_PTR(ret);
|
||||||
|
}
|
||||||
|
|
||||||
clk = clk_register(NULL, &pll->hw);
|
clk = clk_register(NULL, &pll->hw);
|
||||||
if (IS_ERR(clk))
|
if (IS_ERR(clk)) {
|
||||||
|
free_irq(pll->irq, pll);
|
||||||
kfree(pll);
|
kfree(pll);
|
||||||
|
}
|
||||||
|
|
||||||
return clk;
|
return clk;
|
||||||
}
|
}
|
||||||
|
|
|
@ -130,13 +130,17 @@ at91_clk_register_system(struct at91_pmc *pmc, const char *name,
|
||||||
irq_set_status_flags(sys->irq, IRQ_NOAUTOEN);
|
irq_set_status_flags(sys->irq, IRQ_NOAUTOEN);
|
||||||
ret = request_irq(sys->irq, clk_system_irq_handler,
|
ret = request_irq(sys->irq, clk_system_irq_handler,
|
||||||
IRQF_TRIGGER_HIGH, name, sys);
|
IRQF_TRIGGER_HIGH, name, sys);
|
||||||
if (ret)
|
if (ret) {
|
||||||
|
kfree(sys);
|
||||||
return ERR_PTR(ret);
|
return ERR_PTR(ret);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
clk = clk_register(NULL, &sys->hw);
|
clk = clk_register(NULL, &sys->hw);
|
||||||
if (IS_ERR(clk))
|
if (IS_ERR(clk)) {
|
||||||
|
free_irq(sys->irq, sys);
|
||||||
kfree(sys);
|
kfree(sys);
|
||||||
|
}
|
||||||
|
|
||||||
return clk;
|
return clk;
|
||||||
}
|
}
|
||||||
|
|
|
@ -118,12 +118,16 @@ at91_clk_register_utmi(struct at91_pmc *pmc, unsigned int irq,
|
||||||
irq_set_status_flags(utmi->irq, IRQ_NOAUTOEN);
|
irq_set_status_flags(utmi->irq, IRQ_NOAUTOEN);
|
||||||
ret = request_irq(utmi->irq, clk_utmi_irq_handler,
|
ret = request_irq(utmi->irq, clk_utmi_irq_handler,
|
||||||
IRQF_TRIGGER_HIGH, "clk-utmi", utmi);
|
IRQF_TRIGGER_HIGH, "clk-utmi", utmi);
|
||||||
if (ret)
|
if (ret) {
|
||||||
|
kfree(utmi);
|
||||||
return ERR_PTR(ret);
|
return ERR_PTR(ret);
|
||||||
|
}
|
||||||
|
|
||||||
clk = clk_register(NULL, &utmi->hw);
|
clk = clk_register(NULL, &utmi->hw);
|
||||||
if (IS_ERR(clk))
|
if (IS_ERR(clk)) {
|
||||||
|
free_irq(utmi->irq, utmi);
|
||||||
kfree(utmi);
|
kfree(utmi);
|
||||||
|
}
|
||||||
|
|
||||||
return clk;
|
return clk;
|
||||||
}
|
}
|
||||||
|
|
|
@ -222,10 +222,6 @@ void __init iproc_asiu_setup(struct device_node *node,
|
||||||
struct iproc_asiu_clk *asiu_clk;
|
struct iproc_asiu_clk *asiu_clk;
|
||||||
const char *clk_name;
|
const char *clk_name;
|
||||||
|
|
||||||
clk_name = kzalloc(IPROC_CLK_NAME_LEN, GFP_KERNEL);
|
|
||||||
if (WARN_ON(!clk_name))
|
|
||||||
goto err_clk_register;
|
|
||||||
|
|
||||||
ret = of_property_read_string_index(node, "clock-output-names",
|
ret = of_property_read_string_index(node, "clock-output-names",
|
||||||
i, &clk_name);
|
i, &clk_name);
|
||||||
if (WARN_ON(ret))
|
if (WARN_ON(ret))
|
||||||
|
@ -259,7 +255,7 @@ void __init iproc_asiu_setup(struct device_node *node,
|
||||||
|
|
||||||
err_clk_register:
|
err_clk_register:
|
||||||
for (i = 0; i < num_clks; i++)
|
for (i = 0; i < num_clks; i++)
|
||||||
kfree(asiu->clks[i].name);
|
clk_unregister(asiu->clk_data.clks[i]);
|
||||||
iounmap(asiu->gate_base);
|
iounmap(asiu->gate_base);
|
||||||
|
|
||||||
err_iomap_gate:
|
err_iomap_gate:
|
||||||
|
|
|
@ -366,7 +366,7 @@ static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw,
|
||||||
val = readl(pll->pll_base + ctrl->ndiv_int.offset);
|
val = readl(pll->pll_base + ctrl->ndiv_int.offset);
|
||||||
ndiv_int = (val >> ctrl->ndiv_int.shift) &
|
ndiv_int = (val >> ctrl->ndiv_int.shift) &
|
||||||
bit_mask(ctrl->ndiv_int.width);
|
bit_mask(ctrl->ndiv_int.width);
|
||||||
ndiv = ndiv_int << ctrl->ndiv_int.shift;
|
ndiv = (u64)ndiv_int << ctrl->ndiv_int.shift;
|
||||||
|
|
||||||
if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) {
|
if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) {
|
||||||
val = readl(pll->pll_base + ctrl->ndiv_frac.offset);
|
val = readl(pll->pll_base + ctrl->ndiv_frac.offset);
|
||||||
|
@ -374,7 +374,8 @@ static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw,
|
||||||
bit_mask(ctrl->ndiv_frac.width);
|
bit_mask(ctrl->ndiv_frac.width);
|
||||||
|
|
||||||
if (ndiv_frac != 0)
|
if (ndiv_frac != 0)
|
||||||
ndiv = (ndiv_int << ctrl->ndiv_int.shift) | ndiv_frac;
|
ndiv = ((u64)ndiv_int << ctrl->ndiv_int.shift) |
|
||||||
|
ndiv_frac;
|
||||||
}
|
}
|
||||||
|
|
||||||
val = readl(pll->pll_base + ctrl->pdiv.offset);
|
val = readl(pll->pll_base + ctrl->pdiv.offset);
|
||||||
|
@ -655,10 +656,6 @@ void __init iproc_pll_clk_setup(struct device_node *node,
|
||||||
memset(&init, 0, sizeof(init));
|
memset(&init, 0, sizeof(init));
|
||||||
parent_name = node->name;
|
parent_name = node->name;
|
||||||
|
|
||||||
clk_name = kzalloc(IPROC_CLK_NAME_LEN, GFP_KERNEL);
|
|
||||||
if (WARN_ON(!clk_name))
|
|
||||||
goto err_clk_register;
|
|
||||||
|
|
||||||
ret = of_property_read_string_index(node, "clock-output-names",
|
ret = of_property_read_string_index(node, "clock-output-names",
|
||||||
i, &clk_name);
|
i, &clk_name);
|
||||||
if (WARN_ON(ret))
|
if (WARN_ON(ret))
|
||||||
|
@ -690,10 +687,8 @@ void __init iproc_pll_clk_setup(struct device_node *node,
|
||||||
return;
|
return;
|
||||||
|
|
||||||
err_clk_register:
|
err_clk_register:
|
||||||
for (i = 0; i < num_clks; i++) {
|
for (i = 0; i < num_clks; i++)
|
||||||
kfree(pll->clks[i].name);
|
|
||||||
clk_unregister(pll->clk_data.clks[i]);
|
clk_unregister(pll->clk_data.clks[i]);
|
||||||
}
|
|
||||||
|
|
||||||
err_pll_register:
|
err_pll_register:
|
||||||
if (pll->asiu_base)
|
if (pll->asiu_base)
|
||||||
|
|
|
@ -268,7 +268,7 @@ static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary)
|
||||||
memcpy(table, stm32f42xx_gate_map, sizeof(table));
|
memcpy(table, stm32f42xx_gate_map, sizeof(table));
|
||||||
|
|
||||||
/* only bits set in table can be used as indices */
|
/* only bits set in table can be used as indices */
|
||||||
if (WARN_ON(secondary > 8 * sizeof(table) ||
|
if (WARN_ON(secondary >= BITS_PER_BYTE * sizeof(table) ||
|
||||||
0 == (table[BIT_ULL_WORD(secondary)] &
|
0 == (table[BIT_ULL_WORD(secondary)] &
|
||||||
BIT_ULL_MASK(secondary))))
|
BIT_ULL_MASK(secondary))))
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
|
@ -700,6 +700,22 @@ static const struct mtk_composite peri_clks[] __initconst = {
|
||||||
MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
|
MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static struct clk_onecell_data *mt8173_top_clk_data __initdata;
|
||||||
|
static struct clk_onecell_data *mt8173_pll_clk_data __initdata;
|
||||||
|
|
||||||
|
static void __init mtk_clk_enable_critical(void)
|
||||||
|
{
|
||||||
|
if (!mt8173_top_clk_data || !mt8173_pll_clk_data)
|
||||||
|
return;
|
||||||
|
|
||||||
|
clk_prepare_enable(mt8173_pll_clk_data->clks[CLK_APMIXED_ARMCA15PLL]);
|
||||||
|
clk_prepare_enable(mt8173_pll_clk_data->clks[CLK_APMIXED_ARMCA7PLL]);
|
||||||
|
clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_MEM_SEL]);
|
||||||
|
clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
|
||||||
|
clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_CCI400_SEL]);
|
||||||
|
clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_RTC_SEL]);
|
||||||
|
}
|
||||||
|
|
||||||
static void __init mtk_topckgen_init(struct device_node *node)
|
static void __init mtk_topckgen_init(struct device_node *node)
|
||||||
{
|
{
|
||||||
struct clk_onecell_data *clk_data;
|
struct clk_onecell_data *clk_data;
|
||||||
|
@ -712,19 +728,19 @@ static void __init mtk_topckgen_init(struct device_node *node)
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
|
mt8173_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
|
||||||
|
|
||||||
mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data);
|
mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data);
|
||||||
mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
|
mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
|
||||||
mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
|
mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
|
||||||
&mt8173_clk_lock, clk_data);
|
&mt8173_clk_lock, clk_data);
|
||||||
|
|
||||||
clk_prepare_enable(clk_data->clks[CLK_TOP_CCI400_SEL]);
|
|
||||||
|
|
||||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||||
if (r)
|
if (r)
|
||||||
pr_err("%s(): could not register clock provider: %d\n",
|
pr_err("%s(): could not register clock provider: %d\n",
|
||||||
__func__, r);
|
__func__, r);
|
||||||
|
|
||||||
|
mtk_clk_enable_critical();
|
||||||
}
|
}
|
||||||
CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8173-topckgen", mtk_topckgen_init);
|
CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8173-topckgen", mtk_topckgen_init);
|
||||||
|
|
||||||
|
@ -818,13 +834,13 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
|
||||||
{
|
{
|
||||||
struct clk_onecell_data *clk_data;
|
struct clk_onecell_data *clk_data;
|
||||||
|
|
||||||
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
|
mt8173_pll_clk_data = clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
|
||||||
if (!clk_data)
|
if (!clk_data)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
|
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
|
||||||
|
|
||||||
clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMCA15PLL]);
|
mtk_clk_enable_critical();
|
||||||
}
|
}
|
||||||
CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8173-apmixedsys",
|
CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8173-apmixedsys",
|
||||||
mtk_apmixedsys_init);
|
mtk_apmixedsys_init);
|
||||||
|
|
|
@ -530,19 +530,16 @@ static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||||
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
||||||
struct freq_tbl f = *rcg->freq_tbl;
|
struct freq_tbl f = *rcg->freq_tbl;
|
||||||
const struct frac_entry *frac = frac_table_pixel;
|
const struct frac_entry *frac = frac_table_pixel;
|
||||||
unsigned long request, src_rate;
|
unsigned long request;
|
||||||
int delta = 100000;
|
int delta = 100000;
|
||||||
u32 mask = BIT(rcg->hid_width) - 1;
|
u32 mask = BIT(rcg->hid_width) - 1;
|
||||||
u32 hid_div;
|
u32 hid_div;
|
||||||
int index = qcom_find_src_index(hw, rcg->parent_map, f.src);
|
|
||||||
struct clk *parent = clk_get_parent_by_index(hw->clk, index);
|
|
||||||
|
|
||||||
for (; frac->num; frac++) {
|
for (; frac->num; frac++) {
|
||||||
request = (rate * frac->den) / frac->num;
|
request = (rate * frac->den) / frac->num;
|
||||||
|
|
||||||
src_rate = __clk_round_rate(parent, request);
|
if ((parent_rate < (request - delta)) ||
|
||||||
if ((src_rate < (request - delta)) ||
|
(parent_rate > (request + delta)))
|
||||||
(src_rate > (request + delta)))
|
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
|
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
|
||||||
|
|
|
@ -190,7 +190,7 @@ static struct clk *clk_register_flexgen(const char *name,
|
||||||
|
|
||||||
init.name = name;
|
init.name = name;
|
||||||
init.ops = &flexgen_ops;
|
init.ops = &flexgen_ops;
|
||||||
init.flags = CLK_IS_BASIC | flexgen_flags;
|
init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE | flexgen_flags;
|
||||||
init.parent_names = parent_names;
|
init.parent_names = parent_names;
|
||||||
init.num_parents = num_parents;
|
init.num_parents = num_parents;
|
||||||
|
|
||||||
|
@ -303,6 +303,8 @@ static void __init st_of_flexgen_setup(struct device_node *np)
|
||||||
if (!rlock)
|
if (!rlock)
|
||||||
goto err;
|
goto err;
|
||||||
|
|
||||||
|
spin_lock_init(rlock);
|
||||||
|
|
||||||
for (i = 0; i < clk_data->clk_num; i++) {
|
for (i = 0; i < clk_data->clk_num; i++) {
|
||||||
struct clk *clk;
|
struct clk *clk;
|
||||||
const char *clk_name;
|
const char *clk_name;
|
||||||
|
|
|
@ -489,7 +489,7 @@ static int quadfs_pll_is_enabled(struct clk_hw *hw)
|
||||||
struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw);
|
struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw);
|
||||||
u32 npda = CLKGEN_READ(pll, npda);
|
u32 npda = CLKGEN_READ(pll, npda);
|
||||||
|
|
||||||
return !!npda;
|
return pll->data->powerup_polarity ? !npda : !!npda;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int clk_fs660c32_vco_get_rate(unsigned long input, struct stm_fs *fs,
|
static int clk_fs660c32_vco_get_rate(unsigned long input, struct stm_fs *fs,
|
||||||
|
@ -635,7 +635,7 @@ static struct clk * __init st_clk_register_quadfs_pll(
|
||||||
|
|
||||||
init.name = name;
|
init.name = name;
|
||||||
init.ops = quadfs->pll_ops;
|
init.ops = quadfs->pll_ops;
|
||||||
init.flags = CLK_IS_BASIC;
|
init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE;
|
||||||
init.parent_names = &parent_name;
|
init.parent_names = &parent_name;
|
||||||
init.num_parents = 1;
|
init.num_parents = 1;
|
||||||
|
|
||||||
|
@ -774,7 +774,7 @@ static void quadfs_fsynth_disable(struct clk_hw *hw)
|
||||||
if (fs->lock)
|
if (fs->lock)
|
||||||
spin_lock_irqsave(fs->lock, flags);
|
spin_lock_irqsave(fs->lock, flags);
|
||||||
|
|
||||||
CLKGEN_WRITE(fs, nsb[fs->chan], !fs->data->standby_polarity);
|
CLKGEN_WRITE(fs, nsb[fs->chan], fs->data->standby_polarity);
|
||||||
|
|
||||||
if (fs->lock)
|
if (fs->lock)
|
||||||
spin_unlock_irqrestore(fs->lock, flags);
|
spin_unlock_irqrestore(fs->lock, flags);
|
||||||
|
@ -1082,10 +1082,6 @@ static const struct of_device_id quadfs_of_match[] = {
|
||||||
.compatible = "st,stih407-quadfs660-D",
|
.compatible = "st,stih407-quadfs660-D",
|
||||||
.data = &st_fs660c32_D_407
|
.data = &st_fs660c32_D_407
|
||||||
},
|
},
|
||||||
{
|
|
||||||
.compatible = "st,stih407-quadfs660-D",
|
|
||||||
.data = (void *)&st_fs660c32_D_407
|
|
||||||
},
|
|
||||||
{}
|
{}
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -237,7 +237,7 @@ static struct clk *clk_register_genamux(const char *name,
|
||||||
|
|
||||||
init.name = name;
|
init.name = name;
|
||||||
init.ops = &clkgena_divmux_ops;
|
init.ops = &clkgena_divmux_ops;
|
||||||
init.flags = CLK_IS_BASIC;
|
init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE;
|
||||||
init.parent_names = parent_names;
|
init.parent_names = parent_names;
|
||||||
init.num_parents = num_parents;
|
init.num_parents = num_parents;
|
||||||
|
|
||||||
|
@ -513,7 +513,8 @@ static void __init st_of_clkgena_prediv_setup(struct device_node *np)
|
||||||
0, &clk_name))
|
0, &clk_name))
|
||||||
return;
|
return;
|
||||||
|
|
||||||
clk = clk_register_divider_table(NULL, clk_name, parent_name, 0,
|
clk = clk_register_divider_table(NULL, clk_name, parent_name,
|
||||||
|
CLK_GET_RATE_NOCACHE,
|
||||||
reg + data->offset, data->shift, 1,
|
reg + data->offset, data->shift, 1,
|
||||||
0, data->table, NULL);
|
0, data->table, NULL);
|
||||||
if (IS_ERR(clk))
|
if (IS_ERR(clk))
|
||||||
|
@ -582,7 +583,7 @@ static struct clkgen_mux_data stih416_a9_mux_data = {
|
||||||
};
|
};
|
||||||
static struct clkgen_mux_data stih407_a9_mux_data = {
|
static struct clkgen_mux_data stih407_a9_mux_data = {
|
||||||
.offset = 0x1a4,
|
.offset = 0x1a4,
|
||||||
.shift = 1,
|
.shift = 0,
|
||||||
.width = 2,
|
.width = 2,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -786,7 +787,8 @@ static void __init st_of_clkgen_vcc_setup(struct device_node *np)
|
||||||
&mux->hw, &clk_mux_ops,
|
&mux->hw, &clk_mux_ops,
|
||||||
&div->hw, &clk_divider_ops,
|
&div->hw, &clk_divider_ops,
|
||||||
&gate->hw, &clk_gate_ops,
|
&gate->hw, &clk_gate_ops,
|
||||||
data->clk_flags);
|
data->clk_flags |
|
||||||
|
CLK_GET_RATE_NOCACHE);
|
||||||
if (IS_ERR(clk)) {
|
if (IS_ERR(clk)) {
|
||||||
kfree(gate);
|
kfree(gate);
|
||||||
kfree(div);
|
kfree(div);
|
||||||
|
|
|
@ -406,7 +406,7 @@ static struct clk * __init clkgen_pll_register(const char *parent_name,
|
||||||
init.name = clk_name;
|
init.name = clk_name;
|
||||||
init.ops = pll_data->ops;
|
init.ops = pll_data->ops;
|
||||||
|
|
||||||
init.flags = CLK_IS_BASIC;
|
init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE;
|
||||||
init.parent_names = &parent_name;
|
init.parent_names = &parent_name;
|
||||||
init.num_parents = 1;
|
init.num_parents = 1;
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue