Merge branch 'x86-mrst-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-mrst-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, mrst: make mrst_timer_options an enum x86, mrst: make mrst_identify_cpu() an inline returning enum x86, mrst: add more timer config options x86, mrst: add cpu type detection x86: detect scattered cpuid features earlier
This commit is contained in:
Linus Torvalds
commit
f7ddc2b6cd
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@ -55,7 +55,6 @@ extern unsigned long apbt_quick_calibrate(void);
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extern int arch_setup_apbt_irqs(int irq, int trigger, int mask, int cpu);
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extern void apbt_setup_secondary_clock(void);
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extern unsigned int boot_cpu_id;
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extern int disable_apbt_percpu;
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extern struct sfi_timer_table_entry *sfi_get_mtmr(int hint);
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extern void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr);
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@ -13,6 +13,32 @@
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extern int pci_mrst_init(void);
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int __init sfi_parse_mrtc(struct sfi_table_header *table);
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/*
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* Medfield is the follow-up of Moorestown, it combines two chip solution into
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* one. Other than that it also added always-on and constant tsc and lapic
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* timers. Medfield is the platform name, and the chip name is called Penwell
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* we treat Medfield/Penwell as a variant of Moorestown. Penwell can be
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* identified via MSRs.
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*/
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enum mrst_cpu_type {
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MRST_CPU_CHIP_LINCROFT = 1,
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MRST_CPU_CHIP_PENWELL,
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};
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extern enum mrst_cpu_type __mrst_cpu_chip;
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static enum mrst_cpu_type mrst_identify_cpu(void)
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{
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return __mrst_cpu_chip;
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}
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enum mrst_timer_options {
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MRST_TIMER_DEFAULT,
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MRST_TIMER_APBT_ONLY,
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MRST_TIMER_LAPIC_APBT,
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};
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extern enum mrst_timer_options mrst_timer_options;
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#define SFI_MTMR_MAX_NUM 8
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#define SFI_MRTC_MAX 8
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@ -43,10 +43,11 @@
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#include <asm/fixmap.h>
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#include <asm/apb_timer.h>
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#include <asm/mrst.h>
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#define APBT_MASK CLOCKSOURCE_MASK(32)
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#define APBT_SHIFT 22
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#define APBT_CLOCKEVENT_RATING 150
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#define APBT_CLOCKEVENT_RATING 110
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#define APBT_CLOCKSOURCE_RATING 250
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#define APBT_MIN_DELTA_USEC 200
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@ -83,8 +84,6 @@ struct apbt_dev {
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char name[10];
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};
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int disable_apbt_percpu __cpuinitdata;
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static DEFINE_PER_CPU(struct apbt_dev, cpu_apbt_dev);
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#ifdef CONFIG_SMP
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@ -194,29 +193,6 @@ static struct clock_event_device apbt_clockevent = {
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.rating = APBT_CLOCKEVENT_RATING,
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};
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/*
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* if user does not want to use per CPU apb timer, just give it a lower rating
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* than local apic timer and skip the late per cpu timer init.
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*/
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static inline int __init setup_x86_mrst_timer(char *arg)
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{
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if (!arg)
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return -EINVAL;
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if (strcmp("apbt_only", arg) == 0)
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disable_apbt_percpu = 0;
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else if (strcmp("lapic_and_apbt", arg) == 0)
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disable_apbt_percpu = 1;
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else {
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pr_warning("X86 MRST timer option %s not recognised"
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" use x86_mrst_timer=apbt_only or lapic_and_apbt\n",
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arg);
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return -EINVAL;
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}
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return 0;
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}
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__setup("x86_mrst_timer=", setup_x86_mrst_timer);
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/*
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* start count down from 0xffff_ffff. this is done by toggling the enable bit
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* then load initial load count to ~0.
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@ -335,7 +311,7 @@ static int __init apbt_clockevent_register(void)
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adev->num = smp_processor_id();
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memcpy(&adev->evt, &apbt_clockevent, sizeof(struct clock_event_device));
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if (disable_apbt_percpu) {
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if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) {
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apbt_clockevent.rating = APBT_CLOCKEVENT_RATING - 100;
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global_clock_event = &adev->evt;
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printk(KERN_DEBUG "%s clockevent registered as global\n",
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@ -429,7 +405,8 @@ static int apbt_cpuhp_notify(struct notifier_block *n,
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static __init int apbt_late_init(void)
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{
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if (disable_apbt_percpu || !apb_timer_block_enabled)
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if (mrst_timer_options == MRST_TIMER_LAPIC_APBT ||
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!apb_timer_block_enabled)
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return 0;
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/* This notifier should be called after workqueue is ready */
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hotcpu_notifier(apbt_cpuhp_notify, -20);
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@ -450,6 +427,8 @@ static void apbt_set_mode(enum clock_event_mode mode,
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int timer_num;
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struct apbt_dev *adev = EVT_TO_APBT_DEV(evt);
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BUG_ON(!apbt_virt_address);
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timer_num = adev->num;
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pr_debug("%s CPU %d timer %d mode=%d\n",
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__func__, first_cpu(*evt->cpumask), timer_num, mode);
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@ -676,7 +655,7 @@ void __init apbt_time_init(void)
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}
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#ifdef CONFIG_SMP
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/* kernel cmdline disable apb timer, so we will use lapic timers */
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if (disable_apbt_percpu) {
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if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) {
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printk(KERN_INFO "apbt: disabled per cpu timer\n");
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return;
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}
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@ -586,6 +586,7 @@ static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
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if (c->extended_cpuid_level >= 0x80000007)
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c->x86_power = cpuid_edx(0x80000007);
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init_scattered_cpuid_features(c);
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}
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static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
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@ -741,7 +742,6 @@ static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
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get_model_name(c); /* Default name */
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init_scattered_cpuid_features(c);
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detect_nopl(c);
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}
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@ -25,8 +25,34 @@
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#include <asm/i8259.h>
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#include <asm/apb_timer.h>
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/*
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* the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
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* cmdline option x86_mrst_timer can be used to override the configuration
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* to prefer one or the other.
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* at runtime, there are basically three timer configurations:
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* 1. per cpu apbt clock only
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* 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only
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* 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast.
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*
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* by default (without cmdline option), platform code first detects cpu type
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* to see if we are on lincroft or penwell, then set up both lapic or apbt
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* clocks accordingly.
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* i.e. by default, medfield uses configuration #2, moorestown uses #1.
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* config #3 is supported but not recommended on medfield.
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*
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* rating and feature summary:
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* lapic (with C3STOP) --------- 100
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* apbt (always-on) ------------ 110
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* lapic (always-on,ARAT) ------ 150
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*/
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__cpuinitdata enum mrst_timer_options mrst_timer_options;
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static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
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static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
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enum mrst_cpu_type __mrst_cpu_chip;
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EXPORT_SYMBOL_GPL(__mrst_cpu_chip);
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int sfi_mtimer_num;
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struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX];
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@ -167,18 +193,6 @@ int __init sfi_parse_mrtc(struct sfi_table_header *table)
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return 0;
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}
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/*
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* the secondary clock in Moorestown can be APBT or LAPIC clock, default to
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* APBT but cmdline option can also override it.
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*/
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static void __cpuinit mrst_setup_secondary_clock(void)
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{
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/* restore default lapic clock if disabled by cmdline */
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if (disable_apbt_percpu)
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return setup_secondary_APIC_clock();
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apbt_setup_secondary_clock();
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}
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static unsigned long __init mrst_calibrate_tsc(void)
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{
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unsigned long flags, fast_calibrate;
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@ -195,6 +209,21 @@ static unsigned long __init mrst_calibrate_tsc(void)
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void __init mrst_time_init(void)
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{
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switch (mrst_timer_options) {
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case MRST_TIMER_APBT_ONLY:
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break;
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case MRST_TIMER_LAPIC_APBT:
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x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
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x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
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break;
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default:
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if (!boot_cpu_has(X86_FEATURE_ARAT))
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break;
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x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
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x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
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return;
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}
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/* we need at least one APB timer */
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sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
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pre_init_apic_IRQ0();
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apbt_time_init();
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@ -205,16 +234,21 @@ void __init mrst_rtc_init(void)
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sfi_table_parse(SFI_SIG_MRTC, NULL, NULL, sfi_parse_mrtc);
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}
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/*
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* if we use per cpu apb timer, the bootclock already setup. if we use lapic
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* timer and one apbt timer for broadcast, we need to set up lapic boot clock.
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*/
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static void __init mrst_setup_boot_clock(void)
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void __cpuinit mrst_arch_setup(void)
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{
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pr_info("%s: per cpu apbt flag %d \n", __func__, disable_apbt_percpu);
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if (disable_apbt_percpu)
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setup_boot_APIC_clock();
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};
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if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27)
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__mrst_cpu_chip = MRST_CPU_CHIP_PENWELL;
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else if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x26)
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__mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
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else {
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pr_err("Unknown Moorestown CPU (%d:%d), default to Lincroft\n",
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boot_cpu_data.x86, boot_cpu_data.x86_model);
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__mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
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}
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pr_debug("Moorestown CPU %s identified\n",
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(__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT) ?
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"Lincroft" : "Penwell");
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}
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/* MID systems don't have i8042 controller */
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static int mrst_i8042_detect(void)
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@ -232,11 +266,13 @@ void __init x86_mrst_early_setup(void)
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x86_init.resources.reserve_resources = x86_init_noop;
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x86_init.timers.timer_init = mrst_time_init;
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x86_init.timers.setup_percpu_clockev = mrst_setup_boot_clock;
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x86_init.timers.setup_percpu_clockev = x86_init_noop;
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x86_init.irqs.pre_vector_init = x86_init_noop;
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x86_cpuinit.setup_percpu_clockev = mrst_setup_secondary_clock;
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x86_init.oem.arch_setup = mrst_arch_setup;
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x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock;
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x86_platform.calibrate_tsc = mrst_calibrate_tsc;
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x86_platform.i8042_detect = mrst_i8042_detect;
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@ -250,3 +286,26 @@ void __init x86_mrst_early_setup(void)
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x86_init.mpparse.get_smp_config = x86_init_uint_noop;
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}
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/*
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* if user does not want to use per CPU apb timer, just give it a lower rating
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* than local apic timer and skip the late per cpu timer init.
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*/
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static inline int __init setup_x86_mrst_timer(char *arg)
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{
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if (!arg)
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return -EINVAL;
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if (strcmp("apbt_only", arg) == 0)
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mrst_timer_options = MRST_TIMER_APBT_ONLY;
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else if (strcmp("lapic_and_apbt", arg) == 0)
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mrst_timer_options = MRST_TIMER_LAPIC_APBT;
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else {
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pr_warning("X86 MRST timer option %s not recognised"
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" use x86_mrst_timer=apbt_only or lapic_and_apbt\n",
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arg);
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return -EINVAL;
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}
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return 0;
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}
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__setup("x86_mrst_timer=", setup_x86_mrst_timer);
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