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Renesas ARM Based SoC Drivers Updates for v4.14

Add R-Car D3 (r8a77995) support to the Renesas-specific SoC drivers
 - SoC identification
 - System controller
 - Reset controller
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJZf0DrAAoJENfPZGlqN0++LacP/jcymVeUMDpkkPTcoM6b37Qq
 ADSDdiR+1Szu29wtfNDTFUoAlh4UvlpAN93GGJLZ/iYsMDyZYIhcUhnE4l119fdy
 6iMwDhctXHlQ8VNhY0Z9MUXZyyN2Fu/9L2ZDJ2briM2xoNiMgdUYvMlsZI8ZaN1/
 JRmfP+lzCM25Rkdi9sLYolj8szaxbW9RgLBgvXD7ERJ5bsJRKGs6aDrJ2AXMZpwn
 BVOeughlPTxvv+NVFA1qZXWh63/7RjW5t6OMgHw3eNOABKv+o5YfdqOZAa8PHgn9
 LhNAkR90Il9hsGesWwHMKPuCgGHE0R/2nQppWM0xBWO/HfMRnpx8DEt+em/Kjpep
 uxex+bqMOJB0GksVWPM73ci1CQmQxKS6xrTXeTE9kiN+6WD+b0Fsntoz2XN62uJO
 df0z46N6T3I4jFc00vOBnXxCdgDCBCJLxtU8NFg8jzmGP+NkKxxYiwCEs1auKlLF
 CUVX+o8H4V9FKnD3h0/mNsNyw/gCw6TWXlyr/Ba6AjBuZ8TghhMjQ+zbY+xCN9sb
 IFONbr69pVBJ9N2ssGWdf2iLfa+JNcaJdEPZUkumgUlZ9M5RgS+yg3YoTFtlAO6R
 JN2uP1E20qBLlrvAu7pv9HQEim80RyDT2DU2a1qFNx32vhqfl6g3sccJJvGpzodj
 7y7per6KkpvUGrck0kAI
 =AO//
 -----END PGP SIGNATURE-----

Merge tag 'renesas-drivers-for-v4.14' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers

Pull "Renesas ARM Based SoC Drivers Updates for v4.14" from Simon Horman:

Add R-Car D3 (r8a77995) support to the Renesas-specific SoC drivers
- SoC identification
- System controller
- Reset controller

* tag 'renesas-drivers-for-v4.14' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  soc: renesas: rcar-rst: Add support for R-Car D3
  soc: renesas: rcar-sysc: Add support for R-Car D3 power areas
  soc: renesas: Add r8a77995 SYSC PM Domain Binding Definitions
  soc: renesas: Identify R-Car D3
zero-colors
Arnd Bergmann 2017-08-16 21:55:03 +02:00
commit f822e60085
10 changed files with 76 additions and 1 deletions

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@ -17,6 +17,7 @@ Required properties:
- "renesas,r8a7794-sysc" (R-Car E2)
- "renesas,r8a7795-sysc" (R-Car H3)
- "renesas,r8a7796-sysc" (R-Car M3-W)
- "renesas,r8a77995-sysc" (R-Car D3)
- reg: Address start and address range for the device.
- #power-domain-cells: Must be 1.

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@ -26,6 +26,7 @@ Required properties:
- "renesas,r8a7794-rst" (R-Car E2)
- "renesas,r8a7795-rst" (R-Car H3)
- "renesas,r8a7796-rst" (R-Car M3-W)
- "renesas,r8a77995-rst" (R-Car D3)
- reg: Address start and address range for the device.

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@ -3,7 +3,7 @@ config SOC_RENESAS
default y if ARCH_RENESAS
select SOC_BUS
select RST_RCAR if ARCH_RCAR_GEN1 || ARCH_RCAR_GEN2 || \
ARCH_R8A7795 || ARCH_R8A7796
ARCH_R8A7795 || ARCH_R8A7796 || ARCH_R8A77995
select SYSC_R8A7743 if ARCH_R8A7743
select SYSC_R8A7745 if ARCH_R8A7745
select SYSC_R8A7779 if ARCH_R8A7779
@ -13,6 +13,7 @@ config SOC_RENESAS
select SYSC_R8A7794 if ARCH_R8A7794
select SYSC_R8A7795 if ARCH_R8A7795
select SYSC_R8A7796 if ARCH_R8A7796
select SYSC_R8A77995 if ARCH_R8A77995
if SOC_RENESAS
@ -53,6 +54,10 @@ config SYSC_R8A7796
bool "R-Car M3-W System Controller support" if COMPILE_TEST
select SYSC_RCAR
config SYSC_R8A77995
bool "R-Car D3 System Controller support" if COMPILE_TEST
select SYSC_RCAR
# Family
config RST_RCAR
bool "R-Car Reset Controller support" if COMPILE_TEST

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@ -11,6 +11,7 @@ obj-$(CONFIG_SYSC_R8A7792) += r8a7792-sysc.o
obj-$(CONFIG_SYSC_R8A7794) += r8a7794-sysc.o
obj-$(CONFIG_SYSC_R8A7795) += r8a7795-sysc.o
obj-$(CONFIG_SYSC_R8A7796) += r8a7796-sysc.o
obj-$(CONFIG_SYSC_R8A77995) += r8a77995-sysc.o
# Family
obj-$(CONFIG_RST_RCAR) += rcar-rst.o

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@ -0,0 +1,31 @@
/*
* Renesas R-Car D3 System Controller
*
* Copyright (C) 2017 Glider bvba
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*/
#include <linux/bug.h>
#include <linux/kernel.h>
#include <linux/sys_soc.h>
#include <dt-bindings/power/r8a77995-sysc.h>
#include "rcar-sysc.h"
static struct rcar_sysc_area r8a77995_areas[] __initdata = {
{ "always-on", 0, 0, R8A77995_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
{ "ca53-scu", 0x140, 0, R8A77995_PD_CA53_SCU, R8A77995_PD_ALWAYS_ON,
PD_SCU },
{ "ca53-cpu0", 0x200, 0, R8A77995_PD_CA53_CPU0, R8A77995_PD_CA53_SCU,
PD_CPU_NOCR },
};
const struct rcar_sysc_info r8a77995_sysc_info __initconst = {
.areas = r8a77995_areas,
.num_areas = ARRAY_SIZE(r8a77995_areas),
};

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@ -41,6 +41,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = {
/* R-Car Gen3 is handled like R-Car Gen2 */
{ .compatible = "renesas,r8a7795-rst", .data = &rcar_rst_gen2 },
{ .compatible = "renesas,r8a7796-rst", .data = &rcar_rst_gen2 },
{ .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen2 },
{ /* sentinel */ }
};

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@ -283,6 +283,9 @@ static const struct of_device_id rcar_sysc_matches[] = {
#endif
#ifdef CONFIG_SYSC_R8A7796
{ .compatible = "renesas,r8a7796-sysc", .data = &r8a7796_sysc_info },
#endif
#ifdef CONFIG_SYSC_R8A77995
{ .compatible = "renesas,r8a77995-sysc", .data = &r8a77995_sysc_info },
#endif
{ /* sentinel */ }
};

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@ -58,6 +58,7 @@ extern const struct rcar_sysc_info r8a7792_sysc_info;
extern const struct rcar_sysc_info r8a7794_sysc_info;
extern const struct rcar_sysc_info r8a7795_sysc_info;
extern const struct rcar_sysc_info r8a7796_sysc_info;
extern const struct rcar_sysc_info r8a77995_sysc_info;
/*

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@ -144,6 +144,11 @@ static const struct renesas_soc soc_rcar_m3_w __initconst __maybe_unused = {
.id = 0x52,
};
static const struct renesas_soc soc_rcar_d3 __initconst __maybe_unused = {
.family = &fam_rcar_gen3,
.id = 0x58,
};
static const struct renesas_soc soc_shmobile_ag5 __initconst __maybe_unused = {
.family = &fam_shmobile,
.id = 0x37,
@ -199,6 +204,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
#ifdef CONFIG_ARCH_R8A7796
{ .compatible = "renesas,r8a7796", .data = &soc_rcar_m3_w },
#endif
#ifdef CONFIG_ARCH_R8A77995
{ .compatible = "renesas,r8a77995", .data = &soc_rcar_d3 },
#endif
#ifdef CONFIG_ARCH_SH73A0
{ .compatible = "renesas,sh73a0", .data = &soc_shmobile_ag5 },
#endif

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@ -0,0 +1,23 @@
/*
* Copyright (C) 2017 Glider bvba
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*/
#ifndef __DT_BINDINGS_POWER_R8A77995_SYSC_H__
#define __DT_BINDINGS_POWER_R8A77995_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A77995_PD_CA53_CPU0 5
#define R8A77995_PD_CA53_SCU 21
/* Always-on power area */
#define R8A77995_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A77995_SYSC_H__ */