ARM: 8647/2: nommu: dynamic exception base address setting
No-MMU dynamic exception base address configuration on CP15 processors. In the case of low vectors, decision based on whether security extensions are enabled & whether remap vectors to RAM CONFIG option is selected. For no-MMU without CP15, current default value of 0x0 is retained. Signed-off-by: afzal mohammed <afzal.mohd.ma@gmail.com> Tested-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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@ -11,6 +11,7 @@
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#include <linux/kernel.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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#include <asm/sections.h>
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#include <asm/page.h>
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#include <asm/setup.h>
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@ -22,6 +23,8 @@
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#include "mm.h"
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unsigned long vectors_base;
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#ifdef CONFIG_ARM_MPU
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struct mpu_rgn_info mpu_rgn_info;
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@ -278,15 +281,60 @@ static void adjust_lowmem_bounds_mpu(void) {}
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static void __init mpu_setup(void) {}
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#endif /* CONFIG_ARM_MPU */
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#ifdef CONFIG_CPU_CP15
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#ifdef CONFIG_CPU_HIGH_VECTOR
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static unsigned long __init setup_vectors_base(void)
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{
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unsigned long reg = get_cr();
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set_cr(reg | CR_V);
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return 0xffff0000;
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}
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#else /* CONFIG_CPU_HIGH_VECTOR */
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/* Write exception base address to VBAR */
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static inline void set_vbar(unsigned long val)
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{
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asm("mcr p15, 0, %0, c12, c0, 0" : : "r" (val) : "cc");
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}
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/*
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* Security extensions, bits[7:4], permitted values,
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* 0b0000 - not implemented, 0b0001/0b0010 - implemented
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*/
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static inline bool security_extensions_enabled(void)
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{
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return !!cpuid_feature_extract(CPUID_EXT_PFR1, 4);
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}
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static unsigned long __init setup_vectors_base(void)
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{
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unsigned long base = 0, reg = get_cr();
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set_cr(reg & ~CR_V);
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if (security_extensions_enabled()) {
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if (IS_ENABLED(CONFIG_REMAP_VECTORS_TO_RAM))
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base = CONFIG_DRAM_BASE;
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set_vbar(base);
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} else if (IS_ENABLED(CONFIG_REMAP_VECTORS_TO_RAM)) {
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if (CONFIG_DRAM_BASE != 0)
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pr_err("Security extensions not enabled, vectors cannot be remapped to RAM, vectors base will be 0x00000000\n");
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}
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return base;
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}
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#endif /* CONFIG_CPU_HIGH_VECTOR */
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#endif /* CONFIG_CPU_CP15 */
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void __init arm_mm_memblock_reserve(void)
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{
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#ifndef CONFIG_CPU_V7M
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vectors_base = IS_ENABLED(CONFIG_CPU_CP15) ? setup_vectors_base() : 0;
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/*
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* Register the exception vector page.
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* some architectures which the DRAM is the exception vector to trap,
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* alloc_page breaks with error, although it is not NULL, but "0."
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*/
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memblock_reserve(CONFIG_VECTORS_BASE, 2 * PAGE_SIZE);
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memblock_reserve(vectors_base, 2 * PAGE_SIZE);
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#else /* ifndef CONFIG_CPU_V7M */
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/*
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* There is no dedicated vector page on V7-M. So nothing needs to be
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@ -310,7 +358,7 @@ void __init adjust_lowmem_bounds(void)
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*/
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void __init paging_init(const struct machine_desc *mdesc)
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{
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early_trap_init((void *)CONFIG_VECTORS_BASE);
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early_trap_init((void *)vectors_base);
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mpu_setup();
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bootmem_init();
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}
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