Merge branch 'pci/host-iproc' into next
* pci/host-iproc: PCI: iproc: Skip check for legacy IRQ on PAXC buses PCI: iproc: Fix incorrect MSI address alignment PCI: iproc: Add support for the next-gen PAXB controller PCI: iproc: Add PAXBv2 binding info PCI: iproc: Add inbound DMA mapping support PCI: iproc: Add optional dma-ranges PCI: iproc: Make outbound mapping code more generic PCI: iproc: Remove redundant outbound properties PCI: iproc: Add PAXC v2 support PCI: iproc: Add PAXCv2 related binding PCI: iproc: Fix exception with multi-function devices PCI: iproc: Add BCMA type PCI: iproc: Do not reset PAXC when initializing the driver PCI: iproc: Improve core register population
This commit is contained in:
commit
f887e24e05
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@ -1,10 +1,17 @@
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* Broadcom iProc PCIe controller with the platform bus interface
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Required properties:
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- compatible: Must be "brcm,iproc-pcie" for PAXB, or "brcm,iproc-pcie-paxc"
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for PAXC. PAXB-based root complex is used for external endpoint devices.
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PAXC-based root complex is connected to emulated endpoint devices
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internal to the ASIC
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- compatible:
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"brcm,iproc-pcie" for the first generation of PAXB based controller,
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used in SoCs including NSP, Cygnus, NS2, and Pegasus
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"brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based
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controllers, used in Stingray
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"brcm,iproc-pcie-paxc" for the first generation of PAXC based
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controller, used in NS2
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"brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based
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controller, used in Stingray
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PAXB-based root complex is used for external endpoint devices. PAXC-based
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root complex is connected to emulated endpoint devices internal to the ASIC
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- reg: base address and length of the PCIe controller I/O register space
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- #interrupt-cells: set to <1>
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- interrupt-map-mask and interrupt-map, standard PCI properties to define the
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@ -19,6 +26,10 @@ Required properties:
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Optional properties:
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- phys: phandle of the PCIe PHY device
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- phy-names: must be "pcie-phy"
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- dma-coherent: present if DMA operations are coherent
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- dma-ranges: Some PAXB-based root complexes do not have inbound mapping done
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by the ASIC after power on reset. In this case, SW is required to configure
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the mapping, based on inbound memory regions specified by this property.
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- brcm,pcie-ob: Some iProc SoCs do not have the outbound address mapping done
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by the ASIC after power on reset. In this case, SW needs to configure it
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@ -29,11 +40,6 @@ effective:
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Required:
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- brcm,pcie-ob-axi-offset: The offset from the AXI address to the internal
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address used by the iProc PCIe core (not the PCIe address)
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- brcm,pcie-ob-window-size: The outbound address mapping window size (in MB)
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Optional:
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- brcm,pcie-ob-oarr-size: Some iProc SoCs need the OARR size bit to be set to
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increase the outbound window size
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MSI support (optional):
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@ -41,10 +47,19 @@ For older platforms without MSI integrated in the GIC, iProc PCIe core provides
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an event queue based MSI support. The iProc MSI uses host memories to store
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MSI posted writes in the event queues
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- msi-parent: Link to the device node of the MSI controller. On newer iProc
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platforms, the MSI controller may be gicv2m or gicv3-its. On older iProc
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platforms without MSI support in its interrupt controller, one may use the
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event queue based MSI support integrated within the iProc PCIe core.
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On newer iProc platforms, gicv2m or gicv3-its based MSI support should be used
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- msi-map: Maps a Requester ID to an MSI controller and associated MSI
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sideband data
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- msi-parent: Link to the device node of the MSI controller, used when no MSI
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sideband data is passed between the iProc PCIe controller and the MSI
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controller
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Refer to the following binding documents for more detailed description on
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the use of 'msi-map' and 'msi-parent':
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Documentation/devicetree/bindings/pci/pci-msi.txt
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Documentation/devicetree/bindings/interrupt-controller/msi.txt
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When the iProc event queue based MSI is used, one needs to define the
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following properties in the MSI device node:
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@ -80,9 +95,7 @@ Example:
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phy-names = "pcie-phy";
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brcm,pcie-ob;
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brcm,pcie-ob-oarr-size;
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brcm,pcie-ob-axi-offset = <0x00000000>;
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brcm,pcie-ob-window-size = <256>;
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msi-parent = <&msi0>;
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@ -54,6 +54,7 @@ static int iproc_pcie_bcma_probe(struct bcma_device *bdev)
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pcie->dev = dev;
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pcie->type = IPROC_PCIE_PAXB_BCMA;
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pcie->base = bdev->io_addr;
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if (!pcie->base) {
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dev_err(dev, "no controller registers\n");
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@ -563,6 +563,7 @@ int iproc_msi_init(struct iproc_pcie *pcie, struct device_node *node)
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}
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switch (pcie->type) {
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case IPROC_PCIE_PAXB_BCMA:
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case IPROC_PCIE_PAXB:
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msi->reg_offsets = iproc_msi_reg_paxb;
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msi->nr_eq_region = 1;
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@ -30,9 +30,15 @@ static const struct of_device_id iproc_pcie_of_match_table[] = {
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{
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.compatible = "brcm,iproc-pcie",
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.data = (int *)IPROC_PCIE_PAXB,
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}, {
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.compatible = "brcm,iproc-pcie-paxb-v2",
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.data = (int *)IPROC_PCIE_PAXB_V2,
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}, {
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.compatible = "brcm,iproc-pcie-paxc",
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.data = (int *)IPROC_PCIE_PAXC,
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}, {
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.compatible = "brcm,iproc-pcie-paxc-v2",
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.data = (int *)IPROC_PCIE_PAXC_V2,
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},
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{ /* sentinel */ }
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};
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@ -84,19 +90,6 @@ static int iproc_pcie_pltfm_probe(struct platform_device *pdev)
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return ret;
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}
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pcie->ob.axi_offset = val;
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ret = of_property_read_u32(np, "brcm,pcie-ob-window-size",
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&val);
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if (ret) {
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dev_err(dev,
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"missing brcm,pcie-ob-window-size property\n");
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return ret;
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}
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pcie->ob.window_size = (resource_size_t)val * SZ_1M;
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if (of_property_read_bool(np, "brcm,pcie-ob-oarr-size"))
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pcie->ob.set_oarr_size = true;
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pcie->need_ob_cfg = true;
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}
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return ret;
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}
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pcie->map_irq = of_irq_parse_and_map_pci;
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/* PAXC doesn't support legacy IRQs, skip mapping */
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switch (pcie->type) {
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case IPROC_PCIE_PAXC:
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case IPROC_PCIE_PAXC_V2:
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break;
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default:
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pcie->map_irq = of_irq_parse_and_map_pci;
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}
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ret = iproc_pcie_setup(pcie, &res);
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if (ret)
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File diff suppressed because it is too large
Load diff
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* endpoint devices.
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*/
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enum iproc_pcie_type {
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IPROC_PCIE_PAXB = 0,
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IPROC_PCIE_PAXB_BCMA = 0,
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IPROC_PCIE_PAXB,
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IPROC_PCIE_PAXB_V2,
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IPROC_PCIE_PAXC,
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IPROC_PCIE_PAXC_V2,
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};
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/**
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* iProc PCIe outbound mapping
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* @set_oarr_size: indicates the OARR size bit needs to be set
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* @axi_offset: offset from the AXI address to the internal address used by
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* the iProc PCIe core
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* @window_size: outbound window size
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* @nr_windows: total number of supported outbound mapping windows
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*/
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struct iproc_pcie_ob {
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bool set_oarr_size;
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resource_size_t axi_offset;
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resource_size_t window_size;
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unsigned int nr_windows;
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};
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/**
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* iProc PCIe inbound mapping
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* @nr_regions: total number of supported inbound mapping regions
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*/
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struct iproc_pcie_ib {
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unsigned int nr_regions;
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};
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struct iproc_pcie_ob_map;
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struct iproc_pcie_ib_map;
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struct iproc_msi;
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/**
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* @root_bus: pointer to root bus
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* @phy: optional PHY device that controls the Serdes
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* @map_irq: function callback to map interrupts
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* @ep_is_internal: indicates an internal emulated endpoint device is connected
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* @has_apb_err_disable: indicates the controller can be configured to prevent
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* unsupported request from being forwarded as an APB bus error
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*
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* @need_ob_cfg: indicates SW needs to configure the outbound mapping window
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* @ob: outbound mapping parameters
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* @ob: outbound mapping related parameters
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* @ob_map: outbound mapping related parameters specific to the controller
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*
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* @ib: inbound mapping related parameters
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* @ib_map: outbound mapping region related parameters
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*
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* @need_msi_steer: indicates additional configuration of the iProc PCIe
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* controller is required to steer MSI writes to external interrupt controller
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* @msi: MSI data
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*/
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struct iproc_pcie {
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struct device *dev;
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enum iproc_pcie_type type;
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const u16 *reg_offsets;
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u16 *reg_offsets;
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void __iomem *base;
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phys_addr_t base_addr;
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#ifdef CONFIG_ARM
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struct pci_bus *root_bus;
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struct phy *phy;
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int (*map_irq)(const struct pci_dev *, u8, u8);
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bool ep_is_internal;
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bool has_apb_err_disable;
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bool need_ob_cfg;
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struct iproc_pcie_ob ob;
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const struct iproc_pcie_ob_map *ob_map;
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struct iproc_pcie_ib ib;
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const struct iproc_pcie_ib_map *ib_map;
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bool need_msi_steer;
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struct iproc_msi *msi;
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};
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